Outline MOS Gate Dielectrics Incorporation of N Or F at the Si/Sio

Outline

•Scaling issues •Technology

•Reliability of SiO2

•Nitrided SiO2 •High k dielectrics

araswat tanford University 42 EE311 / Gate Dielectric

Incorporation of N or F at the Si/SiO2 Interface Incorporating nitrogen or ﬂuorine instead of hydrogen strengthens the

Si/SiO2 interface and increases the gate dielectric lifetime because Si-F and Si-N bonds are stronger than Si-H bonds. Nitroxides – Nitridation of SiO2 by NH3 , N2O, NO Poly-Si Gate – Growth in N2O – Improvement in reliability – Barrier to dopant penetration from poly-Si gate Oxide N or F – Marginal increase in K – Used extensively

Si substrate Fluorination – Fluorination of SiO2 by F ion implantation – Improvement in reliability – Increases B penetration from P+ poly-Si gate – Reduces K – Not used intentionally

– Can occur during processing (WF6 , BF2) araswat tanford University 43 EE311 / Gate Dielectric

1 Nitridation of SiO2 in NH3

• Oxidation in O2 to grow SiO2. • RTP anneal in NH3 maximize N at the interface and minimize bulk incorporation. • Reoxidation in O2 remove excess nitrogen from the outer surface • Anneal in Ar remove excess hydrogen from the bulk • Process too complex araswat tanford University 44 EE311 / Gate Dielectric

Nitridation in N2O or NO

Profile of N in SiO2 Stress-time dependence of gm degradation of a NMOS

SiO2

Ref. Bhat et.al IEEE IEDM 1994 (Ref: Ahn, et.al., IEEE Electron Dev. Lett. Feb. 1992)

•The problem of H can be circumvented by replacing NH3 by N2O or NO araswat tanford University 45 EE311 / Gate Dielectric

2 Oxidation of Si in N2O

N2O → N2 + O

N2O + O → 2NO

Ref: Okada, et.al., Appl. Phys. Lett. 63(2), 1993

•RTP oxidation shows N accumulation near the Si/SiO2 interface •Furnace oxidation shows almost uniform N proﬁle ⇒lower Qbd araswat tanford University 46 EE311 / Gate Dielectric

Dopant Penetration From Poly-Si Gate Thick gate oxide Thin gate oxide Thin nitrided gate oxide P+ Poly-Si Gate B B B

B in SiO2 SiOXNY Si Si Si

• Incorporation of nitrogen at the interface suppresses dopant diffusion

from gate poly-Si into the channel which can can cause VT shift. • The problem is more serious for P+ poly-Si as boron diffuses more

readily in SiO2. • It is desirable to use P+ gate for PMOS transistors, for scaled CMOS technology to minimize short channel effects

araswat tanford University 47 EE311 / Gate Dielectric

3 MOS Gate Dielectrics

Outline

•Scaling issues •Technology

•Reliability of SiO2

•Nitrided SiO2 •High k dielectrics

araswat tanford University 48 EE311 / Gate Dielectric

High-k MOS Gate Dielectrics

Ichannel ∝ charge x source injection velocity ∝ (gate oxide cap x gate overdrive) vinj ∝ Cox (VGS - VT) Esource µinj

Historically Cox has been increased by decreasing gate oxide thickness. It can also be increased by using a higher K dielectric K I "C " D ox thickness

40 Å 20 Å SiO2 K ≈ 4 Si N K ≈ 8 ! 3 4 Si

#tox Higher thickness -> reduced gate leakage JDT "e araswat tanford University 49 EE311 / Gate Dielectric !

4 Benefits of High-κ Gate Dielectrics

Low VDD leakage Gate VDD High leakage Gate e- 60 Å High-κ κ = 16 e- V V κ = 4 15 Å SiO2 DD DD - - source e drain source e drain !tox J DT " e channel channel Si substrate Si substrate

Higher-κ ﬁlm ⇒ thicker gate dielectric ⇒ lower leakage and power dissipation with the same capacitance !" A ') high $ C = 0 ⇒ t % () " t ox high() = ! SiO2 tox % ) " & SiO2 #

Historically Cox has been increased by decreasing gate oxide thickness. It can also be increased by using a higher K dielectric araswat tanford University 50 EE311 / Gate Dielectric

Alternatives to SiO2: Silicon Nitride

(Ref: Guo & Ma, IEEE Electron Dev. Lett. June. 1998)

 A factor of 2 increase in K  Reduction in bandgap ⇒ increased gate leakage araswat tanford University 51 EE311 / Gate Dielectric

5 Nitridation of Silicon

Thermal Nitridation of Si in NH3 Id - Vg of 1.5 µm Si3N4 gate NMOS

)

A 25 Å Si3N4

( Vg = 2V

r u 1.5V C

D 1V

0.5V

Drain Voltage (V)

(Ref: Moslehi & Saraswat, EEE Trans. Electron Dev. Feb. 1985)

• Si reacts with NH3 to grow Si3N4 – Excellent gate dielectric properties – Reaction needs very high temperatures • Si reacts with atomic nitrogen – Reaction temperature could be reduced using nitrogen plasma – More research needed • Several deposition methods under investigations, e.g., rapid thermal CVD, jet vapor deposition (JVD) araswat tanford University 52 EE311 / Gate Dielectric

Nitride / Nitroxide Sandwich Gate MOS

Id 1.2 nm EOT Gate dielectric

Ref: Q. Xiang, et.al., (AMD), IEDM 2000

• 1.2 nm EOT (Equivalent oxide thickness) gate dielectric can be formed by 1.2 nm EOT - thermally growing ultrathin oxinitride

- CVD of Si3N4 • Low gate leakage • 40 nm channel length CMOS demonstrated Ref: M. Bohr, (Intel), IEDM 2002. araswat tanford University 53 EE311 / Gate Dielectric

6 Requirements for the MOS gate dielectrics

• High dielectric constant ⇒ higher charge induced in the channel • Wide band gap ⇒ higher barriers ⇒ lower leakage • Ability to grow high purity films on Si with a clean interface. • High resistivity and breakdown voltage. • Low bulk and interfacial trap densities. • Compatibility with the substrate and top electrode. • minimal interdiffusion and reaction • minimal silicon reoxidation during growth and device processing

- even a thin SiO2 layer would deteriorate the Cgate significantly. • Thermal stresses — most oxides have larger thermal expansion coefficients than Si. • Good Si fabrication processing compatibility. • Stability at higher processing temperatures and environments • Ability to be cleaned, etched, etc.

araswat tanford University 54 EE311 / Gate Dielectric

Candidates for High K Gate Dielectrics

Dielectric Permittivity Band Gap !EC to Si (eV) SiO2 3.9 9 3.5 Si3N4 7 5.3 2.4 Al2O3 9 8.8 2.8 TiO2 80 3.5 0 Ta2O5 26 4.4 0.3 Y2O3 15 6 2.3 La2O3 30 6 2.3 HfO2 25 6 1.5 ZrO2 25 5.8 1.4 ZrSiO4 15 6 1.5 HfSiO4 15 6 -

Ref: Robertson, J., Appl. Surf. Sci. (2002) 190 (1-4), 2 • Higher K materials have lower bandgap • There are many performance, reliability and process integration issues yet to be solved • More research is needed to make these materials manufacturable

araswat tanford University 55 EE311 / Gate Dielectric

7 Thermodynamic Stability of High-K Dielectric Oxides

100 Å K ≈ 20 75 Å K ≈ 20

10 Å Si3N4

• Unstable oxides (e.g. TiO2, Ta2O5, BST) – React with Si to form SiO2 and silicides upon thermal annealing – Barrier (e.g. Si3N4) is required to prevent such a reaction • Dielectric stack: poly-Si/nitride/unstable oxide/nitride/Si substrate • A monolayer of nitride on both sides of gate dielectric already contributes 5 Å to the physical oxide thickness

• Stable oxides (e.g. HfO2, ZrO2, Al2O3) and their silicates (e.g. ZrSixOy) and aluminates (e.g. ZrAlxOy) – Do not react with Si upon thermal annealing (up to 1000°C) – May not require a barrier layer between Si and the metal oxide • simple structure: poly-Si/stable oxide/Si substrate araswat tanford University 56 EE311 / Gate Dielectric

Stability of Metal Oxides with Si

After Beyers,J. Appl. Phys. 56, 157, 1984 And Wang and Meyer J. Appl. Phys. 64, 4711 , 1988

araswat tanford University 57 EE311 / Gate Dielectric

8 Capacitance and Leakage for High-k Gate Dielectric Films Grown Using ALCVD

V 0 Germanium 10 Silicon 1m

) )

2 c 2 -2

m ±V/ 10 SiO m c 2 c / AB/ A

A ( F(

@( V

e -4 2.5 nm 1

10 + g B F e a 2 )

k V

g a

e -6 ALCVD @ a t

L 10

k n e e ZrO2 t r

a r

a -8 u e G 10 C

L 4 nm e t a 10-10 G 0 0.05 0.1 0.15 0.2 1/C' (µm2/fF) ox Equivalent SiO2 Thickness (nm)

Perkins, Saraswat and McIntyre, Chui, Kim, Saraswat and McIntyre, Stanford Univ. 2002 Stanford Univ. 2004

araswat tanford University 58 EE311 / Gate Dielectric

Atomic Layer CVD of Hi-κ Dielectric

Rotary Pump Pump Turbo Pump 4 4

MFC Loadlock ZrCl HfCl O 2

H Main Chamber Throttle Valve MFC MFC MFC Turbo Pump

Scrubber Rotary Pump Carrier Gas (N2) araswat McIntyre, Saraswat, Stanford tanford University 59 EE311 / Gate Dielectric

9 Atomic Layer Deposition

ZrCl4/HfCl4 (g)

Substrate

ON 1/4 cycle : Reactant A Injection of reactant A (ZrCl4/HfCl4) OFF (ZrCl4/HfCl4)

Reactant B

(H2O) 1 cycle araswat Time (sec) tanford University 60 EE311 / Gate Dielectric

Atomic Layer Deposition

* Zr " OH + ZrCl4 # Zr " O " ZrCl3 + HCl !

Saturated adsorption

Substrate

ON 2/4 cycle : Reactant A Purging (N ) (ZrCl /HfCl ) 2 4 4 OFF

Reactant B

(H2O) 1 cycle araswat Time (sec) tanford University 61 EE311 / Gate Dielectric

10 Atomic Layer Deposition

HCl (g) H2O (g)

Substrate

ON 3/4 cycle : Reactant A Injection of reactant B (ZrCl4/HfCl4) OFF (H2O)

Reactant B

(H2O) 1 cycle araswat Time (sec) tanford University 62 EE311 / Gate Dielectric

Atomic Layer Deposition

* * Zr " Cl + H 2O # Zr " OH + HCl !

ZrO2/HfO2 (s)

Substrate

ON 4/4 cycle : Reactant A Purging (N ) (ZrCl /HfCl ) 2 4 4 OFF

Reactant B

(H2O) 1 cycle araswat Time (sec) tanford University 63 EE311 / Gate Dielectric

11 Atomic Layer Deposition

ZrCl4/HfCl4 (g) Saturated adsorption

Substrate Substrate

HCl (g) H2O (g)

ZrO2/HfO2 (s)

Substrate Substrate

- Surface saturation controlled process - Layer-by-layer deposition process - Excellent film quality and step coverage

araswat tanford University 64 EE311 / Gate Dielectric

Microstructure of ALD HfO2 and HfO2 ZrO =29Å 2 ZrO2=43Å ZrO2=82Å As-deposited ALD-

ZrO2 is polycrystalline.

ZrO2 Chemical oxide

As-deposited ALD-HfO HfO2=28Å HfO2=45Å HfO2=62Å 2 is amorphous.

HfO2 It crystallizes upon high Chemical oxide temperature annealing

• There is always a thin layer of chemical SiO2 present at the interface • There are charges and trap states at various interfaces and grain boundaries araswat tanford University 65 EE311 / Gate Dielectric

12 High-k Gate Dielectric Can Also be Applied to Other Semiconductors

HR-XTEM 400 25 µm Ge hi-! pFET

/V-s) 30 m Ge hi- pFET 2 µ ! 300 100 µm Ge hi-! pFET

HfO2 200 Si Universal Mobility GeOxNy 100 Si hi-! pFET Ge 4 nm 0

Effective Mobility (cm 0.2 0.3 0.4 0.5 0.6 Effective Field (MV/cm)

Chui, et. al., IEDM 2002  Passivation of Ge with GeOxNy, ZrO2 and HfO2  1st demo of Ge MOSFETs with hi-κ  p-MOSFET with 3× mobility vs. Hi-k Si  Passivation of many other materials being experimented, e.g., carbon nanotubes, GaAs, etc. araswat tanford University 66 EE311 / Gate Dielectric

Issues With High k Dielectrics

• How good is the interface with Si? ⇒ mobility • Contamination of Si by metal atoms • Compatibility with gate electrode ⇒ metal gate • Device reliability and lifetime • Minimum EOT achievable • Technology integration

More research is needed to make these materials manufacturable and reliable

araswat tanford University 67 EE311 / Gate Dielectric

13 Reduced Mobility in High- K Gate Stacks

Ph ono ic n b m lo 1 1 1 1 µ u o Surface = + + C Roughness µeff µC µ ph µ sr

Eeff Electron Hole

araswat S. Saito, et al., IEEE IEDM, 2003. tanford University 68 EE311 / Gate Dielectric

Possible Sources for Reduced Mobility in High- K Gate Stacks

S. Saito, et al., IEEE IEDM, Washington, DC, Dec., 2003.

Extensive research is needed to understand these mechanisms and how to minimize their impact on device performance araswat tanford University 69 EE311 / Gate Dielectric

14 Effect of Interface states on CV curves Small density of states Large density of slow states

. Severe distortion, hysteresis and frequency dependence in C-V can be observed if large number of slow states are present

. This causes degradation in device properties, such as, Vt, mobility, etc.

araswat tanford University 70 EE311 / Gate Dielectric

Effect of Slow Dit states on CV Curves C

Responding to DC (Ideal)

Responding to DC (Actual) Effect of Cit Down- sweep Up-sweep Decreasing frequency

Responding to DC (Actual) Vt shift Acceptor -ve V . Measurement is like a regular C-V setup with a DC sweep from +ve to –ve followed by a DC sweep from –ve to +ve. . Hysteresis in C-V is due to the VERY slow states that do not empty out fast enough and cannot even respond to the slow DC sweep. araswat tanford University 71 EE311 / Gate Dielectric

15 Effect of Interface States on Mobility in High- K Gate Stacks

Eeff = 0.1 MV/cm

µeff, for HfO2 and SiO2 gate MOSFETs, along with their three components, Effect of interface traps on mobility. including the components limited by Coulombic scattering reduces the Coulomb scattering, µ , surface coul mobility roughness scattering, µsr, and the Ref: T. P. Ma, IEEE TED, Jan 04 phonon scattering, µph. araswat tanford University 72 EE311 / Gate Dielectric

High-K/Poly-Si Gate Transistors

. High-K/poly-Si gate transistors suffer from high VT, degraded channel mobility and poor drive performance . Phonon scattering limits channel mobility in high-K/poly-Si gate MOSFETs

araswat R. Chau, Intel, ICSICT 2004 tanford University 73 EE311 / Gate Dielectric

16 Metal Gate Screens Surface Phonon Scattering and Improves Mobility in High-K Transistors

1 1 = " µ i µi

R. Chau, Intel, ICSICT 2004 ! araswat tanford University 74 EE311 / Gate Dielectric

Annealing Crystallization of ALD-HfO2

In-situ anneal at 520°C using 30Å HfO2 on 25Å thermal SiO2. As-dep 10 min 20 min

50 min 60 min 70 min

. Upon annealing the amorphous films cryatsllize . Grain boundaries cause statistical variation in the properties

. By adding other elements (e.g. N, Al, Si) to HfO2 crystallization can be impeded araswat tanford University 75 EE311 / Gate Dielectric

17 Crystallization and Phase Separation

3.1 MX 20% SiO2 5555% (2 1S-1i2O) 2

HfO2 SiO2 Si

SiO2 SiO 5 nm 2

5 nm

65% SiO62 5(2%1-15 )SiO2 7755 % ( 2S1-1i8O) 2

. Non-uniformity of k-value leads to mobility degradation . This can occure in the case of silicates. G.B. et al., MRS 2004 5 nm 5 nm

B.Foran et al., ALD conference, 2004 araswat tanford University 76 EE311 / Gate Dielectric

Luigi Colombo, et al.,(T.I.) IWGI Nov 2003 Tokyo, Japan araswat tanford University 77 EE311 / Gate Dielectric

18 Mobility: N Incorporation in HfSiO

Hole Electron

Luigi Colombo, et al.,(T.I.) IWGI Nov 2003 Tokyo, Japan

araswat tanford University 78 EE311 / Gate Dielectric

Summary

•Scaling issues •Technology

•Reliability of SiO2

•Nitrided SiO2 •High k dielectrics

araswat tanford University 79 EE311 / Gate Dielectric