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Microelectronic Device Fabrication I Physics 445/545 Integration Microelectronic Device Fabrication I (Basic Chemistry and Physics of Semiconductor Device Fabrication) Physics 445/545 Integration Seminar Dec. 1 & 3, 2014 Chip Fabrication • From bare Si wafers to fully functional IC’s requires a complicated series of processing steps. • Cleanliness regimen must be rigorous. Jack Kilby inspecting a 300 mm wafer (courtesy TI) Moore’s Law The IC was invented independently in 1959 by Jack Kilby at TI and Robert Noyce at Fairchild (later one of the founders of Intel). In 1965, Intel co-founder Gordon Moore saw the future. His prediction, now popularly known as Moore’s Law, states that the number of transistors on a chip doubles about every two years. Gordon Moore’s original graph from 1965 Today, Intel leads the industry with: • A worldwide silicon fab. Advanced technologies, such as “tri-gate” for improved performance, in production today • Research into new technologies that will enable Intel to continue the 2- year cycle of Moore’s Law for the foreseeable future (courtesy: Intel Corp.) Challenge to Moore’s Law 45 40 35 Gate Delay 30 Interconnect Delay (Al/SiO2) 25 Interconnect Delay (Cu/Low k) 20 Delay (ps) Delay Sum of Delays (Al/SiO2) 15 Sum of Delays 10 (Cu/Low k) 5 0 650 500 350 250 180 130 100 Generation (nm) SIA Technology Roadmap SIA Technology Roadmap-update SIA Technology Roadmap “Acceleration” “More than Moore” Speculative Future Technologies Long range roadmap for logic CMOS transistor research Photolithography Photolithography: • Simple photo-transfer technique quite similar in many respects to ordinary black and white photography. • The master image or pattern resides on a “mask” or “reticule” that consists of a plate of quartz glass initially coated on one side by a thin layer of metallic chromium. • UV light is used to transfer the image into photoresist, which is then “developed” in a “yellow” room. Photolithography – cont’d Exposure Systems: • Contact: original concept, mask contacts substrate. • Proximity: improvement of contact to increase lifetime of mask and reduce “soft” defects. • Projection: current state-of-the-art – a fully configured system costs in the neighborhood of M$20. Photoresist: • Direct write: At one time was considered a competitor • Negative: remains in exposed area. to projection; however, although resolution is high, Developer: xylene or similar solvent throughput is too slow. (Direct write is used for • Positive: removed in exposed area. fabrication of photomasks.) Developer: strong alkaline solution Photoresist spin-coating • Photoresist is generally applied to wafers (or other kinds of substrates) by spin-coating. • As the term suggests, the idea is quite simple: a solution containing the resist is dispensed on a spinning substrate, which then spreads out to form a uniform layer. • Once the film is coated, it is baked to drive off excess solvent and stabilize the properties of the film. Wet Chemical Etching and Cleaning • Many wet chemical processes are still used in IC fabrication. • These require strong acids, viz., sulfuric, nitric, hydrochloric, etc., as well as weaker acids such as acetic and phosphoric. • Also strong bases, viz., potassium hydroxide or more recently tetramethyl ammonium hydroxide. Also weaker bases such as ammonium hydroxide. • Fluoride chemistry: hydrofluoric acid and ammonium fluoride • Solvents: acetone, isopropyl alcohol, etc. • Everyone working fab must be well aware of hazards and correct handling procedures!! Dry Etching Mask Mask Substrate Substrate Isotropic Etching: Anisotropic Etching: • Requires only the use of simple “wet” chemical • Includes a directional component, which ideally solutions. allows vertical etching without undercut. • Increases the width of photlithograpically defined • Cannot be achieved using simple chemical etching, features due to “undercut”. Rule of thumb: size of requires more sophisticated apparatus generally undercut equal to depth of etch. (can be much larger). requiring reduced pressure (a vacuum chamber) • Because anisotropic etching is generally carried out using gaseous chemicals it is “dry”. Plasma Etching Powered Electrode Powered Sheath Vacuum Glow Chamber Grounded Sheath Grounded Sheath • Plasma etching uses gaseous chemicals (viz., halocarbons, halogens, oxygen, etc.) that are activated by a radio frequency glow discharge. • The electrical discharge results in the formation of highly reactive free radical and ionic species that attack the substrate. Directionality + - + - + + - + - + + - + - - + - + + - + + - + + - + - + - - + - + + - + + - + - + + + + + - - + - + + + - - + - - + - - - + + + - + + + + + - + + + + + + - + - + - + - + - + + - - - + + - - + + - + + + + + + + + - + - - - + - - + - - - + - + + - + + - + + - + + + + - + + + - + + + - - + - - - - + - - - + + + + + + + + - + + - + + - + - - - + - - + - - + - - + - + + + + + + + + + + - - + - - + + + - + + + + - + - + - - - - - - - + - + - + + + + + - + - + + - + - + + - - - + + - + + - + - + + + - - - - - + + + + + + + + - - - + - + - - - + + - - - - • Directionality is due to a natural electric field that accelerates ions toward and solid surface. • This is due to the difference in mobility of electrons and ions and is similar to a depletion region formed at a metal- semiconductor contact!! Physical Vapor Deposition • Sputtering, e-beam and thermal evaporation processes are all examples of PVD. • In all cases the idea is the same, by some means a super- cooled vapor is formed from a source, typically solid, that migrates to condense as a thin film on a substrate. Chemical Vapor Deposition • CVD processes may be thermal or “plasma enhanced”. • In both cases, precursor gases react on the substrate surface to form a thin film. • It is critical that gas phase nucleation is avoided. This generally requires subatmospheric pressure, but not necessarily. Electrochemical Deposition Substrate = = SO4 SO4 Cu++ Cu++ Liquid Electrolyte = SO4 = SO4 ++ Cu++ Cu Copper Anode • Electrochemical deposition is merely application of old- fashioned electroplating to IC fabrication. • The deposition is unpatterned. (A patterned deposition is more correctly called “electroforming”.) • Very pure copper films having very good conformal coverage and feature filling are obtained by ECD. • A thin copper “seed” or “strike” layer is required to obtain adherent copper thin films by ECD; this layer must be deposited by some other means. Chemical Mechanical Polishing Spindle Wafer Transport Carrier Pad Capture Ring Table Wafer Insert • Slurry can be dripped on the pad from above or some systems introduce slurry through the pad. • The pad and insert are both compliant. This allows for a more even distribution of down force (or pressure). • Either vacuum or air pressure can be applied to the back of the wafer; however, in practice only the capture ring prevents the wafer being lost from the spindle during CMP. Kinematics of CMP rs ws r Spindle ro w Table • In principle, relative velocity magnitude between pad and wafer surfaces is uniform if the spindle and table rotate at the same angular velocity. • In practice the spin rates are made slightly different to avoid repetitive effects. Damascene Patterning Copper Barrier Layer Dielectric Copper Barrier Layer Two levels Dielectric Damascene Patterning: • Useful for materials such as copper, which cannot be successfully removed by conventional etching Copper Barrier Layer processes. • Requires stringent control of deposition process. Dielectric CMOS Process Flow: n-well formation photoresist n well implant p type silicon substrate n-well Masking: In a CMOS flow, both n-channel and p-channel devices must be fabricated. Since the substrate can only be of one doping type, regions of opposite doping type (in this case n-type) must be fabricated in order that devices of both polarities can be fabricated. (typical n-well implant: P+ 150 keV 1013-1014 cm-2) n well p type silicon substrate n-well Drive Diffusion: Of course, after implantation, the dopant must be activated and implant defects removed. In addition some diffusion is also necessary to insure that the n-type region is sufficiently deep for subsequent device fabrication. (typical n-well drive: 1050C 2 hours) CMOS Process Flow: n-well formation photoresist p type silicon substrate CMOS Process Flow: active area definition silicon nitride n well p type silicon substrate Pad Oxidation: In preparation for subsequent nitride deposition, a thin pad oxide is grown in a dry ambient. This is necessary to prevent defect formation during subsequent processing. LPCVD Nitride Deposition: A layer of silicon nitride is now deposited on the wafer surface. This will serve as a polish stop layer during shallow trench isolation. Alternatively, for LOCOS isolation it will serve both as an implant mask and oxidation mask. silicon nitride n well p type silicon substrate Active Area Masking: This mask defines the actual active area of finished transistors. CMOS Process Flow: active area definition CMOS Process Flow: shallow trench isolation n well p type silicon substrate Nitride/Oxide/Silicon Etch: Plasma etching (fluorine chemistry) is used to pattern nitride and oxide together. The silicon mesa (typical height: 300-500 nm) is fabricated using a chlorine/oxygen plasma etch. Once the etches are completed, the photoresist is stripped and a light chemical etch (a diluted, hydrofluoric, nitric, and acetic acid mixture) of the silicon surface is carried out to remove any plasma damage. This is followed by a thin oxidation (thickness: 20-30 nm ) so that a high quality interface
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