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Investigating 50Nm Channel Length Mosfets Containing a Dielectric

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Investigating 50Nm Channel Length Mosfets Containing a Dielectric Investigating 50nm channel length vertical MOSFETs containing a dielectric pocket, in a circuit environment D. Donaghy, S. Hall V. D. Kunz, C. H. de Groot, P. Ashburn Department of Electrical Engineering & Department of Electronics & Computer Science, Electronics, University of Liverpool, Liverpool, University of Southampton, Southampton SO17 L69 3BX, England 1BJ, England [email protected], [email protected] Abstract ESD/output buffer circuitry. Vertical structures without body contacts can half the transistor area [2]. The use of The performance potential of a 50nm channel length a dielectric pocket can reduce charge sharing between vertical MOSFET (vMOS) architecture is assessed by the body and the gate, thus allowing better threshold numerical simulation and the use of a circuit level voltage control or the channel length to be shortened model. The vMOS architecture incorporates some novel [3,4]. The pocket serves to suppress high leakage features, namely a dielectric pocket for suppression of currents due to the parasitic bipolar transistor. short channel effects and strategies to reduce parasitic Furthermore the pocket prevents boron diffusion into the overlap capacitance. The model allows quantification of body during device fabrication and so mitigates bulk performance limitations arising from drain and source punch-through. The vMOS is compared here to a 350nm overlap capacitances, which are shown to constitute up lateral production device for gate lengths of 50nm and to 60% of the total inverter capacitance. The model 350nm at the 350nm technology node for the condition allows some optimisation of performance from a circuit that power supply, VDD ~ 4 Vth (threshold voltage). perspective. Comparison between a production lateral device and the vMOS device is made at the 350nm node 2. VMOS device modelling although a 50nm channel can be realised at this node for the vMOS. The comparison is made for power supply, Fig. 1 shows the generic device architecture. A basic process to realize such a device is as follows. Body VDD ~ 4Vth. The dual channels and the reduced gate length aid the optimised 50nm vertical structure to regions are implanted for pMOS and nMOS followed by operate 70% times faster at VDD=1V than the 350nm growth of an oxide layer to form the dielectric pocket. A layer of polysilicon is then deposited to form the lateral device at VDD = 3V for a fan-out, N=10. For a loaded inverter, the performance advantages increases extrinsic drain contact. The turret is then etched. A to a factor of 3.5. The model further predicts that the silicon epitaxial layer is grown over the entire surface followed by gate oxide growth. vertical 50nm inverter at VDD = 1V has an energy-delay product an order of magnitude lower than the 350nm Turret width 350nm dgso lateral inverter at VDD=3V for a fan-out of 10. 1. Introduction Gate polysilicon Dielectric tox_d pocket Drain As technology is scaled down from the deep- dgdov submicrometer to decananometer region, device sizes and isolation spacings become comparable to depletion Lp layer widths. To reduce some of the short-channel Body problems a vertical structure containing a dielectric dgsov pocket between the body/drain junction is proposed. FILOX Vertical transistors can overcome scaling problems due Source Source to lithography resolution [1], whereby decananometer dgsol channels can be realised with relaxed lithography as the Fig 1: vMOS with dielectric pocket in drain region channel length is determined by the accuracy of ion- implantation or epitaxial growth. The 2001 ITRS A gate electrode is formed by deposition of poly-Si roadmap also recognises that vertical structures allow followed by appropriate implant. Dopant is out-diffused double gate devices thus increasing current drive. For from the drain polysilicon layer into the single crystal long channel devices there is some scope for reducing body to form the intrinsic drain contact. the device area while maintaining good off-state To obtain model parameters for circuit simulation the characteristics. This is ideal in memory circuits or in device was modelled using the ISE tool with the Van Dort quantum correction model, hydrodynamic model, turret top under gate poly-Si. The deposited oxide layer avalanche and band-to-band tunneling all switched on to on top of the turret serves to minimise gate to drain provide self-consistent data for short-channel, highly overlap capacitance caused by the poly-Si gate track doped devices. We assume the drain encroaches under over the top of the turret which provides for dual channel the dielectric pocket by 25nm and pocket thickness is set operation. The oxide thickness on the side of the poly-Si initially at 10nm. The turret width is set to a minimum extrinsic drain contact is set to 5nm and this is explained feature size of 350nm. The gate oxide thickness was later. varied as well as the body doping and the results of Vth and Ioff for the pMOS are summarized in figure 2. 3. Circuit model -02 0.2 10 A unity fan-out CMOS inverter circuit is shown in Fig. 2nm -03 0.1 O 3nm 10 4, where the parasitic capacitances are identified. f f - ) 0 No Pocket s -04 t V V a ( Pocket TH 10 -0.1 t e e g l e a -05 t -0.2 a V l 10 k DD o a v -0.3 g d -06 e l c o 10 M3 u M1 h -0.4 Cg Csg s r e -07 r Cdb r I e -0.5 n Cdp h leak 10 t T ( -0.6 A CM -08 Vin 10 ) Vo -0.7 -09 -0.8 10 1E+18 2E+18 3E+18 4E+18 Body doping (cm-3) Fig. 2 50nm channel length p-vMOS: Threshold M2 M4 voltage and off-state leakage current versus body doping for 2nm & 3nm gate oxide thickness. Figure 4. Circuit used as a test bench The threshold voltage was determined by linear extrapolation of transconductance, gm(Vgs) to zero. The Vth’s of the lateral device were +0.6/-0.74V. As off-state current was taken as the current measured at mentioned above, Vth for vMOS devices were obtained VDS = –1V and VGS = 0V. The leakage current is a from simulations to be +/- 0.3V for channel length L = minimum for a body doping of 3x1018cm-3; band-to-band 50nm and VDD = 1V. For VDD = 3V, Vth’s were set the tunnelling becomes increasingly dominant beyond the same as the lateral devices. Thus the devices considered minimum. A 2nm gate oxide and a body doping of 18 -3 operate with VDD ~ 4 Vth. 3x10 cm result in a threshold voltage of –0.32V and a The capacitive components of the device structure were leakage current of 1nA/ m at a drain to source voltage identified and lumped together into one single capacitor, of –1V. The dielectric pocket increases the threshold CT assigned to the output node, Vo. As the gate to voltage by 20mV and reduces the off-state leakage by source/drain overlap capacitances (Cgso/Cgdo), are about a factor of two. Depletion capacitance associated responsible for a significant portion of CT in a vertical with the drain contact is reduced by lower body doping structure, these capacitances were isolated from the total gate source/drain capacitance, (Cgs/Cgd). Other Drain contact 800nm capacitances considered were gate to substrate (included Contact regions with Csg), drain to bulk depletion region Cdb, dielectric Gate contact pocket capacitance, Cdp taking into account depletion Lower doped body region under the oxide, and finally the capacitance due to the 350nm drain contact (Fig.3). The voltage dependence of Gate polysilicon W depletion capacitance is linearised in the usual manner. Note that vertical devices benefit from being operated 350nm 350nm350nm 350nm ‘source down’ because this reduces the switched Source depletion capacitance compared to ‘drain down’ ie & Body source at the top of the turret. contact We define a circuit performance metric f where f is the fall time of Vo following an abrupt input voltage Figure 3. vMOS Plan – view step. The fall time can be calculated by considering the discharge of the effective load capacitance, CT, via the under the contact as shown by the shaded region in Fig. NMOS pull-down transistor, between 10 and 90% of the 3. The gate to source capacitance is reduced by full voltage swing as indicated in the model equations increasing the field oxide above the source [5]. Gate- below, where i(t) is the transient current through the drain capacitance is reduced by an oxide layer on the NMOS and other symbols have their usual meaning. Gate field dependence of mobility is included also. important component is that of the edge, defined by the 0.9VDD thickness of the drain poly-Si contact; dgdov in Fig.1. It dt 3 fs fus 3CT (VO )* is not possible to reduce the thickness of the poly-Si 0.1VDD i(t) layer to reduce dgdov as this will compromise drain series resistance. However, it should be possible to V C L. H 1 thicken the sidewall oxide by using poly SiGe or T 1 sat / dV fs / * o amorphous Si, which will oxidise faster, for the drain 2CoxWvsat VDD Vth 0 VDD Vth 1 VO VDsat contact and the leverage on performance is investigated V C L Dsat 1 in Fig.6. We estimate that a thickness of 5nm is realistic T dV fus * 2 o and this will reduce CT by 35% as shown in Fig.6. 2CoxW eff VDD VO VLt VDD Vth VO 2 ) 25 90 F f ( t ) 85 o CT The latter two equations represent the time the device is d 20 Gate:Drain overlap 80 g C saturated and unsaturated respectively.
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