DOCSLIB.ORG

A Fefet Based Processing-In-Memory Architecture for Solving Distributed Least-Square Optimizations

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
A Fefet Based Processing-In-Memory Architecture for Solving Distributed Least-Square Optimizations A FeFET Based Processing-In-Memory Architecture for Solving Distributed Least-Square Optimizations Insik Yoon1, Muya Chang1, Kai Ni2, Matthew Jerry2, Samantak Gangopadhyay1, Gus Smith3, Tomer Hamam1, 3 1 4 2 1 Vijaykrishnan Narayanan , Justin Romberg , Shih-Lien Lu , Suman Datta and Arijit Raychowdhury 1Georgia Institute of Technology, Atlanta, GA 30318, USA, 2University of Notre Dame, Notre Dame, IN 46556 USA 3Pennsylvania State University, State College, PA 16801 USA, 4TSMC, Taiwan Email: [email protected] /Phone: (678)643-5264 Introduction: HfO2 based ferroelectric FET (FeFET) has recently received great interest for its application in nonvolatile memory (NVM) [1]. Unlike conventional perovskite based ferroelectric materials, HfO2 is CMOS compatible and retains ferroelectricity for thin film with thickness around 10 nm. Therefore, successful integration of ferroelectric HfO2 into advanced CMOS technology makes this technology highly promising for NVM [1]. Moreover, by tuning the portion of switched ferroelectric domain, a FeFET can exhibit multiple intermediate states, which enables its application as an analog conductance in mixed-signal in-memory computing. Currently, such architectures have been applied to neuromorphic computing [2,3]. In this paper, we present a processing-in-memory (PIM) architecture with FeFETs and demonstrate how this can be used to solve a new class of optimization problems, in particular, distributed least square minimization. Device Operation and Modeling: The operation of FeFET is illustrated in Fig. 1. A positive/negative gate pulse erase/program the device by setting the ferroelectric polarization to point toward the channel/gate, which would set the device in low/high VTH state, respectively. The corresponding IDS-VGS characteristics for the two states are shown in Fig. 1(c). The separation of the two states indicate the memory window (MW), which is around 1.0 V for 10 nm HfO2 FeFET [1]. By applying a read pulse, VR, the two states can be differentiated by sensing the read current. The operation of FeFET as an analog conductance is different from the binary memory, in that a series of weak pulses are applied to set the device in desired state [2]. Out of the various pulse schemes proposed in [3] to tune the state, we use the pulse-amplitude modulation scheme (Fig. 2). Fig. 2(e) shows the applied pulse waveform. After each pulse, the percentage of switched ferroelectric domains is modified. The device states are shown in Fig. 2 (a)-(d). The device IDS-VGS corresponding to different states are shown in Fig. (f), which shows the intermediate states. The different states could be sensed by applying a read pulse, VR, the corresponding drain-to-source conductance, GDS, can be sensed. Fig. 2(g) shows the ideal GDS as a function of applied pulse numbers. GDS increases/decreases linearly and symmetrically with pulse numbers during potentiation/depression, respectively. The modeling framework for FeFET is shown in Fig. 3(a), which is composed of two sub-components: (1) baseline 45nm MOSFET, which is models QMOS(VMOS) in BSIM 4, and (2) the ferroelectric which models QFE(VFE) using the dynamic Preisach model. Fig. 4(a) and (b) show the measured and simulated ID-VG characteristics under potentiation and Fig. 5 shows FeFET channel conductance vs. the number of pulses from both simulations and experiments. Architecture and Application: In Fig. 6, we present the cell schematic of a differential FeFET memory cell that computes MAC on positive and negative numbers. One number is stored as a differential value of conductance in two FeFETs and the other number is applied as a differential input voltage to BL1 and BL2. As WL is asserted, differential current flows to the SL and an ADC digitizes the result. The vector is mapped to input voltage in BL and numbers in matrix are mapped to conductance in FeFET array. Fig.7 describes the end-to-end and vertically integrated model from device to architecture. We use this architecture to demonstrate distributed least-square optimization (with wide applications to signal processing, machine learning etc.) which solves an inverse problem of the form Az=B where A is the Grammian matrix of the basis and B is the observation vector [4]. We show that this problem can be mapped to iterative and distributed PIM where each unit is shown in Fig. 8. In Fig. 9, we compare compute latency and energy dissipation from a compute unit with FeFET memory vs. DAC resolution and number of bits per FeFET cell. The figure also shows the design-space exploration of ADC, DAC bit resolution and number of bits per FeFET cell in terms of latency and energy dissipation. At a system level, this results in 21X (3X) improvement in energy-efficiency (performance) compared to an SRAM+ALU architecture. We use the proposed algorithm and architecture for solving a classic problem of signal reconstruction from non-uniform samples: (1) Signal reconstruction from 1D EEG Signals and (2) Recovery of CT Images used in medical imaging in Fig. 10. We note more than 35dB PSNR after signal reconstruction. Conclusion: In this paper, we present a FeFET based processing in memory architecture and demonstrate its application to solving distributed least squares optimizations. References: [1] H. Mulaosmanovic et al., VLSI Tech. Dig., 2017. [2] S. Oh, et al., IEEE Electron Device Letters, pp. 732-735, 2017. [3] M. Jerry, et al., IEDM, 2017. [4] Ferreira et. al., Signal Processing, 1994. 978-1-5386-3028-0/18/$31.00 ©2018 IEEE Authorized licensed use limited to: Georgia Institute of Technology. Downloaded on June 28,2021 at 14:04:12 UTC from IEEE Xplore. Restrictions apply. (a) (e) (a) Model Components ERS G b c d V (a) S D d c b a G G n+ n+ p-Si (f) Preisach Model S D VFE QFE (VFE) (b) G n+ n+ S D S VG = VFE + VMOS (c) D n+ n+ I QFE (VFE) = QMOS (VMOS) p-Si p-Si BSIM 4 VR VMOS (c) QMOS (VMOS) S G ψS PGM D S D (g) VGS I Here b is the sample vector, z is the coefficient vector obtained (b) n+ n+ a G by stacking the coefficients ↵ (kx , ! x ,ky , ! y ), and A isreferred p-Si (b) Preisach Model Components MW to as the Grammian (Gram)S matrix of the basis. S D VR D (d) GWhen the size of A matrix islarge (as in most applications)VFEa Veff QFE G Static Preisach n+ n+ S D Delay Unit n+ direct solutionnis+not possible. Therefore, alternatively wefollow Model VGS an iterative approach, the Jacobi method. A general update of dVeff VFE - Veff P (V ) = mF(V ) + b : inner loop p-Si pz-Sini j th component at the k iteration is given as (4), where = FE eff eff th dt τ F(Veff) = Qotanh[a(Veff - VC)]: saturated loop B = A T A and c = A T b. Pulse num X Fig. 1. (a) Erase and (b) program operation Fig. 2. (a) – (d) Fek EFT− 1 states w.r.tk − 1 Fig. 3. (a) Components of compact model zj = B jj (cj − B jizi ) (4) Fig. 3: (a) simulated FerroFET channel conductance (b)Measured of binary FeFET memory. (c) Device IDS- ferroelectric domain switchingi =6 j . (e) for FeFEFerrToFET andchannel(bconductance) the dyna(GDS) asmica functionPreisachof pulse number. Some observations are worth emphasizing: (1) To update z k , j and pulse-amplitude modulation scheme [10]. For illustration, VGS characteristics after the program/erase. pulse amonlyplitvaluesudefrommodulpreviousatiiterationon scareheneed.me.(2) Columnsmodeofl components which is composed of a Fig. 2 illustrates the operation with pulse-amplitude modulation A are coupled only with neighboring frames, which leads to The separation of the two curves is the (f) IDS-VGS characteristics after each delay unischeme,t andwhichtheisstausedticin thisPrpapereisach. Fig. 2(e) modeshowsl. the applied simpler computation of B . Such a system maps naturally to ji pulse waveform. After each pulse, the percentage of switched a systolic PIM architecture with (1) near neighbor connections memory window. pulse. (g) measured w.r.t applied pulse ferroelectric domains is modified. The device states are shown and (2) embedded linear algebraic operators on the periphery number. in Fig. 2 (a)-(d).PoThetentdeiavicetionIDS-VGS correspondingDepressionto different -5 10-5 of the subarray – asPwillotenbetiadescribedtion in theDepfolloresswingion sections. 10 Simulation 3.00E-04 states are shown in Fig. 2 (f), which shows the intermediate Experiment 16 states V : 1.0V to 4.0V III. FERROFETS -MODELING AND EXPERIMENTAL states. The different states could be sensed16 sbytateapplyings a read V : 2.85V to 4.45V ERS E RS V ERIFI CATION with with ] 2.50E-04 pulse, VR, the corresponding drain-to-source conductance, GDS, -6 Step = 0.1 V Step = 0.05 V S linearity linearity 10 [ -6 HfO2 based ferroelectricSimulatFETion (FerroFET) has recently re- can be sensed. Fig. 2 (g) shows the ideal GDS as a function e 10 f r f r o c 2.00E-04 e o e ceived great interest for its application in nonvolatile memory of applied pulse numbers. GDS increases/decreases linearly ) Experimental e b b n s e a ) m a A s m with pulse number during potentiation/depression, respectively. u (NVM)t [8]. It is CMOS compatible and retains ferroelectricity e ( Data A -7 r n a u 1.50E-04 c ( c e D 10 n e r A symmetrical potentiation/depression is necessary for high n foru thin film with thickness around 10 nm. By tuning the portion I D I s l c e I -7 u n s d p I l of switched ferroelectric domain, a FerroFET can exhibit mul- accuracy computation. The experimental procedure is outside n 1.00E-04 10 u p tipleo intermediate states, which has been used in neuromorphic the scope of this paper and is described in [11].
Load more

Recommended publications
  • A Review on VDMOS As a Power MOSFET
    IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-ISSN: 2278-2834, p- ISSN: 2278-8735 A Review on VDMOS as a Power MOSFET Surbhi Sharma Vani Gupta1, Shivani Saxena2 1(M.TECH VLSI Banasthali Vidyapith) 2 (Assistant Professor, Dept. of Electronics, Banasthali Vidyapith) ABSTRACT: Today's electronics scenario finds itself with advancement in the field of fore most important component MOSFET. Though one step ahead of MOSFET, power MOSFETs find prime and superior choice for discrete components in circuits as well as today's integrated circuits. Moreover the revolutionary usage of power mosfet for significant power handling capacity lead to the discovery of a whole new genre of power Mosfet such as VDMOS. The progressive demand for high power radio frequency applications in wireless market and superior switching speed makes VDMOS a worthy choice. This paper actuates the working model of VDMOS with its characteristics and working parameters such as breakdown voltage, on-resistance etc. Keywords - Commutation, Power Mosfet, Transconductance,V-groove MOSFET, Vertical diffused MOSFET I. INTRODUCTION VDMOS has highly accomplished features of large input impedance, high switching speed and well heat stability. Its wide range of features have been applied to motor drive, switch power supply, automotive electronics and energy saving lamp and so on. The development of power MOSFETS began in 1970s VMOS (vertical MOSFET), after a decade DDMOS (double diffused MOSFET) technology was introduced. The VDMOS (vertically diffused MOSFET and LDMOS (laterally diffused MOSFET) were derived from the DDMOS technology. Thus the first generation of VDMOS was launched. Currently, the development of VDMOS in our country is still in its prime and the research is still in its maturing stage.
    [Show full text]
  • S Driving MOSPOWER® Fets
    s Siiiconix Application Note AN79-4 Driving MOSPOWER® FETs Dave Hoffman INTRODUCTION January 1979 Using VMOS Power FETs you can achieve performance When driving VMOS it must be kept in mind that the never before possible—if you drive them properly. This dynamic input impedance is very different than the static article describes circuits and suggests design methods to input impedance. The input of a VMOS device is capa- be used in order to obtain the performance from VMOS citive. The DC input impedance is very high but the AC that you need. input impedance varies with frequency. Because of this effect, the rise and fall times of VMOS are dependent on When designing with VMOS there are some facts that the output impedance of the circuit driving it. The first must be kept in mind in order to get optimum results approximation of the rise or fall time is simply with every circuit. The first fact is that VMOS is a very high frequency device. The cut-off frequency for all VMOS tror tf = 2.2 (1) FETs is several hundred megahertz. Most power designers are not used to designing with extremely high frequency where R.QUT is the output impedance of the drive circuit. devices because with bipoiars the frequency response This equation is valid only if the drain load resistance decreases as the power increases. The very high frequency is much larger than RQUT- Knowing this fact, along with response of VMOS is the basis for many of its advantages the fact that there is no storage or delay time with VMOS, but it must be kept in mind while designing.
    [Show full text]
  • CRYOGENIC CHARACTERISTICS of Igbts
    CRYOGENIC CHARACTERISTICS OF IGBTs by SHAOYONG YANG A thesis submitted to The University of Birmingham for the degree of DOCTOR OF PHILOSOPHY Electronic, Electrical and Computer Engineering School of Engineering The University of Birmingham July 2005 University of Birmingham Research Archive e-theses repository This unpublished thesis/dissertation is copyright of the author and/or third parties. The intellectual property rights of the author or third parties in respect of this work are as defined by The Copyright Designs and Patents Act 1988 or as modified by any successor legislation. Any use made of information contained in this thesis/dissertation must be in accordance with that legislation and must be properly acknowledged. Further distribution or reproduction in any format is prohibited without the permission of the copyright holder. Abstract Applications are now starting to emerge for superconducting devices in the areas of electrical power conversion and management, for example superconducting windings for marine propulsion motors, superconducting fault current limiters and superconducting magnet energy storage (SMES). Many of these applications also require power electronics, and it is therefore timely to consider the possibility of locating the power electronics in the cryo- system with the superconducting devices. Although significant work has been undertaken on the cryogenic operation of small devices, little has been published on larger devices, particularly the IGBT. This therefore forms the focus of this study. To examine the cryogenic performance of the sample devices, a cryo-system consisting of a cold chamber, a helium-filled compressor and vacuum pumps was built. Static, gate charge and switching tests were carried out on three types of IGBT modules, PT (punch-through), NPT (non-punch-through) and IGBT3 respectively, in the temperature range of 50 to 300 K.
    [Show full text]
  • Real-Time Reconfigurable Devices Implemented in UV-Light Programmable Floating-Gate CMOS
    Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS by Snorre Aunet June 2002 A dissertation submitted to the Norwegian University of Science and Technology Faculty of Information Technology, Mathematics and Electrical Engineering in partial fulfillment of the requirements for the degree of Doktor Ingenipr. ii iii Abstract This dissertation describes using theory, computer simulations and labora ­ tory measurements a new class of real time reconfigurable UV-programmable floating-gate circuits operating with current levels typically in the pA to fiA range, implemented in a standard double-poly CMOS technology. A new design method based on using the same basic two-MOSFET circuits extensively is proposed, meant for improving the opportunities to make larger FGUVMOS circuitry than previously reported. By using the same basic circuitry extensively, instead of different circuitry for basic digital functions, the goal is to ease UV-programming and test and save circuitry on chip and I/O-pads. Matching of circuitry should also be improved by using this approach. Compact circuitry can be made, reducing wiring and active components. Compared to earlier FGUVMOS approaches the number of transistors for implementing the CARRY’ of a FULL-ADDER is reduced from 22 to 2. A complete FULL-ADDER can be implemented using only 8 transistors. 2- MOSFET circuits able to implement CARRY’, NOR, NAND and INVERT functions are demonstrated by measurements on chip, working with power supply voltages ranging from 800 mV down to 93 mV. An 8-transistor FULL-ADDER might use 2500 times less energy than a FULL-ADDER implemented using standard cells in the same 0.6 fim CMOS technology while running at 1 MHz.
    [Show full text]
  • The Matching of Small Capacitors for Analog Vlsi
    THE MATCHING OF SMALL CAPACITORS FOR ANALOG VLSI Bradley A. Minch Chris Diorio Paul Hasler Carver Mead Computation and Neural Systems California Institute of Technology Pasadena, CA 91125 (818) 395-6996 [email protected] ABSTRACT b4 b3 62 bo The capacitor has become the dominant passive component bi for analog circuits designed in standard CMOS processes. 5-to-25 Thus, capacitor matching is a primary factor in determin- Decoder ing the precision of many analog circuit techniques. In ... ... this paper, we present experimental measurements of the vsweep mismatch between square capacitors ranging in size from ... ... 6 pm x 6 pm to 20 pm x 20 pm fabricated in a standard 2 pm double-poly CMOS process available through MOSIS. For a size of 6 pm x 6 pm, we have found that those capacitors that fell within one standard deviation of the mean matched to better than 1%.For the 20 pm x 20 pm size, we observed that those capacitors that fell within 1 standard deviation - of the mean matched to about 0.2%. Finally, we observed the effect of nonidentical surrounds on capacitor matching. Figure 1. Experimental setup used to measure ca- 1. INTRODUCTION pacitance mismatch. As analog circuits have been integrated with digital circuits [7] operating in the subthreshold region [8], using the ex- on CMOS chips, the capacitor has come to dominate ana- perimental setup depicted in Fig. 1. A vMOS transistor is log circuit design. In many ca.ses, resistors are unavailable in CMOS processes, and inductors are generally unattrac- a floating-gate MOS transistor with multiple control gates that capacitively couple into the floating gate, establish- tive for use in the design of all but RF or microwave cir- ing the floating gate’s voltage via a capacitive divider.
    [Show full text]
  • A Closed Form Analytical Model of Back-Gated 2-D Semiconductor Negative Capacitance Field Effect Transistors
    Received 21 November 2017; accepted 21 December 2017. Date of publication 27 December 2017; date of current version 15 January 2018. The review of this paper was arranged by Editor J. Kumar. Digital Object Identifier 10.1109/JEDS.2017.2787137 A Closed Form Analytical Model of Back-Gated 2-D Semiconductor Negative Capacitance Field Effect Transistors CHUNSHENG JIANG 1,2, MENGWEI SI 2, RENRONG LIANG1,JUNXU1, PEIDE D. YE 2 (Fellow, IEEE), AND MUHAMMAD ASHRAFUL ALAM2 (Fellow, IEEE) 1 Tsinghua National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua University, Beijing 100084, China 2 School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA CORRESPONDING AUTHORS: R. LIANG; M. A. ALAM (e-mail: [email protected]; [email protected]) This work was supported in part by the National Key Research and Development Program of China under Grant 2016YFA0302300 and Grant 2016YFA0200400, in part by the National Science and Technology Major Project of China under Grant 2016ZX02301001, in part by the National Natural Science Foundation of China under Grant 61306105, and in part by the Tsinghua University Initiative Scientific Research Program. ABSTRACT Steep slope (SS < 60 mV/dec at room temperature) negative capacitance (NC) FETs, based on the 2-D transition metal dichalcogenide semiconductor channel materials, may have a promising future in low-power electronics because of their high on-state current and very high on/off ratio. In this paper, we develop an analytically compact drain current model for long-channel back-gated 2-D NC-FETs by solving the classical drift-diffusion equations.
    [Show full text]
  • Trench Gate Power MOSFET: Recent Advances and Innovations Raghvendra Sahai Saxena and M
    Trench Gate Power MOSFET: Recent Advances and Innovations Raghvendra Sahai Saxena and M. Jagadesh Kumar Raghavendra S. Saxena and M. Jagadesh Kumar, "Trench Gate Power MOSFET: Recent Advances and Innovations", Advances in Microelectronics and Photonics, (Ed., S. Jit), Chapter 1, Nova Science Publishers, Inc. 400 Oser Avenue, Suite 1600, Hauppauge, NY 11788, USA, pp:1-23, 2012. Chapter 1 Trench Gate Power MOSFET: Recent Advances and Innovations Raghvendra Sahai Saxena and M. Jagadesh Kumar The trench gate MOSFET has established itself as the most suitable power device for low to medium voltage power applications by offering the lowest possible ON resistance among all MOS devices. The evolution of the trench gate power MOSFET has been discussed in this chapter, starting right from its beginnings to the recent trends. The innovations in the structural improvements to meet the requirements for an efficient operation, the progress in the fabrication process technology, the characterization methods and various reliability issues have been emphasized. I. INTRODUCTION From the very beginning in the history of mankind, there have been continuous and systematic scientific efforts to make our lives easy and comfortable. The development of power electronic devices is one of the steps towards that goal as these devices provide the means to control heavy electro- mechanical loads, industrial machines etc. to perform difficult tasks that would have been impossible otherwise. In these applications, a huge amount of electrical energy is required, which is acquired from an electrical source and stored in various elements and finally released in a controlled manner for our intended use of driving various devices and systems.
    [Show full text]
  • Neuron MOS Binary-Logic Integrated Circuits. II. Simplifying
    Neuron MOS Binary-Logic Integrated Circuits - Part II: Simplifying Techniques of Circuit Configuration and their Practical Applications 著者 大見 忠弘 journal or IEEE Transactions on Electron Devices publication title volume 40 number 5 page range 974-979 year 1993 URL http://hdl.handle.net/10097/48000 doi: 10.1109/16.210207 974 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40, NO. 5. MAY IYY3 Neuron MOS Binary-Logic Integrated Circuits- Part 11: Simplifying Techniques of Circuit Configuration and their Practical Applications Tadashi Shibata, Member, IEEE, and Tadahiro Ohmi, Member, IEEE Abstract-In Part I1 of the paper, the fundamental circuit 11. ELIMINATIONOF INPUT-STAGED/A CONVERTER ideas developed in Part I [l]are applied to practical circuits and the impact of neuron MOSFET on the implementation of The basic configuration of vMOS logic circuits pre- binary-logic circuits is examined. For this purpose, two tech- sented in Part I [I] employs a D/A converter circuit at the niques to simplify the circuit configurations are presented. It is input stage which translates the combination of binary in- shown that the input-stage D/A converter circuit in the basic put signals into a single multivalued variable Vpthat we configuration can be eliminated without any major problems, call a principal variable. Then the design of a vMOS bi- resulting in improved noise margins and speed performance. Then the design technique for symmetric functions is pre- nary-logic circuit reduces to the definition of a functional sented, which is especially important when the number of input form of the so-called universal literal function in the ter- variables is increased.
    [Show full text]
  • Investigating 50Nm Channel Length Mosfets Containing a Dielectric
    Investigating 50nm channel length vertical MOSFETs containing a dielectric pocket, in a circuit environment D. Donaghy, S. Hall V. D. Kunz, C. H. de Groot, P. Ashburn Department of Electrical Engineering & Department of Electronics & Computer Science, Electronics, University of Liverpool, Liverpool, University of Southampton, Southampton SO17 L69 3BX, England 1BJ, England [email protected], [email protected] Abstract ESD/output buffer circuitry. Vertical structures without body contacts can half the transistor area [2]. The use of The performance potential of a 50nm channel length a dielectric pocket can reduce charge sharing between vertical MOSFET (vMOS) architecture is assessed by the body and the gate, thus allowing better threshold numerical simulation and the use of a circuit level voltage control or the channel length to be shortened model. The vMOS architecture incorporates some novel [3,4]. The pocket serves to suppress high leakage features, namely a dielectric pocket for suppression of currents due to the parasitic bipolar transistor. short channel effects and strategies to reduce parasitic Furthermore the pocket prevents boron diffusion into the overlap capacitance. The model allows quantification of body during device fabrication and so mitigates bulk performance limitations arising from drain and source punch-through. The vMOS is compared here to a 350nm overlap capacitances, which are shown to constitute up lateral production device for gate lengths of 50nm and to 60% of the total inverter capacitance. The model 350nm at the 350nm technology node for the condition allows some optimisation of performance from a circuit that power supply, VDD ~ 4 Vth (threshold voltage). perspective.
    [Show full text]
  • Effect of Transition from PD to FD Operation on the Depletion Isolation Effect in Vertical Mosfets
    1 Effect of transition from PD to FD operation on the depletion isolation effect in vertical MOSFETs M. M. A. Hakim*, C. H. de Groot*, E. Gili*, T. Uchino*, S. Hall** and Peter Ashburn* Email:[email protected] *Microelectronics Group, University of Southampton, Highfield, Southampton, SO17 1BJ, UK **Dept. of EEE, University of Liverpool, Brownlow Hill, Liverpool L69 3GJ, UK Abstract-We study the effect of transition from However no work has been reported on FD VMOS partially depleted to fully depleted operation on the transistors or on the transition from PD to FD operation depletion isolation effect in vertical MOSFETs. The and the impact of substrate conduction during this impact of the body contact during this transition is transition. In this article a comprehensive investigation of exemplified. It is found that for pillar thickness > 120 the transition from PD to FD operation on the depletion nm the body contact is effective and for pillar isolation is done during source on top mode of operation. thickness < 60 nm is ineffective. In VMOS devices with Subsequently the impact of the body contact on depletion pillar thicknesses of 60-120 nm, even though the isolation is reported at various pillar thickness to gain existence of depletion isolation is identified, substrate physical insight into the behavior of thin pillar body conduction is found to reduce floating body effects and contacted VMOS devices. improve the breakdown voltage. We show that the reduction of the pillar thickness results in the gradual ineffectiveness of the body contact. The impact of substrate conduction on the breakdown voltage and kink behavior is also gradually reduced.
    [Show full text]
  • Condition Monitoring for Discrete Packaged Insulated Gate Bipolar
    CONDITION MONITORING FOR DISCRETE PACKAGED INSULATED GATE BIPOLAR TRANSISTORS IN POWER CONVERTERS by Syed Huzaif Ali APPROVED BY SUPERVISORY COMMITTEE: ___________________________________________ Dr. Bilal Akin, Chair ___________________________________________ Dr. Mehrdad Nourani ___________________________________________ Dr. Ghanshyamsinh Gohil ___________________________________________ Dr. Hoi Lee Copyright 2018 Syed Huzaif Ali All Rights Reserved Dedicated to my wife, sister, father and late mother CONDITION MONITORING FOR DISCRETE PACKAGED INSULATED GATE BIPOLAR TRANSISTORS IN POWER CONVERTERS by SYED HUZAIF ALI, BE, MS DISSERTATION Presented to the Faculty of The University of Texas at Dallas in Partial Fulfillment of the Requirements for the Degree of DOCTOR OF PHILOSOPHY IN ELECTRICAL ENGINEERING THE UNIVERSITY OF TEXAS AT DALLAS August 2018 ACKNOWLEDGMENTS I am indebted to my advisor, Dr. Bilal Akin, who provided me encouragement and support throughout the course of my PhD studies. During my study, his technical comments provided me with necessary guidance. I consider myself to be privileged for my successful PhD completion under his supervision. I would like to thank Dr. Mehrdad Nourani, Dr. Ghanshyamsinh Gohil, and Dr. Hoi Lee for their support as well as for serving as my dissertation committee members. Truly, without their valuable comments, and suggestions I could not have completed my dissertation. I would like to further thank all the administrative assistants of the electrical engineering department. I am also thankful to my colleagues, particularly, Mr. Enes Ugur, Mr. Kudra Baruti, and Mr. Fei Yang, for their contributions to this project. I am also highly indebted to Dr. Serkan Dusmez from Texas Instruments for his tremendous support and encouragement at every step while we worked together in the same laboratory.
    [Show full text]
  • Is Negative Capacitance FET a Steep-Slope Logic Switch?
    Corrected: Author correction ARTICLE https://doi.org/10.1038/s41467-019-13797-9 OPEN Is negative capacitance FET a steep-slope logic switch? Wei Cao 1 & Kaustav Banerjee 1* The negative-capacitance field-effect transistor(NC-FET) has attracted tremendous research efforts. However, the lack of a clear physical picture and design rule for this device has led to numerous invalid fabrications. In this work, we address this issue based on an unexpectedly 1234567890():,; concise and insightful analytical formulation of the minimum hysteresis-free subthreshold swing (SS), together with several important conclusions. Firstly, well-designed MOSFETs that have low trap density, low doping in the channel, and excellent electrostatic integrity, receive very limited benefit from NC in terms of achieving subthermionic SS. Secondly, quantum- capacitance is the limiting factor for NC-FETs to achieve hysteresis-free subthermionic SS, and FETs that can operate in the quantum-capacitance limit are desired platforms for NC-FET construction. Finally, a practical role of NC in FETs is to save the subthreshold and overdrive voltage losses. Our analysis and findings are intended to steer the NC-FET research in the right direction. 1 Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106, USA. *email: [email protected] NATURE COMMUNICATIONS | (2020)11:196 | https://doi.org/10.1038/s41467-019-13797-9 | www.nature.com/naturecommunications 1 ARTICLE NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-019-13797-9 lthough
    [Show full text]