F PRINCIPLES AND CIRCUITS Part 1 E Field-Effect by Ray Marston Ray Marston explains FET (Field-Effect ) basics in this opening episode of this new T four-part series. ield-Effect Transistors (FETs) are unipolar devices, and have two big advantages over bipolarF transistors: one is that they have a near-infinite input resistance and thus offer near- Figure 1. Comparison of infinite current and power transistor and gain; the other is that their JFET symbols, switching action is not marred notations, and by charge-storage problems, supply polarities. and they thus outperform most bipolars in terms of digi- tal switching speeds. Figure 2. Basic structure of Several different basic a simple n-channel JFET, types of FETs are available, showing how channel width is and this opening episode controlled via the gate bias. looks at their basic operating rial with a drain terminal at one end becomes so deep that conduction principles. Parts 2 to 4 of the and a source terminal at the other. A ceases. an n-channel FET, -ve for a p-channel series will show practical ways p-type control electrode or gate sur- Thus, the basic JFET of Figure 2 FET), a drain current (ID) flows and of using FETs. rounds (and is joined to the surface passes maximum current when its can be controlled via a gate-to-source of) the middle section of the n-type gate bias is zero, and its current is bias voltage VGS. bar, thus forming a p-n junction. reduced or ‘depleted’ when the gate (2). ID is greatest when VGS = 0, FET BASICS In normal use, the drain terminal bias is increased. It is thus known as and is reduced by applying a reverse is connected to a positive supply and a ‘depletion-type’ n-channel JFET. A bias to the gate (negative bias in an An FET is a three-terminal ampli- the gate is biased at a value that is p-channel version of the device can n-channel device, positive bias in a fying device. Its terminals are known negative (or equal) to the source volt- (in principle) be made by simply p-type). The magnitude of VGS need- as the source, gate, and drain, and age, thus reverse-biasing the JFET’s transposing the p and n materials. ed to reduce ID to zero is called the correspond respectively to the emit- internal p-n junction, and account- ‘pinch-off’ voltage, VP, and typically ter, base, and collector of a normal ing for its very high input imped- JFET DETAILS has a value between 2 and 10 volts. transistor. Two distinct families of ance. The magnitude of ID when VGS = 0 is FETs are in general use. The first of With zero gate bias applied, a Figure 3 shows the basic form of denoted IDSS, and typically has a these is known as ‘junction-gate’ current flow from drain to source via construction of a practical n-channel value in the range 2 to 20mA. types of FETs; this term generally a conductive ‘channel’ in the n-type JFET; a p-channel JFET can be made (3). The JFET’s gate-to-source being abbreviated to either JUGFET bar is formed. When negative gate by transposing the p and n materials. junction has the characteristics of a or (more usually) JFET. bias is applied, a high resistance All operate in the depletion silicon . When reverse-biased, The second family is known as region is formed within the junction, mode, as already described. Figure 4 gate leakage currents (IGSS) are only either ‘insulated-gate’ FETs or Metal and reduces the width of the n-type shows the typical transfer character- a couple of nA (1nA = .001µA) at Oxide Semiconductor FETs, and conduction channel and thus istics of a low-power n-channel JFET, room temperature. Actual gate sig- these terms are generally abbreviat- reduces the magnitude of the drain- and illustrates some important fea- nal currents are only a fraction of an ed to IGFET or MOSFET, respectively. to-source current. As the gate bias is tures of this type of device. The most nA, and the input impedance of the ‘N-channel’ and ‘p-channel’ versions increased, the ‘depletion’ region important characteristics of the JFET gate is typically thousands of of both types of FET are available, spreads deeper into the n-type chan- are as follows: megohms at low frequencies. The just as normal transistors are avail- nel, until eventually, at some ‘pinch- gate junction is shunted by a few pF, able in npn and pnp versions. Figure off’ voltage value, the depletion layer (1). When a JFET is connected to so the input impedance falls as fre- 1 shows the symbols and supply a supply with quency rises. polarities of both types of bipolar the polarity If the JFET’s gate-to-source junc- transistor, and compares them with shown in tion is forward-biased, it conducts both JFET versions. Figure 1 like a normal silicon diode. If it is Figure 2 illustrates the basic con- (drain +ve for excessively reverse-biased, it struction and operating principles of a simple n-channel JFET. It consists of a bar of n-type semiconductor mate- Figure 5. Figure 4. An n-channel Idealized JFET can be Figure 3. transfer used as a Construction characteristics voltage- of n-channel of an controlled JFET. n-channel . JFET.

1 MAY 2000/Nuts & Volts Magazine ©T & L Publications, Inc. All rights reserved. configuration can be terminal device, or may be internally obtained by using connected to the source, making a the basic Figure 11 three-terminal device. circuit. In practice, An important point about the fairly accurate bias- IGFET/MOSFET is that it is also avail- ing techniques (dis- able as an enhancement-mode device, cussed in Part 2 of in which its conduction channel is nor- this series) must be mally closed but can be opened by Figure 6. An n-channel Figure 7. An n-channel JFET can be used as used in these cir- applying forward bias to its gate. JFET can be used as a an electronic chopper. cuits. Figure 13 shows the basic con- voltage-controlled . struction and the symbol of the n- THE IGFET/MOSFET channel version of such a device. Here, no n-channel drain-to-source The second (and most impor- conduction path exists through the p- tant) family of FETs are those known type substrate, so with zero gate bias under the general title of IGFET or there is no conduction between drain Figure 8. An n-channel JFET MOSFET. In these FETs, the gate ter- and source; this feature is indicated in can be used as a minal is insulated from the semicon- the symbol of Figure 13(b) by the constant-current ductor body by a very thin layer of sil- gaps between source and drain. generator. icon dioxide, hence the title To turn the device on, significant ‘Insulated Gate Field Effect positive gate bias is needed, and Transistor,’ or IGFET. Also, the devices when this is of sufficient magnitude, it generally use a ‘Metal-Oxide Silicon’ starts to convert the p-type substrate avalanches like a . In stant as VDS is increased beyond the semiconductor material in their con- material under the gate into an n- either case, the JFET suffers no dam- knee value. Thus, when VDS is below struction, hence the alternative title channel, enabling conduction to take age if gate currents are limited to a the JFET’s knee value, the drain-to- of MOSFET. place. few mA. source terminals act as a resistor, RDS, Figure 12 shows the basic con- Figure 14 shows the typical trans- (4). Note in Figure 4 that, for with a value dictated by VGS, and can struction and the standard symbol of fer characteristics of an n-channel each VGS value, drain current ID rises thus be used as a voltage-variable the n-channel depletion-mode FET. It enhancement-mode IGFET/MOSFET, linearly from zero as the drain-to- resistor, as in Figure 5. resembles the JFET, except that its and Figure 15 shows the VGS/ID source voltage (VDS) is increased Typically, RDS can be varied from gate is fully insulated from the body curves of the same device when from zero up to some value at which a few hundred ohms (at VGS = 0) to of the FET (as indicated by the Figure powered from a 15V supply. Note a ‘knee’ occurs on each curve, and thousands of megohms (at VGS = VP), 12(b) symbol) but, in fact, operates that no ID current flows until the gate that ID then remains virtually con- enabling the JFET to be used as a on a slightly different principle to the voltage reaches a ‘threshold’ (VTH) voltage-controlled switch (Figure 6) JFET. value of a few volts, but that beyond or as an efficient ‘chopper’ (Figure 7) It has a normally-open n-type this value, the drain current rises in a that does not suffer from offset-volt- channel between drain and source, non-linear fashion. age or saturation-voltage problems. but the channel width is controlled by Also note that the transfer graph Also note in Figure 4 that when the electrostatic field of the gate bias. is divided into two characteristic VDS is above the knee value, the ID The channel can be closed by applying regions, as indicated (in Figure 14) by value is controlled by the VGS value suitable negative bias, or can be the dotted line, these being the ‘tri- and is almost independent of VDS, increased by applying positive bias. ode’ region and the ‘saturated’ i.e., the JFET acts as a voltage-con- In practice, the FET substrate may region. In the region, the trolled current generator. The JFET be externally available, making a four- device acts like a voltage-controlled can be used as a fixed-value current generator by either tying the gate to the source as in Figure 8(a), or by Figure 9. Basic n-channel Figure 12. common-source applying a fixed negative bias to the Construction (a) JFET circuit. gate as in Figure 8(b). Alternatively, it and symbol (b) can (when suitably biased) be used as of n-channel a voltage-to-current signal amplifier. depletion-mode (5). FET ‘gain’ is specified as IGFET/MOSFET. transconductance, gm, and denotes the magnitude of change of drain current with gate voltage, i.e., a gm of 5mA/V signifies that a VGS varia- tion of one volt produces a 5mA Figure 13. Construction (a) change in ID. Note that the form I/V is the inverse of the ohms formula, and symbol (b) so g measurements are often of n-channel m enhancement-mode expressed in ‘mho’ units. Usually, gm IGFET/MOSFET. Figure 10. Basic n-channel is specified in FET data sheets in common-drain terms of mmhos (milli-mhos) or (source-follower) µmhos (micro-mhos). Thus, a gm of JFET circuit. 5mA/V = 5-mmho or 5000-µmho. In most practical applications, the JFET is biased into the linear region and used as a voltage amplifi- er. Looking at the n-channel JFET, it can be used as a common source Figure 14. amplifier (corresponding to the bipo- Typical transfer lar npn common emitter amplifier) characteristics of by using the basic connections in n-channel enhancement-mode Figure 9. IGFET/MOSFET. Alternatively, the common drain or source follower (similar to the bipolar emitter follower) configura- tion can be obtained by using the Figure 11. Basic n-channel connections in Figure 10, or the com- common-gate JFET circuit. mon gate (similar to common base) ©T & L Publications, Inc. All rights reserved. Nuts & Volts Magazine/MAY 2000 2 MOSFET, the main signal current bottom of its V-groove caused an material. flows ‘laterally’ (see Figures 3, 12, excessive electric field at this point Several manufacturers produce and 13) through the device’s con- and restricted the device’s operating power that each comprise a ductive channel. This channel is very voltage. Subsequent to the original large array of parallel-connected low- thin, and maximum operating cur- VFET introduction, Intersil introduced power lateral (rather than horizontal) rents are consequently very limited their own version of the ‘VMOS’ tech- MOSFET cells that share the total (typically to maximum values in the nique, with a U-shaped groove (plus operating current equally between range 2 to 40mA). other modifications) that improved them; the device thus acts like a sin- In post-1970 times, many manu- device reliability and gave higher max- gle high-power MOSFET. These high- facturers have tried to produce viable imum operating currents and volt- power devices are known as lateral high-power/high-current versions of ages. In 1980, Siliconix added these MOSFETs or L-MOSFETs, and give a the FET, and the most successful of and other modifications to their own performance that is particularly useful these have relied on the use of a ‘ver- VFET devices, resulting in further in super-fi audio power amplifier tical’ (rather than lateral) flow of cur- improvements in performance. applications. rent through the conductive channel Note that, in parallel-connected Figure 15. of the device. One of the best known OTHER POWER FETs MOSFETs (as used in the internal Typical VGS/ID characteristics of of these devices is the ‘VFET,’ an structure of the HEXFET and L-MOS- n-channel enhancement-mode power MOSFET Several manufacturers have pro- FET devices described above), equal enhancement-mode which was first introduced by duced viable power FETs without current sharing is ensured by the con- IGFET/MOSFET Siliconix way back in 1976. using ‘V’- or ‘U’-groove techniques, duction channel’s positive tempera- Figure 17 shows the basic struc- but still relying on the vertical flow of ture coefficient; if the current in one ture of the original Siliconix VFET. It current between drain and source. In MOSFET becomes excessive, the has an essentially four-layer struc- the 1980s, Hitachi produced both p- resultant heating of its channel raises Figure 16. ture, with an n-type source layer at channel and n-channel power MOS- its resistance, thus reducing its cur- Internally- the top, followed by a p-type ‘body’ FET devices with ratings up to 8A and rent flow and tending to equalize it protected layer, an epitaxial n-type layer, and 200V; these devices were intended with that of other parallel-connected n-channel (at the bottom) an n-type drain layer. for use mainly in audio and low-RF MOSFETs. This feature makes such depletion-mode Note that a ‘V’ groove (hence the applications. power MOSFETs almost immune to IGFET/MOSFET. ‘VFET’ title) passes through the first Supertex of California and thermal runaway problems. two layers and into the third layer of Farranti of England pioneered the Today, a vast range of power the device, and is electrostatically development of a range of power MOSFET types are manufactured. connected (via an MOSFETS with the general title of ‘Low voltage’ n-channel types are insulating silicon ‘vertical DMOS.’ These featured high readily available with voltage/current dioxide film) to operating voltages (up to 650V), high ratings as high as 100V/75A, and the gate terminal. current rating (up to 16A), low on ‘high voltage’ ones with ratings as If the gate is resistance (down to 50 milliohms), high as 500V/25A. shorted to the and very fast operating speeds (up to One of the most important source, and the 2GHz at 1A, 500MHz at 10A). recent developments in the power- drain is made pos- Siemens of West Germany used a MOSFET field has been the introduc- itive, no drain-to- modified version of DMOS, known as tion of a variety of so-called ‘intelli- source current SIPMOS, to produce a range of n- gent’ or ‘smart’ MOSFETs with built- flows, because channel devices with voltage ratings in overload protection circuitry; these the diode formed as high as 1kV and with current rat- MOSFETs usually carry a distinctive by the p and n ings as high as 30A. registered trade name. Philips Figure 17. Basic structure of the VFET materials is One International solu- devices of this type are known as power device. reverse-biased. tion to the power MOSFET problem is TOPFETs (Temperature and Overload But if the gate is a device which, in effect, houses a Protected MOSFETs); Figure 19 resistor; in the saturated region, it made positive to the source, the vast array of parallel-connected low- shows (in simplified form) the basic acts like a voltage-controlled con- resulting electrostatic field converts power vertical MOSFETs or ‘cells’ internal circuitry and the circuit sym- stant-current generator. the area of p-type material adjacent which share the total current equally bol of the TOPFET. The basic n-channel MOSFETs of to the gate into n-type material, thus between them, and thus act like a sin- The Siemens version of the Figures 12 and 13 can — in principle creating a conduction channel in the gle high-power MOSFET, as indicated smart MOSFET is known as the PRO- — be converted to p-channel devices position shown in Figure 17 and in Figure 18. These devices are named FET. PROFET devices incorporate pro- by simply transposing their p and n enabling current to flow vertically HEXFET, after the hexagonal structure tection against damage from short materials, in which case their sym- from the drain to the source. of these cells, which have circuits, over temperature, overload, bols must be changed by reversing As the gate becomes more posi- a density of about 100,000 per and electrostatic discharge (ESD). the directions of their substrate tive, the channel width increases, square centimeter of semiconductor International Rectifier produce a arrows. enabling the A number of sub-variants of the drain-to-source MOSFET are in common use. The current to type known as ‘DMOS’ uses a dou- increase as the ble-diffused manufacturing tech- drain-to-source Figure 18. The IR HEXFET comprises nique to provide it with a very short resistance a balanced matrix of parallel- conduction channel and a conse- decreases. This connected low-power MOSFETs, quent ability to operate at very high basic VFET can which are equivalent to a single high-power MOSFET. switching speeds. Several other thus pass reason- MOSFET variants are described in the ably high cur- remainder of this opening episode. rents (typically Note that the very high gate up to 2A) with- impedance of MOSFET devices out creating makes them liable to damage from excessive current electrostatic discharges and, for this density within Figure 19. The basic reason, they are often provided with the channel internal circuitry (a) internal protection via integral regions. and the circuit symbol or zeners, as shown in the example The original (b) of the TOPFET in Figure 16. Siliconix VFET (Temperature and design of Figure Overload Protected VFET DEVICES 17 was success- MOSFET). ful, but imper- In a normal small-signal JFET or fect. The sharp 3 MAY 2000/Nuts & Volts Magazine ©T & L Publications, Inc. All rights reserved. an internally pro- known as CMOS, and rely on the use Figure 20. Normal circuit tected high-voltage of complementary pairs of MOSFETs. symbol of the IGBT high-current bipo- Figure 21 illustrates basic CMOS prin- (Insulated Gate Bipolar lar transistor out- ciples. The basic CMOS device com- Transistor). put. Figure 20 prises a p-type and n-type pair of shows the normal enhancement-mode MOSFETs, wired circuit symbol of in series, with their gates shorted range of smart n-channel MOSFET the IGBT. Devices of this type usually together at the input and their drains known as SMARTFETs; these incor- have voltage/current/power ratings tied together at the output, as porate protection against damage ranging from as low as shown in Figure 21(a). The pair are from short circuits, over tempera- 600V/6A/33W (in the device known meant to use logic-0 or logic-1 digital ture, overvoltage, and ESD. as the HGTD3N603), to as high as input signals, and Figures 21(b) and Finally, yet another recent and 1200V/520A/3000W (in the device 21(c), respectively, show the device’s important development in the n- known as the MG400Q1US51). equivalent circuit under these condi- channel power MOSFET field, has tions. been the production — by various CMOS BASICS When the input is at logic-0, the manufacturers — of a range of high upper (p-type) MOSFET is biased fully power devices known as IGBTs One major FET application is in on and acts like a closed switch, and (Insulated Gate Bipolar Transistors), digital ICs. The best known range of the lower (n-type) MOSFET is biased which have a MOSFET-type input and such devices use the technology off and acts like an open switch; the output is thus effectively connected to the positive supply line (logic-1) via a series resistance of about 100R. When the input is at logic-1, the MOSFET states are reversed, with Q1 acting like an open switch and Q2 acting like a closed switch, so the output is effectively connected to ground (logic-0) via 100R. Note in both cases that the entire signal cur- rent is fed to the load, and none is Figure 21. Basic CMOS circuit (a), and its equivalent with shunted off by the CMOS circuitry; (b) a logic-0 input and (c) a logic-1 input. this is a major feature of CMOS tech- nology. NV

©T & L Publications, Inc. All rights reserved. Nuts & Volts Magazine/MAY 2000 4 F PRINCIPLES AND CIRCUITS Part 2 E Field-Effect Transistors by Ray Marston Ray Marston looks at practical JFET circuits in this second episode of T this four-part series.

ast month’s opening applications, and is the most widely episode explained (among used of the three biasing methods. Figure 1. other things) the basic oper- A more accurate way of biasing Outline and ating principles of JFETs. the JFET is via the ‘offset’ system of connections of JFETs are low-power devices Figure 4(a), in which divider R1-R2 the 2N3819 and MPF102 JFETs. Lwith a very high input resistance applies a fixed positive bias to the and invariably operate in the deple- gate via Rg, and the source voltage tion mode, i.e., they pass maximum equals this voltage minus current when the gate bias is zero, VGS. If the gate voltage is Parameter 2N3918 MPF102 and the current is reduced (‘deplet- large relative to VGS, ID is ed’) by reverse-biasing the gate set mainly by Rs and is not V max (= max. drain-to-source voltage) 25V 25V terminal. greatly influenced by VGS DS Most JFETs are n-channel variations. This system thus VDG max (= max. drain-to-gate voltage) 25V 25V V max (= max. gate-to-source voltage) -25V -25V (rather than p-channel) devices. enables ID values to be set GS Two of the oldest and best known with good accuracy and IDSS (= drain-to-source current with VGS = 0V) 2-20mA 2-20mA n-channel JFETs are the 2N3819 without need for individual IGSS max (= gate leakage current at 25° C) 2nA 2nA and the MPF102, which are usually component selection. PT max (= max. power dissipation, in free air) 200mW 310mW housed in TO92 plastic packages Similar results can be with the connections shown in obtained by grounding the Figure 2. Basic characteristics of the 2N3819 and MPF102 n-channel JFETs. Figure 1; Figure 2 lists the basic gate and taking the bot- characteristics of these two devices. tom of Rs to a large negative volt- er with offset gate biasing. Overall This month’s article looks at age, as in Figure 4(b). voltage gain is about 0.95. C2 is a basic usage information and appli- The third type of biasing system bootstrapping and raises cations of JFETs. All practical cir- is shown in Figure 5, in which con- the input impedance to 44M, shunt- cuits shown here are specifically stant-current generator Q2 sets the ed by 10pF. designed around the 2N3819, but ID, irrespective of the JFET character- Figure 8 shows a hybrid (JFET will operate equally well when istics. This system gives excellent plus bipolar) source follower. Offset using the MPF102. biasing stability, but at the expense biasing is applied via R1-R2, and of increased circuit complexity constant-current generator Q2 acts JFET BIASING and cost. as a very high-impedance source In the three biasing systems load, giving the circuit an overall The JFET can be used as a lin- described, Rg can have any value up voltage gain of 0.99. C2 bootstraps Figure 3. Basic JFET ear amplifier by reverse-biasing its to 10M, the top limit being imposed R3’s effective impedance up to ‘self-biasing’ system. gate relative to its source terminal, by the volt drop across Rg caused thus driving it into the linear region. by gate leakage currents, which may Three basic JFET biasing techniques upset the gate bias. are in common use. The simplest of these is the ‘self-biasing’ system SOURCE FOLLOWER shown in Figure 3, in which the CIRCUITS Figure 4. gate is grounded via Rg, and any Basic JFET ‘offset-biasing’ current flowing in Rs drives the When used as linear , system. source positive relative to the gate, JFETs are usually used in either the thus generating reverse bias. source follower (common drain) or Suppose that an ID of 1mA is common-source modes. The source wanted, and that a VGS bias of -2V2 follower gives a very high input is needed to set this condition; the impedance and near-unity voltage correct bias can obviously be gain (hence the alternative title of obtained by giving Rs a value of ‘voltage follower’). 2k2; if ID tends to fall for some rea- Figure 6 shows a simple self- son, VGS naturally falls as well, and biasing (via RV1) source follower; thus makes ID increase and counter RV1 is used to set a quiescent R2 the original change; the bias is thus volt-drop of 5V6. The circuit’s actual self-regulating via negative feed- input-to-output voltage gain is 0.95. back. A degree of bootstrapping is In practice, the VGS value need- applied to R3 and increases its effec- ed to set a given ID varies widely tive impedance; the circuit’s actual between individual JFETS, and the input impedance is 10M shunted by only sure way of getting a precise ID 10pF, i.e., it is 10M at very low fre- value in this system is to make Rs a quencies, falling to 1M0 at about Figure 5. Basic JFET Figure 6. Self-biasing ‘constant-current’ biasing variable resistor; the system is, how- 16kHz and 100k at 160kHz, etc. system. ever, accurate enough for many Figure 7 shows a source follow- source-follower. Zin = 10M. 1 JUNE 2000/Nuts & Volts Magazine ©T & L Publications, Inc. All rights reserved. Figure 12. Common-source Figure 13. ‘Hybrid’ common-source Figure 8. Hybrid source follower. Zin = 500M. amplifier with offset gate biasing. amplifier.

1000M, which is shunted by the ance of 2M2. of 0.5V, 5V, and 50V. R4 protects JFET’s gate impedance; the input Q1’s gate against damage if exces- impedance of the complete circuit DC VOLTMETERS sive input voltage is applied to the is 500M, shunted by 10pF. circuit. Note then if the high effective Figure 14 shows a JFET used to To use the Figure 14 circuit, value of input impedance of this make a very simple and basic three- first trim RV2 to give zero meter circuit is to be maintained, the range DC voltmeter with a maxi- reading in the absence of an input output must either be taken to mum FSD sensitivity of 0.5V and an voltage, and then connect an accu- external loads via an additional input impedance of 11M1. Here, rate 0.5V DC to the input and trim emitter follower stage (as shown R6-RV2 and R7 form a potential RV1 to give a precise full-scale dotted in the diagram) or must be divider across the 12V supply and — meter reading. Repeat these adjust- taken only to fairly high imped- if the R7-RV2 junction is used as the ments until consistent zero and full- Figure 7. Source follower with ance loads. circuit’s zero-voltage point — sets scale readings are obtained; the offset biasing. Zin = 44M. the top of R6 at +8V and the bot- unit is then ready for use. COMMON SOURCE tom of R7 at -4V. Q1 is used as a In practice, this very simple cir- AMPLIFIERS source follower, with its gate cuit tends to drift with variations in grounded via the R1 to R4 network supply voltage and temperature, Figure 9 shows a simple self- and is offset biased by taking its and fairly frequent trimming of the biasing common source amplifier; source to -4V via R5; it consumes zero control is needed. Drift can be RV1 is used to set a quiescent about 1mA of drain current. greatly reduced by using a zener- 5V6 across R3. The RV1-R2 bias- In Figure 14, R6-RV2 and Q1-R5 stabilized 12V supply. ing network is AC-decoupled via act as a Wheatstone bridge net- Figure 15 shows an improved C2, and the circuit gives a voltage work, and RV2 is adjusted so that low-drift version of the JFET volt- gain of 21dB (= x12), and has a the bridge is balanced and zero cur- meter. Q1 and Q2 are wired as a ±3dB frequency response that rent flows in the meter in the differential amplifier, so any drift spans 15Hz to 250kHz and an absence of an input voltage at Q1 occurring on one side of the circuit input impedance of 2M2 shunted gate. Any voltage applied to Q1 is automatically countered by a simi- by 50pF. (This high shunt value is gate then drives the bridge out of lar drift on the other side, and due to Miller feedback, which balance by a proportional amount, good stability is obtained. The cir- multiplies the JFET’s effective which can be read directly on the cuit uses the ‘bridge’ principle, with Figure 9. Simple self-biasing gate-to-drain capacitance by the meter. Q1-R5 forming one side of the common-source amplifier. circuit’s x12 Av value.) R1 to R3 form a range multipli- bridge and Q2-R6 forming the Figure 10 shows a simple self- er network that — when RV1 is cor- other. Q1 and Q2 should ideally be biasing headphone amplifier that rectly adjusted — gives FSD ranges a matched pair of JFETs, with IDSS can be used with headphone impedances of 1k0 or greater. It has a built-in volume control (RV1), has an input impedance of 2M2, and can use any supply in the 9V to 18V range. Figure 11 shows a self-biasing add-on pre-amplifier that gives a voltage gain in excess of 20dB, has a bandwidth that extends beyond 100kHz, and has an input impedance of 2M2. It can be Figure 10. Simple headphone used with any amplifier that can Figure 14. Simple three-range amplifier. provide a 9V to 18V power DC voltmeter. source. JFET common source ampli- fiers can — when very high biasing Figure 15. accuracy is needed — be designed Low-drift using either the ‘offset’ or ‘con- three-range stant-current’ biasing technique. DC volt- Figures 12 and 13 show circuits of meter. these types. Note that the ‘offset’ circuit of Figure 12 can be used with supplies in the range 16V to 20V only, while the hybrid circuit of Figure 13 can be used with any supply in the 12V to 20V range. Both circuits give a voltage gain of Figure 11. General-purpose 21dB, a ±3dB bandwidth of 15Hz add-on pre-amplifier. to 250kHz, and an input imped- ©T & L Publications, Inc. All rights reserved. Nuts & Volts Magazine/JUNE 2000 2 3mV to 300mV large DC negative control voltage is RMS). fed to Q1’s gate; Q1 thus acts as a The circuit can high resistance under this condition, accept input signal so only a small part of the input sig- levels up to a maxi- nal is fed to Q2’s base, and the cir- mum of 500mV cuit gives low overall gain. RMS Q1 and R4 Thus, the output level stays are wired in series fairly constant over a wide range of to form a voltage- input signal levels; this characteris- controlled attenua- tic is useful in cassette recorders, tor that controls intercoms, and telephone ampli- Figure 17. Voltage-controlled the input signal fiers, etc. amplifier/attenuator. level to common Finally, Figure 19 shows a JFET Figure 16. VLF astable multivibrator. emitter amplifier used to make a DC-to-AC converter tive control voltage is fed to Q2, which has its output buffered or ‘chopper’ that produces a square- values matched within 10%. The cir- Q1 gate, the JFET acts like a near- via emitter follower Q3. wave output with a peak amplitude cuit is set up in the same way as infinite resistance and causes zero Q3’s output is used to generate equal to that of the DC input volt- that of Figure 14. signal attenuation, so the circuit (via C5-R9-D1-D2-C4-R5) a DC con- age. gives high overall gain but, when trol voltage that is fed back to Q1’s In this case, Q1 acts like an MISCELLANEOUS the gate bias is zero, the FET acts gate, thus forming a DC negative- electronic switch that is wired in JFET CIRCUITS like a low resistance and causes feedback loop that automatically series with R1 and is gated on and heavy signal attenuation, so the cir- adjusts the overall voltage gain so off at a 1kHz rate via the Q2-Q3 To conclude this month’s arti- cuit gives an overall signal loss. that the output signal level tends to astable circuit, thus giving the DC-to- cle, Figures 16 to 19 show a miscel- Intermediate values of signal remain constant as the input signal AC conversion. Note that Q1’s gate- laneous collection of useful JFET cir- attenuation and overall gain or loss level is varied, as follows. drive signal amplitude can be varied cuits. The Figure 16 design is that can be obtained by varying the con- When a very small input signal via RV1; if too large a drive is used, of a very-low-frequency (VLF) trol voltage value. is applied to the circuit, Q3’s output Q1’s gate-to-source junction starts astable or free-running multivibrator; Figure 18 shows how this volt- signal is also small, so negligible DC to avalanche, causing a small spike its on and off periods are controlled age-controlled attenuator technique control voltage is fed to Q1’s gate; voltage to break through the drain by C1-R4 and C2-R3, and R3 and R4 can be used to make a ‘constant Q1 thus acts as a low resistance and give an output even when no can have values up to 10M. volume’ amplifier that produces an under this condition, so almost the DC input is present. With the values shown, the cir- output signal level change of only full input signal is applied to Q2 To prevent this, connect a DC cuit cycles at a rate of once per 20 7.5dB when the input signal level is base, and the circuit gives high over- input and then trim RV1 until the seconds, i.e., at a frequency of varied over a 40dB range (from all gain. output is just on the verge of 0.05Hz; start button S1 When a large input decreasing; once set up in this way, must be held closed for signal is applied to the cir- the circuit can be reliably used to Figure 18. Constant-volume amplifier. at least one second to cuit, Q3’s output signal chop voltages as small as a fraction initiate the astable tends to be large, so a of a millivolt. NV action. Figure 17 shows — in basic form — how a JFET and a 741 op-amp can be used to make a voltage-controlled ampli- fier/attenuator. The op- amp is used in the inverting mode, with its voltage gain set by the R2/R3 ratio, and R1 and the JFET are used as a voltage-controlled input attenuator. Figure 19. DC-to-AC converter or ‘chopper’ circuit. When a large nega-

3 JUNE 2000/Nuts & Volts Magazine ©T & L Publications, Inc. All rights reserved. F PRINCIPLES AND CIRCUITS E Part 3 by Ray Marston Field-Effect Transistors Ray Marston looks at practical MOSFET and CMOS circuits in this penultimate episode of T this four-part series.

art 1 of this series explained (among other things) the basic operating principles of the MOSFET (or IGFET), and pointed Figure 1. Pout that complementary enhance- Symbol of the Figure 2. Standard symbols of ment-mode pairs of these devices dual-gate or form the basis of the digital tech- (a) three-pin and (b) four-pin n-channel enhancement-mode nology known as CMOS. MOSFET. MOSFETs. The present episode of the series looks at practical applications bias. This ‘normally open-circuit’ MOSFETs are some- of MOSFETs and CMOS-based action is implied by the gaps times provided with MOSFET devices. between source and drain in the integral protection device’s standard symbol, shown in via diodes or zen- A MOSFET INTRODUCTION Figure 2(a), which depicts an n- ers. channel MOSFET (the arrow head MOSFETs are available in both is reversed in a p-channel device). THE 4007UB depletion-mode and enhancement- In some devices, the semiconduc- Figure 3. Typical transfer characteristics of mode versions. Depletion-mode tor substrate is made externally The easiest and 4007UB n-channel enhancement-mode MOSFETs. types give a performance similar to available, creating a ‘four-terminal’ cheapest practical a JFET, but with a far higher input MOSFET, as shown in Figure 2(b). way of learning about enhance- The 4007UB usage rules are resistance (i.e., with a far higher Figure 3 shows typical transfer ment-mode MOSFETs is via a simple. In any given application, all low-frequency input impedance). characteristics of an n-channel 4007UB IC, which is the simplest unused IC elements must be dis- Some depletion-mode enhancement-mode MOSFET, and member of the popular CMOS abled. Complementary pairs of MOSFETs are equipped with two Figure 4 shows the VGS/ID curves ‘4000-series’ digital IC range, and MOSFETs can be disabled by con- independent gates, enabling the of the same device when powered actually houses six useful MOSFETs necting them as standard CMOS drain-to-source currents to be con- from a 15V supply. Note that no in a single 14-pin DIL package. inverters (i.e., gate-to-gate and trolled via either one or both of significant ID current flows until the Figure 5 shows the functional source-to-source) and tying their the gates; these devices (which are gate voltage rises to a threshold diagram and pin numbers of the inputs to ground, as shown in often used as signal mixers in VHF (VTH) value of a few volts but that, 4007UB, which houses two com- Figure 7. tuners) are known as dual-gate or beyond this value, the drain current plementary pairs of independently- Individual MOSFETs can be dis- tetrode MOSFETs, and use the sym- rises in a non-linear fashion. accessible MOSFETs and a third abled by tying their source to their bol shown in Figure 1. Also note that the Figure 3 complementary MOSFET pair that substrate and leaving the drain Most modern MOSFETs are graph is divided into two character- is connected as a standard CMOS open circuit. In use, the IC’s input enhancement-mode devices, in istic regions, as indicated by the inverter stage. terminal must not be allowed to which the drain-to-source conduc- dotted line; these being the ‘tri- Each of the IC’s three indepen- rise above VDD (the supply voltage) tion channel is closed when the ode’ region, in which the MOSFET dent input terminals is internally or fall below VSS (zero volts). gate bias is zero, but can be acts like a voltage-controlled resis- connected to the standard CMOS To use an n-channel MOSFET, opened by applying a forward gate tor, and the ‘saturated’ region,’ in protection network shown in the source must be tied to VSS, which it acts like a voltage- Figure 6. either directly or via a current-limit- controlled constant-current Within the IC, Q1, Q3, and Q5 ing resistor. To use a p-channel generator. are p-channel MOSFETs, and Q2, MOSFET, the source must be tied Because of their very Q4, and Q6 are n-channel types. to VDD, either directly or via a cur- high input resistances, Note that the performance graphs rent-limiting resistor. MOSFETs are vulnerable to of Figures 3 and 4 actually apply to damage via electrostatic dis- the individual n-channel devices charges; for this reason, within this CMOS IC.

Figure 5. Functional diagram of the 4007UB dual CMOS pair plus inverter. Figure 6. Internal- Figure 4. Typical VGS/ID protection network characteristics of 4007UB n-channel (within dotted lines) on enhancement-mode MOSFET. each input of the 4007UB.

1 JULY 2000/Nuts & Volts Magazine ©T & L Publications, Inc. All rights reserved. Figure 8. Method of biasing n-channel 4007UB MOSFETs for use as a linear inverting amplifier (with Figure 7. Individual 4007UB complementary pairs medium input can be disabled by connecting them as CMOS impedance). Figure 9. High impedance inverters and grounding their inputs. version of the inverting amplifier.

Figure 12. Circuit (a), truth table (b), and symbol (c) of the basic CMOS digital inverter.

Figure 10. Methods of biasing n-channel 4007UB MOSFET as Figure 11. Bootstrapped source a unity-gain non-inverting follower has ultra-high input can thus be used as a direct significant quiescent current. amplifier or source follower. impedance. replacement in many small-signal Figure 13 shows the typical bipolar transistor circuits. drain-current (ID) transfer character- an n-channel MOSFET as a unity- istics of the circuit under this condi- LINEAR OPERATION gain non-inverting common-drain THE CMOS INVERTER tion; ID is zero when the input is at amplifier or source follower. zero or full supply volts, but rises To fully understand the opera- The MOSFET gate is biased at A major application of to a maximum value (typically tion and vagaries of CMOS circuit- half-supply volts by the R2-R3 enhancement-mode MOSFETs is in 0.5mA at 5V, or 10.5mA at 15V) ry, it is necessary to understand divider, and the source terminal the basic CMOS inverting stage of when the input is at roughly half- the linear characteristics of basic automatically takes up a quiescent Figure 12(a), in which an n-channel supply volts, under which condition MOSFETs, as shown in the graph value that is slightly more than VTH and a p-channel pair of MOSFETs both MOSFETs of the inverter are of Figure 4. below the gate value. are wired in series but share com- biased equally. Note that negligible drain cur- The basic circuit has an input mon input and output terminals. Figure 14 shows the typical rent flows until the gate rises to a impedance equal to the paralleled This basic CMOS circuit is pri- input-to-output voltage-transfer ‘threshold’ value of about 1.5 to values of R2 and R3 (=50k), but marily meant for use in digital characteristics of the simple CMOS 2.5 volts, but that the drain current can be increased to greater than applications (as described towards inverter at different supply voltage then increases almost linearly with 10M by wiring R4 as shown. the end of Part 1 of this series), in values. Note that the output volt- further increases in gate voltage. Alternatively, the input imped- which it consumes negligible quies- age changes by only a small Figure 8 shows how to use an ance can be raised to several hun- cent current but can source or sink amount when the input voltage is n-channel 4007UB MOSFET as a dred megohms by bootstrapping substantial output currents. shifted around the VDD and 0V lev- linear inverting amplifier. R1 acts as R4 via C1 as shown in Figure 11. Figures 12(b) and 12(c) show els, but that when Vin is biased at Q2’s drain load, and R2-Rx bias the Note from the above descrip- the inverter’s digital truth table and roughly half-supply volts, a small gate so that Q2 operates in the lin- tion that the enhancement-mode its circuit symbol. Note that Q5 change of input voltage causes a ear mode. MOSFET performs like a conven- and Q6 of the 4007UB IC are large change of output voltage. The Rx value is selected to give tional bipolar transistor, except that fixed-wired in the CMOS inverter Typically, the inverter gives a the desired quiescent drain voltage, it has an ultra-high input imped- configuration. voltage gain of about 30dB when and is normally in the 18k to 100k ance and has a substantially larger Although intended primarily used with a 15V supply, or 40dB range. input-offset voltage (the base-to- for digital use, the basic CMOS at 5V. The amplifier can be made to emitter offset of a bipolar is typi- inverter can be used as a linear Figure 15 shows a practical lin- give a very high input impedance cally 600mV, while the gate-to- amplifier by biasing its input to a ear CMOS inverting amplifier by wiring a 10M isolating resistor source offset voltage of a MOSFET value between the logic-0 and stage. It is biased by wiring 10M between the R2-Rx junction and is typically two volts). logic-1 levels; under this condition resistor R1 between the input and Q2 gate, as shown in Figure 9. Allowing for these differences, Q1 and Q2 are both biased partly output terminals, so that the out- Figure 10 shows how to use the enhancement-mode MOSFET on, and the inverter thus passes put self-biases at approximately

Figure 14. Typical input-to-output voltage transfer characteristics of the 4007UB simple CMOS inverter.

Figure 13. Drain-current transfer characteristics of the simple CMOS inverter.

©T & L Publications, Inc. All rights reserved. Nuts & Volts Magazine/JULY 2000 2 two MOSFETs of the CMOS stage, as shown in the ‘micropower’ cir- cuit of Figure 18. This diagram also lists the Figure 16. effects that different resistor values Typical AV have on the drain current, voltage and gain, and bandwidth of the amplifi- frequency er when operated from a 15V sup- characteristics ply and with its output loaded by a of the linear-mode Figure 15. Method of biasing 10M/15pF oscilloscope probe. Note that the additional resis- basic CMOS the simple CMOS inverter for amplifier. linear operation. tors of the Figure 18 circuit increase the output impedance of half-supply volts. the amplifier (the output imped- Figure 16 shows the typical ance is roughly equal to the R1-AV voltage gain and frequency charac- product), and this impedance and teristics of this circuit when operat- the external load resistance/capaci- ed at three alternative supply rail tance has a great effect on the values; this graph assumes that the overall gain and bandwidth of the amplifier output is feeding into the circuit. high impedance of a 10M/15pF When using a 10k value for Figure 17. oscilloscope probe and, under this R1, for example, if the load capaci- Typical ID/VDD condition, the circuit has a band- tance is increased (from 15pF) to characteristics width of 2.5MHz when operating 50pF, the bandwidth falls to about of the linear-mode from a 15V supply. 4kHz, but if the capacitance is CMOS As would be expected from reduced to 5pF, the bandwidth amplifier. the voltage transfer graph of increases to 45kHz. Similarly, if the Figure 14, the distortion character- resistive load is reduced from 10M istics of the CMOS linear amplifier to 10k, the voltage gain falls to are quite good with small-ampli- unity; for significant gain, the load tude signals (output amplitudes up resistance must be large relative to to 3V peak-to-peak with a 15V sup- the output impedance of the ply), but the distortion then amplifier. increases as the output approaches The basic (unbiased) CMOS the upper and lower supply limits. inverter stage has an input capaci- Unlike a bipolar transistor circuit, tance of about 5pF and an input the CMOS amplifier does not ‘clip’ resistance of near-infinity. Thus, if excessive sinewave signals, but pro- the output of the Figure 18 circuit gressively rounds off their peaks. is fed directly to such a load, it Figure 17 shows the typical shows a voltage gain of x30 and a drain-current versus supply-voltage bandwidth of 3kHz when R1 has a characteristics of the CMOS linear value of 1M0; it even gives a useful amplifier. The current typically gain and bandwidth when R1 has Figure 19. Linear CMOS varies from 0.5mA at 5V, to a value of 10M, but consumes a amplifier wired as x10 12.5mA at 15V. quiescent current of only 0.4µA. inverting amplifier. In many applications, the qui- escent supply current of the PRACTICAL CMOS 4007UB CMOS amplifier can be usefully reduced — at the cost of The CMOS linear amplifier can reduced amplifier bandwidth — by easily be used in either its standard wiring external in series or micropower forms to make a vari- with the source terminals of the ety of fixed-gain amplifiers, mixers, integrators, active filters, and oscilla- tors, etc. A selection of such circuits is shown in Figures 19 to 23. Figure 18. Micropower 4007UB Figure 21. Figure 19 shows the practical CMOS linear amplifier, showing Linear circuit of an x10 inverting amplifier. method of reducing ID, with Figure 20. Linear CMOS CMOS The CMOS stage is biased by feed- performance details. amplifier back resistor R2, and the voltage amplifier wired as wired as unity-gain four-input an gain is set at x10 by the R1/R2 audio mixer. integrator. ratio. The input impedance of the The circuit has four input terminals, circuit is 1M0, and equals the R1 and the voltage gain between each value. input and the output is fixed at enabling the circuit to oscillate. If Figure 20 shows the above cir- unity by the relative values of the the user wants the crystal to pro- cuit modified for use as an audio 1M0 input resistor and the 1M0 vide a frequency accuracy within ‘mixer’ or analog voltage adder. feedback resistor. 0.1% or so, Rx can be replaced by Figure 21 shows a short and C1-C2 can be omitted. the basic CMOS For ultra-high accuracy, the correct Figure 23. amplifier used as a values of Rx-C1-C2 must be individ- Micropower simple integrator. ually determined (the diagram version of the Figure 22 shows shows the typical range of values). . the linear CMOS Finally, Figure 23 shows a amplifier used as a ‘micropower’ version of the CMOS crystal oscillator. The crystal oscillator. In this case, Rx is amplifier is linearly actually incorporated in the amplifi- biased via R1 and er. If desired, the output of this Figure 22. Linear CMOS provides 180° of oscillator can be fed directly to the amplifier wired as a phase shift at the input of an additional CMOS crystal oscillator. crystal resonant fre- inverter stage, for improved wave- quency, thus form shape/amplitude. NV 3 JULY 2000/Nuts & Volts Magazine ©T & L Publications, Inc. All rights reserved. F PRINCIPLES AND CIRCUITS E Part 4 by Ray Marston Field-Effect Transistors

T Ray Marston looks at practical VMOS power FET circuits in this final episode of this four-part series.

art 1 of this series explained (among other things) the basic operating principles of those enhancement-mode Figure 2. power-FET devices known Major asP VFETs or VMOS. This final parameters of episode of the series takes a deeper Figure 1. Symbol of five popular n-channel look at these devices and shows Siliconix VMOS power FET with Siliconix VMOS practical ways of using them. integral zener diode power FETs. gate protection. A VMOS INTRODUCTION VFETs. They are available as n-chan- applications. A VFET can, for most practical nel devices only, and usually incorpo- purposes, be simply regarded as a rate an integral zener diode which THE VN66AF Figure 3. high-power version of a conventional gives the gate a high degree of pro- Outline enhancement-mode MOSFET. The tection against accidental damage; The best way to get to know and pin connections specific form of VFET construction Figure 1 shows the standard symbol VMOS is to actually ‘play’ with it, of the shown in Figure 17 in Part 1 of this used to represent such a device, and and the readily available Siliconix TO202-cased series was pioneered by Siliconix in Figure 2 lists the main characteristics VN66AF is ideal for this purpose. It VN66AF the mid-1970s, and the devices of five of the most popular members is normally housed in a TO202-style power FET. using this construction are marketed of the VMOS family; note in particu- plastic-with-metal-tab package with under the trade name ‘VMOS power lar the very high maximum operat- the outline and pin connections FETs’ (Vertically-structured Metal- ing frequencies of these devices. shown in Figure 3. VN66AF’s typical output and satura- Oxide Silicon power Field-Effect Other well-known families of Figure 4 lists the major static tion characteristics. Note the follow- Transistors). This ‘VMOS’ name is ‘Vertically-structured’ power MOS- and dynamic characteristics of the ing specific points from these traditionally associated with the V- FETS are those produced by Hitachi, VN66AF. Points to note here are graphs. shaped groove formed in the struc- Supertex, and Farranti, etc. Some of that the input (gate-to-source) signal ture of the original (1976) versions these V-type power MOSFETs are must not exceed the unit’s 15V (1) The device passes negligible of the device. available in both n-channel and p- zener rating, and that the device has drain current until the gate voltage Siliconix VMOS power FETs are channel versions and are useful in a typical dynamic input capacitance reaches a threshold value of about probably the best known type of various high-performance comple- of 50pF. This capacitance dictates 1V; the drain current then increases mentary the dynamic input impedance of the non-linearity as the gate is varied up audio VN66AF; the static input impedance to about 4V, at which point the power is of the order of a million drain current value is about 400mA; amplifier megohms. Figures 5 and 6 show the the device has a square-law transfer characteristic below 400mA. (2) The device has a highly linear transfer charac- teristic above 400mA (4V on the gate) and thus offers good results as a low-distor- tion class-A power amplifier. (3) The drain current is controlled almost entirely by the gate voltage and is almost independent of the drain voltage so long as the device is not saturated. A point not shown in the dia- gram is that, for a given value of gate voltage, the drain current has a negative temperature coefficient of about 0.7% per °C, so that the drain current decreases as temperature rises. This Figure 4. Major static and dynamic characteristics Figure 5. Typical output characteristics characteristic gives a fair of the VN66AF. of the VN66AF. degree of protection against

1 AUGUST 2000/Nuts & Volts Magazine ©T & L Publications, Inc. All rights reserved. Figure 10. Method of boosting the output of Figure 9 by driving three VN66AFs in Figure 6. parallel. Typical saturation characteristics of the VN66AF. Figure 11. If inductive loads such as relays (a) or bells, buzzers, or speakers (b) are used in digital switching circuits, protection speed analog power switch. diodes must be wired as DIGITAL CIRCUITS shown.

VMOS can be used in a wide short, or be pro- variety of digital and analog applica- tected with a fer- tions. It is delightfully easy to use in rite bead or a digital switching and amplifying small resistor in applications; Figure 7 shows the series with the Figure 12. basic connections. The load is wired gate. Water- between the drain and the positive VMOS can be or touch- activated supply rail, and the digital input sig- interfaced directly power nal is fed directly to the gate termi- to the output of a Figure 7. Basic VMOS digital switch. switch or amplifier. nal. Switch-off occurs when the CMOS IC, as input goes below the gate threshold shown in Figure value (typically about 1.2V). The 8. Output rise drain ON current is determined by and fall times of the peak amplitude of the gate sig- about 60nS can be expected, due to VMOS in digital switching applica- nal, as shown in Figure 5, unless sat- the limited output currents available tions, note that if inductive drain uration occurs. In most digital appli- from a single CMOS gate, etc. Rise loads such as relays, self-interrupting cations, the ON current should be and fall times can be reduced by dri- bells or buzzers, or moving-coil chosen to ensure saturation. ving the VMOS from a number of speakers are used, clamping diodes The static input impedance of CMOS gates wired in parallel, or by must be connected as shown in VMOS is virtually infinite, so zero using a special high-current driver. Figure 11, to damp inductive back- drive power is needed to maintain VMOS can be interfaced to the EMFs and thus protect the VMOS the VN66AF in the ON or OFF state. output of TTL by using a pull-up device against damage. Drive power is, however, needed to resistor on the TTL output, as shown Figure 8. Methods of driving switch the device from one state to in Figure 9. The 5V TTL output of SOME DIGITAL DESIGNS VMOS from CMOS. the other; this power is absorbed in this circuit is sufficient to drive charging or discharging the 50pF 600mA through a single VN66AF. Figures 12 to 15 show a few input capacitance of the VN66AF. Higher output cur- The rise and fall times of the rents can be output of the Figure 7 circuit are obtained either by (assuming zero input rise and fall wiring a level- times) determined by the source shifter stage impedance of the input signal, by between the TTL Figure 13. the input capacitance and forward output and the Delayed- transconductance of the VMOS VMOS input, or by turn-off device, and by the value of R . If wiring a number power L switch. RL is large compared to RS, the of VMOS devices VN66AF gives rise and fall times of in parallel, as Figure 9. Method of driving roughly 0.11nS per ohm of RS shown in Figure VMOS from TTL. value. Thus, a 100R source imped- 10. ance gives a 11nS rise or fall time. When using thermal runaway. If RL is not large compared to RS, (4) When the device is saturat- these times may be considerably ed (switched fully on) the drain-to- changed. source path acts as an almost pure A point to note when driving resistance with a value controlled by the VN66AF in digital applications is the gate voltage. The resistance is that its zener forward and reverse Figure 14. typically 2R0 when 10V is on the ratings must never be exceeded. Simple gate, and 10R when 2V is on the Also, because of the very high fre- -output gate. The device’s ‘off’ resistance is quency response of VMOS, the timer circuit. in the order of megohms. These fea- device is prone to unwanted oscilla- tures make the device highly suitable tions if its circuitry is poorly for use as a low-distortion high- designed. Gate leads should be kept

©T & L Publications, Inc. All rights reserved. Nuts & Volts Magazine/AUGUST 2000 2 wired in the drain-to-gate negative DC LAMP CONTROLLERS feedback loop and sets the quiescent drain voltage at roughly half-supply Figure Figures 16 to 18 show three value, so that maximal signal level 15. simple but useful DC lamp controller swings can be accommodated before Warble- circuits that can be used to control clipping occurs. tone the brilliance of any 12V lamp with When — in the Figure 19 circuit six watt a power rating of up to six watts. A — R3 has a value of zero ohms, the alarm. VMOS power FET can, for many pur- circuit exhibits an input impedance poses, be regarded as a voltage con- that, because of the AC negative trolled constant-current generator; feedback effects, is roughly equal to thus, in Figure 16, the VMOS drain the parallel values of R1 and R2 divid- current (and thus the lamp bright- ed by the circuit’s voltage gain (RL x ness) is directly controlled by the gM. If R3 has a finite value, the input variable voltage of RV1’s slider. The impedance is slightly less than the R3 circuit thus functions as a manual value, unless AC feedback-decoupling lamp dimmer. capacitor C2 is fitted in place, in The Figure 17 circuit is a simple which case, the input impedance is modification of the above design, slightly greater than the R3 value. the action being such that the lamp Figure 20 shows how to bias the turns on slowly when the switch is VN66AF for common drain (voltage closed as C1 charges up via R3, and follower) operation. Potential divider turns off slowly when the switch is R1-R2 sets the VMOS gate at a quies- opened as C1 discharges via R3. cent value slightly greater than half- The Figure 18 circuit is an effi- supply voltage. When the R3 value is Figure 16. Simple DC cient ‘digital’ lamp dimmer which zero, the circuit input impedance is Figure 17. Soft-start controls the lamp brilliance without equal to the parallel values of R1 and lamp dimmer. lamp switch. causing significant power loss across R2. When the R3 value is finite, the the VMOS device. The two 4011B input impedance equals the R3 value CMOS gates form an astable multivi- plus the parallel R1-R2 values. The brator with a mark/space ratio that input impedance can be raised to a is fully variable from 10:1 to 1:10 via value many times greater than R3 by RV1; its output is fed to the VN66AF adding the C2 ‘bootstrap’ capacitor Figure 18. gate, and enables the mean lamp to the circuit. High- brightness to be varied from virtually Finally, Figure 21 shows a practi- efficiency fully-off to fully-on. In this circuit, the cal example of a VMOS linear appli- DC lamp VMOS device is alternately switched cation. The circuit is wired as a class- dimmer. fully on and fully off, so power loss- A power amplifier which, because of es are negligible. the excellent linearity of the VN66AF, gives remarkably little distortion for LINEAR CIRCUITS so simple a design. The VN66AF must be mounted on a good VMOS power FETs can, when heatsink in this application. When suitably biased, easily be used in the design is used with a purely In the manually activated either the common source or com- resistive 8R0 load, the amplifier Figure 19. Biasing delayed-turn-off circuit of Figure 13, mon drain (voltage follower) linear bandwidth extends up to 10MHz. NV technique for C1 charges rapidly via R1 when modes. The voltage gain in the com- linear common push-button switch PB1 is closed, mon source mode is equal to the source operation. and discharges slowly via R2 when product of RL and the device’s gM or PB1 is open. The load thus activates forward transconductance. In the FET as soon as PB1 is closed, but does case of the VN66AF, this gives a not deactivate until some 10s of sec- voltage gain onds after PB1 is released. of 0.25 per In the simple relay-output timer ohm of RL circuit of Figure 14, the VMOS value, i.e., a device is driven by the output of a gain of x4 Figure 21. manually triggered monostable or with a 16R Simple class-A one-shot multivibrator designed load, or x25 audio power around two gates of a 4001B CMOS with a 100R amplifier gives 1% THD at 1W. IC; the relay turns on as soon as PB1 load. The volt- simple but useful digital applications is closed, and then turns off auto- age gain in of the VN66AF. The water- or touch- matically again some pre-set ‘delay the common activated power switch of Figure 12 time’ later. The delay is variable from drain mode is could not be simpler: when the a few seconds to a few minutes via slightly less touch contacts and water probes are RV1. than unity. open, zero volts are on the gate of Finally, Figure 15 shows the A VMOS power the VN66AF, so the device passes practical circuit of an inexpensive FET can be biased zero current. When a resistance but very impressive alarm-call gener- into the linear com- Figure 20. (zero to 10s of megohms) is placed ator that produces a ‘dee-dah’ mon source mode Biasing across the contacts (by contact with sound like that of a British police car by using the stan- techniques for skin resistance) or probes (by water siren. The alarm can be turned on dard enhancement- linear common drain (voltage contact), a substantial gate voltage by closing PB1 or be feeding a ‘high’ mode MOSFET bias- follower) is developed by potential divider voltage to the R1-R2 junction. The ing technique operation. action and the VN66AF passes a circuit uses an 8R0 speaker and gen- shown in Figure 19, high drain current, thus activating erates roughly six watts of output in which the R1-R2 the bell, buzzer, or relay. power. potential divider is

3 AUGUST 2000/Nuts & Volts Magazine ©T & L Publications, Inc. All rights reserved.