Principles and Circuits
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Techniques for Low Power Analog, Digital and Mixed Signal CMOS
Louisiana State University LSU Digital Commons LSU Doctoral Dissertations Graduate School 2005 Techniques for low power analog, digital and mixed signal CMOS integrated circuit design Chuang Zhang Louisiana State University and Agricultural and Mechanical College, [email protected] Follow this and additional works at: https://digitalcommons.lsu.edu/gradschool_dissertations Part of the Electrical and Computer Engineering Commons Recommended Citation Zhang, Chuang, "Techniques for low power analog, digital and mixed signal CMOS integrated circuit design" (2005). LSU Doctoral Dissertations. 852. https://digitalcommons.lsu.edu/gradschool_dissertations/852 This Dissertation is brought to you for free and open access by the Graduate School at LSU Digital Commons. It has been accepted for inclusion in LSU Doctoral Dissertations by an authorized graduate school editor of LSU Digital Commons. For more information, please [email protected]. TECHNIQUES FOR LOW POWER ANALOG, DIGITAL AND MIXED SIGNAL CMOS INTEGRATED CIRCUIT DESIGN A Dissertation Submitted to the Graduate Faculty of the Louisiana State University and Agricultural and Mechanical College in partial fulfillment of the requirements for the degree of Doctor of Philosophy in The Department of Electrical and Computer Engineering by Chuang Zhang B.S., Tsinghua University, Beijing, China. 1997 M.S., University of Southern California, Los Angeles, U.S.A. 1999 M.S., Louisiana State University, Baton Rouge, U.S.A. 2001 May 2005 ACKNOWLEDGEMENTS I would like to dedicate my work to my parents, Mr. Jinquan Zhang and Mrs. Lingyi Yu and my wife Yiqian Wang, for their constant encouragement throughout my life. I am very grateful to my advisor Dr. Ashok Srivastava for his guidance, patience and understanding throughout this work. -
Review of CMOS Amplifiers for High Frequency Applications
International Journal of Engineering and Advanced Technology (IJEAT) ISSN: 2249-8958 (Online), Volume-10 Issue-2, December 2020 Review of CMOS Amplifiers for High Frequency Applications Sajin. C.S, T. A. Shahul Hameed Abstract: The headway in electronics technology proffers Block diagram of an RF communication system is shown in user-friendly devices. The characteristics such as high Fig.1. In RF communication, amplifier circuits such as low integration, low power consumption, good noise immunity are the noise amplifier, power amplifier, distributed amplifier and significant benefits that CMOS offer, paying many challenges driver amplifier play a vital role. Now days a lot of research simultaneously with it. The short channel effects and presence of parasitic which prevent speed pose questions on the performance works being done in power amplifier and low noise amplifier. parameters. A great sort of works has done by many groups in the While designing a CMOS amplifier many points have to be design of the CMOS amplifier for high-frequency applications to noted to avoid unnecessary performance degradation. CMOS discuss the parameters such as power consumption, high technology has very low power consumption so it can be used bandwidth, high speed and linearity trade-off to obtain an for this low power invented amplifier. CMOS is a MOSFET optimized output. A lot of amplifier topologies are experimented that has symmetrical and complementary pair of p and n-type and discussed in the literature with its design and simulation. In this paper, the various efforts associated with CMOS amplifier MOSFET. The designer should deal with numerous tradeoffs circuit for high-frequency applications are studying extensively. -
(12) United States Patent (10) Patent No.: US 6,356,152 B1 Jezdic Et Al
USOO6356152B1 (12) United States Patent (10) Patent No.: US 6,356,152 B1 Jezdic et al. (45) Date of Patent: Mar. 12, 2002 (54) AMPLIFIER WITH FOLDED SUPER- 5,451.901 A 9/1995 Welland ..................... 330/133 FOLLOWERS 5,512.858 A 4/1996 Perrot ........................ 330/258 5,578,964 A 11/1996 Kim et al. .................. 330/258 (75) Inventors: Andrija Jezdic, Arlington; John L. St.2Y- 2 A : 3.0. S.Inser el G.al. O.. : Wateriority is) 6,118,340 A 9/2000 Koen ......................... 330/253 (73) Assignee: Texas Instruments Incorporated, * cited by examiner Dallas, TX (US) (*) Notice: Subject to any disclaimer, the term of this Primary 'EC, R, Pascal patent is extended or adjusted under 35 ASSistant Examiner Khan Van Nguyen U.S.C. 154(b) by 0 days (74) Attorney, Agent, or Firm-Pedro P. Hernandez; W. a -- James Brady, III; Frederick J. Telecky, Jr. (21) Appl. No.: 09/617,069 (57) ABSTRACT (22) Filed: Jul. 16, 2000 Fixed gain amplifiers have particular use in the read channel of hard disk drives. ACMOS fixed gain amplifier 18c having Related U.S. Application Data a constant gain over the large dynamic range of hard disk (60) Provisional application No. 60/143,798, filed on Jul. 14, drive applications is provided by incorporating Super fol 1999. lower transistors M3 and M4 into the input stage of the fixed (51) Int. Cl. .................................................. HO3F 3/45 gain amplifier. The Super follower transistors are folded into (52) U.S. Cl. ........................................ 330/253; 330/258 the output stage of the amplifier. The differential current (58) Field of Search ................................ -
A Review on VDMOS As a Power MOSFET
IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-ISSN: 2278-2834, p- ISSN: 2278-8735 A Review on VDMOS as a Power MOSFET Surbhi Sharma Vani Gupta1, Shivani Saxena2 1(M.TECH VLSI Banasthali Vidyapith) 2 (Assistant Professor, Dept. of Electronics, Banasthali Vidyapith) ABSTRACT: Today's electronics scenario finds itself with advancement in the field of fore most important component MOSFET. Though one step ahead of MOSFET, power MOSFETs find prime and superior choice for discrete components in circuits as well as today's integrated circuits. Moreover the revolutionary usage of power mosfet for significant power handling capacity lead to the discovery of a whole new genre of power Mosfet such as VDMOS. The progressive demand for high power radio frequency applications in wireless market and superior switching speed makes VDMOS a worthy choice. This paper actuates the working model of VDMOS with its characteristics and working parameters such as breakdown voltage, on-resistance etc. Keywords - Commutation, Power Mosfet, Transconductance,V-groove MOSFET, Vertical diffused MOSFET I. INTRODUCTION VDMOS has highly accomplished features of large input impedance, high switching speed and well heat stability. Its wide range of features have been applied to motor drive, switch power supply, automotive electronics and energy saving lamp and so on. The development of power MOSFETS began in 1970s VMOS (vertical MOSFET), after a decade DDMOS (double diffused MOSFET) technology was introduced. The VDMOS (vertically diffused MOSFET and LDMOS (laterally diffused MOSFET) were derived from the DDMOS technology. Thus the first generation of VDMOS was launched. Currently, the development of VDMOS in our country is still in its prime and the research is still in its maturing stage. -
S Driving MOSPOWER® Fets
s Siiiconix Application Note AN79-4 Driving MOSPOWER® FETs Dave Hoffman INTRODUCTION January 1979 Using VMOS Power FETs you can achieve performance When driving VMOS it must be kept in mind that the never before possible—if you drive them properly. This dynamic input impedance is very different than the static article describes circuits and suggests design methods to input impedance. The input of a VMOS device is capa- be used in order to obtain the performance from VMOS citive. The DC input impedance is very high but the AC that you need. input impedance varies with frequency. Because of this effect, the rise and fall times of VMOS are dependent on When designing with VMOS there are some facts that the output impedance of the circuit driving it. The first must be kept in mind in order to get optimum results approximation of the rise or fall time is simply with every circuit. The first fact is that VMOS is a very high frequency device. The cut-off frequency for all VMOS tror tf = 2.2 (1) FETs is several hundred megahertz. Most power designers are not used to designing with extremely high frequency where R.QUT is the output impedance of the drive circuit. devices because with bipoiars the frequency response This equation is valid only if the drain load resistance decreases as the power increases. The very high frequency is much larger than RQUT- Knowing this fact, along with response of VMOS is the basis for many of its advantages the fact that there is no storage or delay time with VMOS, but it must be kept in mind while designing. -
Transistors 101
Nanotechnology 101 Series Transistors 101 Mark Lundstrom Purdue University Network for Computational Nanotechnology West Lafayette, IN USA NCN www.nanohub.org 1 what to transistors do? 2 Field-Effect Transistor Lillienfield, 1925 Heil, 1935 Bardeen, Schockley, and Brattain, 1947 “The transistor was probably the most important invention of the 20th century,” Ira Flatow, Transistorized! www.pbs.org/transistor 3 transistors integrated circuit Intel 4004 Kilby and Noyce (1958, 1959) Hoff (1971) • junction transistor, 1951 • commercial IC’s, 1961 • silicon BJT, 1954 • PMOS IC’s, 1963 ~2000 transistors • MOSFET, 1960 • CMOS invented, 1963 • NMOS IC’s, 1970 4 silicon microelectronics Silicon wafer (300 mm) Silicon “chip” (~ 2 cm x 2 cm) MPU ROM DSP Control logic RAM analog Intel TI cell phone chip 5 Transistor scaling ~ L Each technology generation: (scaling) L " L 2 A " A 2 Number of transistors per chip doubles (Moore’s Law) ! ! 6 Moore’s Law http://public.itrs.net/ > - - ) > - 10 10000 s - r ) e s t n e o r m c o i 1 1000 n m a ( n ( e z e i z s i s e 0.1 100 r e u r t u a t e nanoelectronics a F 0.01 10 e F 70 80 90 00 10 20 Year--> L = 6 nm (IBM, 2002) L = 5 nm (NEC, 20703) applications symbol switch amplifier D D D G G G S S S 8 EE fundamentals 1) Voltage 2) Current 3) Resistance 4) I-V characteristics resistor voltage source current source 5) Metals, insulators, and semiconductors 9 voltage potential energy = mgh h FG ground 10 voltage + + + + + + + + + + + + + + ++ V = E d Volts d electric field, E force F = qE - - - - - - - - - - - -
CRYOGENIC CHARACTERISTICS of Igbts
CRYOGENIC CHARACTERISTICS OF IGBTs by SHAOYONG YANG A thesis submitted to The University of Birmingham for the degree of DOCTOR OF PHILOSOPHY Electronic, Electrical and Computer Engineering School of Engineering The University of Birmingham July 2005 University of Birmingham Research Archive e-theses repository This unpublished thesis/dissertation is copyright of the author and/or third parties. The intellectual property rights of the author or third parties in respect of this work are as defined by The Copyright Designs and Patents Act 1988 or as modified by any successor legislation. Any use made of information contained in this thesis/dissertation must be in accordance with that legislation and must be properly acknowledged. Further distribution or reproduction in any format is prohibited without the permission of the copyright holder. Abstract Applications are now starting to emerge for superconducting devices in the areas of electrical power conversion and management, for example superconducting windings for marine propulsion motors, superconducting fault current limiters and superconducting magnet energy storage (SMES). Many of these applications also require power electronics, and it is therefore timely to consider the possibility of locating the power electronics in the cryo- system with the superconducting devices. Although significant work has been undertaken on the cryogenic operation of small devices, little has been published on larger devices, particularly the IGBT. This therefore forms the focus of this study. To examine the cryogenic performance of the sample devices, a cryo-system consisting of a cold chamber, a helium-filled compressor and vacuum pumps was built. Static, gate charge and switching tests were carried out on three types of IGBT modules, PT (punch-through), NPT (non-punch-through) and IGBT3 respectively, in the temperature range of 50 to 300 K. -
A CMOS Chopper Amplifier
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-22, NO. 3, JUNE 1987 335 A CMOS Chopper Amplifier CHRISTIAN C. ENZ, STUDENT MEMBER, IEEE, ERIC A. VITTOZ, MEMBER, IEEE, AND FRAN~OIS KRUMMENACHER Abstracf —This paper describes a highly sensitive CMOS chopper Section II will review different low-frequency noise and amplifier for low-frequency applications. It is realized with a second-order offset reduction techniques, emphasizing the fundamental low-pass selective amplifier using a continuous-time filtering technique. differences between the autozero and chopper techniques. The circuit has been integrated in a 3-pm p-well CMOS technology. The chopper amplifier dc gain is 38 dB with a 2@-Efz bandwidth. The equiv- Section III will present the realization of the selective alent inpnt noise is 63 nV/dHz and free from l/~ noise. The input offset amplifier, whereas the theoretical performances of the is below 5 VV for a toning error less than 1 percent. The amplifier chopper amplifier will be discussed in Section IV. Finally consumes only 34 ~W. the circuit implementation and the experimental results will be presented in Sections V and VI. 1. INTRODUCTION II. LOW-FREQUENCY NOISE AND OFFSET N SPITE OF the evolution of scaled-down digital REDUCTION TECHNIQUES [3] Iprocesses, analog circuits will always be needed to per- form a variety of critical tasks required to interface the 4. Input Device Optimization digital with the external world. One of these functions is high-precision amplification with low power consumption. The classical approach to reduce the l/f noise is to The amplifier must be fully compatible with a process enlarge the gate area of the input devices [3]. -
A Fefet Based Processing-In-Memory Architecture for Solving Distributed Least-Square Optimizations
A FeFET Based Processing-In-Memory Architecture for Solving Distributed Least-Square Optimizations Insik Yoon1, Muya Chang1, Kai Ni2, Matthew Jerry2, Samantak Gangopadhyay1, Gus Smith3, Tomer Hamam1, 3 1 4 2 1 Vijaykrishnan Narayanan , Justin Romberg , Shih-Lien Lu , Suman Datta and Arijit Raychowdhury 1Georgia Institute of Technology, Atlanta, GA 30318, USA, 2University of Notre Dame, Notre Dame, IN 46556 USA 3Pennsylvania State University, State College, PA 16801 USA, 4TSMC, Taiwan Email: [email protected] /Phone: (678)643-5264 Introduction: HfO2 based ferroelectric FET (FeFET) has recently received great interest for its application in nonvolatile memory (NVM) [1]. Unlike conventional perovskite based ferroelectric materials, HfO2 is CMOS compatible and retains ferroelectricity for thin film with thickness around 10 nm. Therefore, successful integration of ferroelectric HfO2 into advanced CMOS technology makes this technology highly promising for NVM [1]. Moreover, by tuning the portion of switched ferroelectric domain, a FeFET can exhibit multiple intermediate states, which enables its application as an analog conductance in mixed-signal in-memory computing. Currently, such architectures have been applied to neuromorphic computing [2,3]. In this paper, we present a processing-in-memory (PIM) architecture with FeFETs and demonstrate how this can be used to solve a new class of optimization problems, in particular, distributed least square minimization. Device Operation and Modeling: The operation of FeFET is illustrated in Fig. 1. A positive/negative gate pulse erase/program the device by setting the ferroelectric polarization to point toward the channel/gate, which would set the device in low/high VTH state, respectively. The corresponding IDS-VGS characteristics for the two states are shown in Fig. -
Design of Analog Circuits in 28Nm CMOS Technology for Physics Applications
UNIVERSITÀ DEGLI STUDI DI MILANO-BICOCCA Dipartimento di Fisica “G. Occhialini” AUDENTES FORTUNA IUVAT Tesi di Dottorato in Fisica e Astronomia Curriculum: Tecnologie Fisiche Ciclo XXIX Design of Analog Circuits in 28nm CMOS Technology for Physics Applications Autore: Alessandra Pipino Tutor: Prof. Massimo Gervasi Supervisore: Prof. Andrea Baschirotto Coordinatore: prof.ssa Marta Calvi Anno Accademico 2015/2016 To Fabrizio 3 i Abstract The exponential trend of the complementary metal-oxide-semiconductor (CMOS) technologies predicted by Moore’s law has been successfully demonstrated over the last three decades. A constant downscaling of CMOS technologies has been devel- oped, in order to comply with requirements on speed, complexity, circuit density and power consumption of advanced high performance digital applications. With the arrival of nanoscale (sub-100nm) CMOS technologies, digital perfor- mance improve further, but many new challenges have been introduced for analog designers. In fact, for the digital circuits CMOS scaling-down leads to several benefits: speed improvement, reduced power consumption, high integration and complexity level. The analog circuits, instead, strongly suffers from the ScalTech trend, because the MOS behavior dramatically changes through the different technological nodes. Es- pecially for the ultra-scaled nodes, second order effects, previously negligible, become very important and start to be dominant, affecting the transistors performance. For instance, lower intrinsic DC-gain, reduced dynamic range, operating point issues and larger parameter variability are some of the problems due to the scaling of physical (length, oxide thickness, etc.) and electrical (supply voltage) parameters. Analog designers have to manage these problems at different phases of the design, circuital and layout, in order to satisfy the market high-performance requirements. -
Real-Time Reconfigurable Devices Implemented in UV-Light Programmable Floating-Gate CMOS
Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS by Snorre Aunet June 2002 A dissertation submitted to the Norwegian University of Science and Technology Faculty of Information Technology, Mathematics and Electrical Engineering in partial fulfillment of the requirements for the degree of Doktor Ingenipr. ii iii Abstract This dissertation describes using theory, computer simulations and labora tory measurements a new class of real time reconfigurable UV-programmable floating-gate circuits operating with current levels typically in the pA to fiA range, implemented in a standard double-poly CMOS technology. A new design method based on using the same basic two-MOSFET circuits extensively is proposed, meant for improving the opportunities to make larger FGUVMOS circuitry than previously reported. By using the same basic circuitry extensively, instead of different circuitry for basic digital functions, the goal is to ease UV-programming and test and save circuitry on chip and I/O-pads. Matching of circuitry should also be improved by using this approach. Compact circuitry can be made, reducing wiring and active components. Compared to earlier FGUVMOS approaches the number of transistors for implementing the CARRY’ of a FULL-ADDER is reduced from 22 to 2. A complete FULL-ADDER can be implemented using only 8 transistors. 2- MOSFET circuits able to implement CARRY’, NOR, NAND and INVERT functions are demonstrated by measurements on chip, working with power supply voltages ranging from 800 mV down to 93 mV. An 8-transistor FULL-ADDER might use 2500 times less energy than a FULL-ADDER implemented using standard cells in the same 0.6 fim CMOS technology while running at 1 MHz. -
The Matching of Small Capacitors for Analog Vlsi
THE MATCHING OF SMALL CAPACITORS FOR ANALOG VLSI Bradley A. Minch Chris Diorio Paul Hasler Carver Mead Computation and Neural Systems California Institute of Technology Pasadena, CA 91125 (818) 395-6996 [email protected] ABSTRACT b4 b3 62 bo The capacitor has become the dominant passive component bi for analog circuits designed in standard CMOS processes. 5-to-25 Thus, capacitor matching is a primary factor in determin- Decoder ing the precision of many analog circuit techniques. In ... ... this paper, we present experimental measurements of the vsweep mismatch between square capacitors ranging in size from ... ... 6 pm x 6 pm to 20 pm x 20 pm fabricated in a standard 2 pm double-poly CMOS process available through MOSIS. For a size of 6 pm x 6 pm, we have found that those capacitors that fell within one standard deviation of the mean matched to better than 1%.For the 20 pm x 20 pm size, we observed that those capacitors that fell within 1 standard deviation - of the mean matched to about 0.2%. Finally, we observed the effect of nonidentical surrounds on capacitor matching. Figure 1. Experimental setup used to measure ca- 1. INTRODUCTION pacitance mismatch. As analog circuits have been integrated with digital circuits [7] operating in the subthreshold region [8], using the ex- on CMOS chips, the capacitor has come to dominate ana- perimental setup depicted in Fig. 1. A vMOS transistor is log circuit design. In many ca.ses, resistors are unavailable in CMOS processes, and inductors are generally unattrac- a floating-gate MOS transistor with multiple control gates that capacitively couple into the floating gate, establish- tive for use in the design of all but RF or microwave cir- ing the floating gate’s voltage via a capacitive divider.