DOCSLIB.ORG

Transistors 101

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Transistors 101 Nanotechnology 101 Series Transistors 101 Mark Lundstrom Purdue University Network for Computational Nanotechnology West Lafayette, IN USA NCN www.nanohub.org 1 what to transistors do? 2 Field-Effect Transistor Lillienfield, 1925 Heil, 1935 Bardeen, Schockley, and Brattain, 1947 “The transistor was probably the most important invention of the 20th century,” Ira Flatow, Transistorized! www.pbs.org/transistor 3 transistors integrated circuit Intel 4004 Kilby and Noyce (1958, 1959) Hoff (1971) • junction transistor, 1951 • commercial IC’s, 1961 • silicon BJT, 1954 • PMOS IC’s, 1963 ~2000 transistors • MOSFET, 1960 • CMOS invented, 1963 • NMOS IC’s, 1970 4 silicon microelectronics Silicon wafer (300 mm) Silicon “chip” (~ 2 cm x 2 cm) MPU ROM DSP Control logic RAM analog Intel TI cell phone chip 5 Transistor scaling ~ L Each technology generation: (scaling) L " L 2 A " A 2 Number of transistors per chip doubles (Moore’s Law) ! ! 6 Moore’s Law http://public.itrs.net/ > - - ) > - 10 10000 s - r ) e s t n e o r m c o i 1 1000 n m a ( n ( e z e i z s i s e 0.1 100 r e u r t u a t e nanoelectronics a F 0.01 10 e F 70 80 90 00 10 20 Year--> L = 6 nm (IBM, 2002) L = 5 nm (NEC, 20703) applications symbol switch amplifier D D D G G G S S S 8 EE fundamentals 1) Voltage 2) Current 3) Resistance 4) I-V characteristics resistor voltage source current source 5) Metals, insulators, and semiconductors 9 voltage potential energy = mgh h FG ground 10 voltage + + + + + + + + + + + + + + ++ V = E d Volts d electric field, E force F = qE - - - - - - - - - - - - - - - - - - - - - ground: V = 0 potential energy: E = qE d Joules 11 voltage + V = 1.5 V I - 12 current I + + + + + + + + + ++ I - - - - - - - - - Q I = C/sec = amperes " 13 ! resistance R I resistance (ohms W) 14 current-voltage characteristic decreasing R I increasing R V V Ohm’s Law: I = R 15 ! ideal voltage source I I + V LOAD V 0- 0 V 16 ideal current source + I I 0 + LOAD V I0 - V - 17 transistor I D + ? VDS G V VGS S - 18 metal I • good conductors Au Ag • resistance low Cu • conduction by electrons 19 insulator I glass • very poor conductors quartz • resistance very high SiO2 20 semiconductor I Si resistance greater than a Ge metal (~ 1 W) but less than an insulator (~ 106 W) GaAs 21 semiconductor doping I intrinsic semiconductor: e.g. pure Si doped semiconductor: < 1% ‘impurities’ Si p-type: boron impurities conduction by + charges n-type: phosphorus impurities conduction by - charges22 EE fundamentals √ 1) Voltage √ 2) Current √ 3) Resistance √ 4) I-V characteristics resistor voltage source current source √ 5) Metals, insulators, and semiconductors 23 building a transistor n+ poly Si SiO2 p-type silicon 24 building a transistor source gate drain n+ poly Si n+ Si p-type silicon 25 S G D 26 transistor - + VDS I D VG < VT source gate drain n+ Si p-type silicon 27 transistor I D VDS 28 transistor - + VDS I D VG > VT source gate drain n+ Si - - p-type silicon 29 transistor I D VDS 30 transistor - + VDS I D VG > VT source gate drain + - - n Si -- - p-type silicon 31 transistor: a voltage controlled resistor? I D increasing VG VDS 32 real transistors VGS G + + + + - - - - ID S D VDS VDS 33 real transistors VGS ID ID VGS VDS VDS 34 real transistors V ID GS G S D VDS VDS why does the current saturate? 35 MOSFET energy band diagrams electron energy vs. position S G D VD≈ 0V VD= VDD E = -q V 36 low VDS I1 I2 I1, I2 ~ VG ID = I1 - I2 VD = 0: I1 = 12 ID = 0 ID VD > 0: VG2 I1 > 12 V G1 ID > 0 37 VDS high VDS I1 I2 I1, ~ VG I2 ~ 0 I D I = I ~ V VG2 D 1 G VG1 38 VDS complementary CMOS VDD P-channel MOSFET VOUT VIN N-channel MOSFET 39 CMOS G G S D S D n+ Si p+ Si p-type silicon n-type silicon n-MOS: VGS > 0 p-MOS: VGS < 0 40 CMOS inverter VDD VDD P > - - T V U OUT O VIN V V N DD VIN--> “transfer characteristic” 41 CMOS inverter ID VDD > - - T U O V VDD V --> IN VDS flatter characteristic sharp transition (small dependence of I on V ) separates zero and one D DS gives sharp transition 42 Two input CMOS NAND gate V AND dd A B C 0 0 0 0 1 0 P1 P2 1 0 0 V 1 1 1 Cout V A N1 in1 NAND A B C V 0 0 1 Bin2 N2 0 1 1 1 0 1 1 1 0 43 CMOS Amplifier VDD gain VDD > - v - out VOUT T U VIN O V VDD VIN--> vin 44 transistors terminal 1 point contact transistor bipolar transistor I1 MOSFET JFET SOI MOSFET FinFET control MODFET (HEMT) heterojunction bipolar transistor velocity modulation transistor terminal 2 45.
Load more

Recommended publications
  • Techniques for Low Power Analog, Digital and Mixed Signal CMOS
    Louisiana State University LSU Digital Commons LSU Doctoral Dissertations Graduate School 2005 Techniques for low power analog, digital and mixed signal CMOS integrated circuit design Chuang Zhang Louisiana State University and Agricultural and Mechanical College, [email protected] Follow this and additional works at: https://digitalcommons.lsu.edu/gradschool_dissertations Part of the Electrical and Computer Engineering Commons Recommended Citation Zhang, Chuang, "Techniques for low power analog, digital and mixed signal CMOS integrated circuit design" (2005). LSU Doctoral Dissertations. 852. https://digitalcommons.lsu.edu/gradschool_dissertations/852 This Dissertation is brought to you for free and open access by the Graduate School at LSU Digital Commons. It has been accepted for inclusion in LSU Doctoral Dissertations by an authorized graduate school editor of LSU Digital Commons. For more information, please [email protected]. TECHNIQUES FOR LOW POWER ANALOG, DIGITAL AND MIXED SIGNAL CMOS INTEGRATED CIRCUIT DESIGN A Dissertation Submitted to the Graduate Faculty of the Louisiana State University and Agricultural and Mechanical College in partial fulfillment of the requirements for the degree of Doctor of Philosophy in The Department of Electrical and Computer Engineering by Chuang Zhang B.S., Tsinghua University, Beijing, China. 1997 M.S., University of Southern California, Los Angeles, U.S.A. 1999 M.S., Louisiana State University, Baton Rouge, U.S.A. 2001 May 2005 ACKNOWLEDGEMENTS I would like to dedicate my work to my parents, Mr. Jinquan Zhang and Mrs. Lingyi Yu and my wife Yiqian Wang, for their constant encouragement throughout my life. I am very grateful to my advisor Dr. Ashok Srivastava for his guidance, patience and understanding throughout this work.
    [Show full text]
  • Review of CMOS Amplifiers for High Frequency Applications
    International Journal of Engineering and Advanced Technology (IJEAT) ISSN: 2249-8958 (Online), Volume-10 Issue-2, December 2020 Review of CMOS Amplifiers for High Frequency Applications Sajin. C.S, T. A. Shahul Hameed Abstract: The headway in electronics technology proffers Block diagram of an RF communication system is shown in user-friendly devices. The characteristics such as high Fig.1. In RF communication, amplifier circuits such as low integration, low power consumption, good noise immunity are the noise amplifier, power amplifier, distributed amplifier and significant benefits that CMOS offer, paying many challenges driver amplifier play a vital role. Now days a lot of research simultaneously with it. The short channel effects and presence of parasitic which prevent speed pose questions on the performance works being done in power amplifier and low noise amplifier. parameters. A great sort of works has done by many groups in the While designing a CMOS amplifier many points have to be design of the CMOS amplifier for high-frequency applications to noted to avoid unnecessary performance degradation. CMOS discuss the parameters such as power consumption, high technology has very low power consumption so it can be used bandwidth, high speed and linearity trade-off to obtain an for this low power invented amplifier. CMOS is a MOSFET optimized output. A lot of amplifier topologies are experimented that has symmetrical and complementary pair of p and n-type and discussed in the literature with its design and simulation. In this paper, the various efforts associated with CMOS amplifier MOSFET. The designer should deal with numerous tradeoffs circuit for high-frequency applications are studying extensively.
    [Show full text]
  • (12) United States Patent (10) Patent No.: US 6,356,152 B1 Jezdic Et Al
    USOO6356152B1 (12) United States Patent (10) Patent No.: US 6,356,152 B1 Jezdic et al. (45) Date of Patent: Mar. 12, 2002 (54) AMPLIFIER WITH FOLDED SUPER- 5,451.901 A 9/1995 Welland ..................... 330/133 FOLLOWERS 5,512.858 A 4/1996 Perrot ........................ 330/258 5,578,964 A 11/1996 Kim et al. .................. 330/258 (75) Inventors: Andrija Jezdic, Arlington; John L. St.2Y- 2 A : 3.0. S.Inser el G.al. O.. : Wateriority is) 6,118,340 A 9/2000 Koen ......................... 330/253 (73) Assignee: Texas Instruments Incorporated, * cited by examiner Dallas, TX (US) (*) Notice: Subject to any disclaimer, the term of this Primary 'EC, R, Pascal patent is extended or adjusted under 35 ASSistant Examiner Khan Van Nguyen U.S.C. 154(b) by 0 days (74) Attorney, Agent, or Firm-Pedro P. Hernandez; W. a -- James Brady, III; Frederick J. Telecky, Jr. (21) Appl. No.: 09/617,069 (57) ABSTRACT (22) Filed: Jul. 16, 2000 Fixed gain amplifiers have particular use in the read channel of hard disk drives. ACMOS fixed gain amplifier 18c having Related U.S. Application Data a constant gain over the large dynamic range of hard disk (60) Provisional application No. 60/143,798, filed on Jul. 14, drive applications is provided by incorporating Super fol 1999. lower transistors M3 and M4 into the input stage of the fixed (51) Int. Cl. .................................................. HO3F 3/45 gain amplifier. The Super follower transistors are folded into (52) U.S. Cl. ........................................ 330/253; 330/258 the output stage of the amplifier. The differential current (58) Field of Search ................................
    [Show full text]
  • A CMOS Chopper Amplifier
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-22, NO. 3, JUNE 1987 335 A CMOS Chopper Amplifier CHRISTIAN C. ENZ, STUDENT MEMBER, IEEE, ERIC A. VITTOZ, MEMBER, IEEE, AND FRAN~OIS KRUMMENACHER Abstracf —This paper describes a highly sensitive CMOS chopper Section II will review different low-frequency noise and amplifier for low-frequency applications. It is realized with a second-order offset reduction techniques, emphasizing the fundamental low-pass selective amplifier using a continuous-time filtering technique. differences between the autozero and chopper techniques. The circuit has been integrated in a 3-pm p-well CMOS technology. The chopper amplifier dc gain is 38 dB with a 2@-Efz bandwidth. The equiv- Section III will present the realization of the selective alent inpnt noise is 63 nV/dHz and free from l/~ noise. The input offset amplifier, whereas the theoretical performances of the is below 5 VV for a toning error less than 1 percent. The amplifier chopper amplifier will be discussed in Section IV. Finally consumes only 34 ~W. the circuit implementation and the experimental results will be presented in Sections V and VI. 1. INTRODUCTION II. LOW-FREQUENCY NOISE AND OFFSET N SPITE OF the evolution of scaled-down digital REDUCTION TECHNIQUES [3] Iprocesses, analog circuits will always be needed to per- form a variety of critical tasks required to interface the 4. Input Device Optimization digital with the external world. One of these functions is high-precision amplification with low power consumption. The classical approach to reduce the l/f noise is to The amplifier must be fully compatible with a process enlarge the gate area of the input devices [3].
    [Show full text]
  • Design of Analog Circuits in 28Nm CMOS Technology for Physics Applications
    UNIVERSITÀ DEGLI STUDI DI MILANO-BICOCCA Dipartimento di Fisica “G. Occhialini” AUDENTES FORTUNA IUVAT Tesi di Dottorato in Fisica e Astronomia Curriculum: Tecnologie Fisiche Ciclo XXIX Design of Analog Circuits in 28nm CMOS Technology for Physics Applications Autore: Alessandra Pipino Tutor: Prof. Massimo Gervasi Supervisore: Prof. Andrea Baschirotto Coordinatore: prof.ssa Marta Calvi Anno Accademico 2015/2016 To Fabrizio 3 i Abstract The exponential trend of the complementary metal-oxide-semiconductor (CMOS) technologies predicted by Moore’s law has been successfully demonstrated over the last three decades. A constant downscaling of CMOS technologies has been devel- oped, in order to comply with requirements on speed, complexity, circuit density and power consumption of advanced high performance digital applications. With the arrival of nanoscale (sub-100nm) CMOS technologies, digital perfor- mance improve further, but many new challenges have been introduced for analog designers. In fact, for the digital circuits CMOS scaling-down leads to several benefits: speed improvement, reduced power consumption, high integration and complexity level. The analog circuits, instead, strongly suffers from the ScalTech trend, because the MOS behavior dramatically changes through the different technological nodes. Es- pecially for the ultra-scaled nodes, second order effects, previously negligible, become very important and start to be dominant, affecting the transistors performance. For instance, lower intrinsic DC-gain, reduced dynamic range, operating point issues and larger parameter variability are some of the problems due to the scaling of physical (length, oxide thickness, etc.) and electrical (supply voltage) parameters. Analog designers have to manage these problems at different phases of the design, circuital and layout, in order to satisfy the market high-performance requirements.
    [Show full text]
  • Compact High Performance Analog Cmos Baseband Design Solutions for Multistandard Wireless Transceivers
    COMPACT HIGH PERFORMANCE ANALOG CMOS BASEBAND DESIGN SOLUTIONS FOR MULTISTANDARD WIRELESS TRANSCEIVERS DISSERTATION Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the Graduate School of The Ohio State University By Seok-Bae Park, B.S., M.S. ***** The Ohio State University 2006 Dissertation Committee: Approved by Mohammed Ismail El-Naggar, Adviser Patrick Roblin Adviser Steven B. Bibyk Graduate Program in Electrical and Computer Engineering c Copyright by Seok-Bae Park 2006 ABSTRACT In this dissertation, a novel compact wireless radio transceiver architecture reusing a baseband chain so as to significantly reduce the die area is proposed. The proposed architecture employs a direct conversion architecture with a shared base- band chain and is suitable for wireless standards based on time-division duplexing air interface. In direct conversion architectures, baseband channel selection filters and variable gain amplifiers are placed in the receive path as well as in the transmit path. Here, it is proposed to use the same baseband filters and variable gain amplifiers in both the receive path and the transmit path to reduce the die area. To realize a high performance direct conversion receiver for multistandard wireless communications, the limiting factors in the direct conversion receiver should be identified and removed. In this dissertation, among many problems in direct conversion receivers, the DC offset problem is addressed. The origins of the DC offset are summarized, and three self-mixing mechanisms generating the DC offset are modeled to understand how the static and dynamic DC offsets are produced from the mechanisms. A DC offset cancellation scheme consisting of a static DC offset canceller and a dynamic DC offset canceller is proposed.
    [Show full text]
  • 5G and E-Band Communication Circuits in Deep- Scaled CMOS Analog Circuits and Signal Processing
    ACSP · Analog Circuits and Signal Processing Marco Vigilante Patrick Reynaert 5G and E-Band Communication Circuits in Deep- Scaled CMOS Analog Circuits and Signal Processing Series Editors Mohammed Ismail, Dublin, USA Mohamad Sawan, Montreal, Canada More information about this series at http://www.springer.com/series/7381 Marco Vigilante • Patrick Reynaert 5G and E-Band Communication Circuits in Deep-Scaled CMOS 123 Marco Vigilante Patrick Reynaert ESAT-MICAS ESAT-MICAS KU Leuven KU Leuven Leuven Leuven Belgium Belgium ISSN 1872-082X ISSN 2197-1854 (electronic) Analog Circuits and Signal Processing ISBN 978-3-319-72645-8 ISBN 978-3-319-72646-5 (eBook) https://doi.org/10.1007/978-3-319-72646-5 Library of Congress Control Number: 2017964595 © Springer International Publishing AG, part of Springer Nature 2018 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication.
    [Show full text]
  • Design of an RF CMOS Power Amplifier for Wireless Sensor Networks Hua Pan University of Arkansas, Fayetteville
    University of Arkansas, Fayetteville ScholarWorks@UARK Theses and Dissertations 5-2012 Design of an RF CMOS Power Amplifier for Wireless Sensor Networks Hua Pan University of Arkansas, Fayetteville Follow this and additional works at: http://scholarworks.uark.edu/etd Part of the Electrical and Electronics Commons Recommended Citation Pan, Hua, "Design of an RF CMOS Power Amplifier for Wireless Sensor Networks" (2012). Theses and Dissertations. 357. http://scholarworks.uark.edu/etd/357 This Thesis is brought to you for free and open access by ScholarWorks@UARK. It has been accepted for inclusion in Theses and Dissertations by an authorized administrator of ScholarWorks@UARK. For more information, please contact [email protected], [email protected]. DESIGN OF AN RF CMOS POWER AMPLIFIER FOR WIRELESS SENSOR NETWORKS DESIGN OF AN RF CMOS POWER AMPLIFIER FOR WIRELESS SENSOR NETWORKS A thesis submitted in partial fulfillment of the requirements for the degree of Masters of Science in Electrical Engineering By Hua Pan Capital Normal University Bachelor of Engineering in Electronics and Information Engineering, 2005 May 2012 University of Arkansas ABSTRACT The Power Amplifier (PA) is the last Radio Frequency (RF) building block in a transmitter, directly driving an antenna. The low power RF input signal of the PA is amplified to a significant power RF output signal by converting DC power into RF power. Since the PA consumes a majority of the power, efficiency plays one of the most important roles in a PA design. Designing an efficient, fully integrated RF PA that can operate at low supply voltage (1.2V), low power, and low RF frequency (433MHz) is a major challenge.
    [Show full text]
  • Information to Users
    INFORMATION TO USERS This manuscript has been reproduced from the microfilm master. UMI films the text directly from the original or copy submitted. Thus, some thesis and dissertation copies are in typewriter face, while others may be from any type of computer printer. The quality of this reproduction is dependent upon the quality of the copy subm itted. Broken or indistinct print, colored or poor quality illustrations and photographs, print bleedthrough, substandard margins, and improper alignment can adversely affect reproduction. In the unlikely event that the author did not send UMI a complete manuscript and there are missing pages, these will be noted. Also, if unauthorized copyright material had to be removed, a note will indicate the deletion. Oversize materials (e.g., maps, drawings, charts) are reproduced by sectioning the original, beginning at the upper left-hand comer and continuing from left to right in equal sections with small overlaps. Photographs included in the original manuscript have been reproduced xerographicaliy in this copy. Higher quality 6” x 9" black and white photographic prints are available for any photographs or illustrations appearing in this copy for an additional charge. Contact UMI directly to order. ProQuest Information and Learning 300 North Zeeb Road, Ann Arbor, Ml 48106-1346 USA 800-521-0600 UMI* CMOS DIGITALLY PROGRAMMABLE ANALOG FRONT-ENDS FOR THIRD GENERATION WIRELESS APPLICATIONS DISSERTATION Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the Graduate School of The Ohio State University By Hassan Elwan, B.S., M.S. ***** The Ohio State University 2001 Dissertation Committee: Approved by Mohammed Ismail, Adviser Patrick Roblin Adviser George Valeo Department of Electrical Engineering UMI Number 3022479 UMI UMI Microform 3022479 Copyright 2001 by Bell & Howell Information and Learning Company.
    [Show full text]
  • Noise Efficient Integrated Amplifier Designs for Biomedical Applications
    electronics Article Noise Efficient Integrated Amplifier Designs for Biomedical Applications Sebastian Simmich 1,* , Andreas Bahr 2 and Robert Rieger 1 1 Networked Electronic Systems, Institute of Electrical Engineering and Information Technology, Kiel University, 24143 Kiel, Germany; [email protected] 2 Sensor System Electronics, Institute of Electrical Engineering and Information Technology, Kiel University, 24143 Kiel, Germany; [email protected] * Correspondence: [email protected] Abstract: The recording of neural signals with small monolithically integrated amplifiers is of high interest in research as well as in commercial applications, where it is common to acquire 100 or more channels in parallel. This paper reviews the recent developments in low-noise biomedical amplifier design based on CMOS technology, including lateral bipolar devices. Seven major circuit topology categories are identified and analyzed on a per-channel basis in terms of their noise-efficiency factor (NEF), input-referred absolute noise, current consumption, and area. A historical trend towards lower NEF is observed whilst absolute noise power and current consumption exhibit a widespread over more than five orders of magnitude. The performance of lateral bipolar transistors as amplifier input devices is examined by transistor-level simulations and measurements from five different prototype designs fabricated in 180 nm and 350 nm CMOS technology. The lowest measured noise p floor is 9.9 nV/ Hz with a 10 µA bias current, which results in a NEF of 1.2. Citation: Simmich, S.; Bahr, A.; Keywords: noise efficiency; NEF; lateral BJT; chopper stabilized; OTA; inverter based; current reuse; Rieger, R. Noise Efficient Integrated folded-cascode; multistage; low noise; low power; CMOS Amplifier Designs for Biomedical Applications.
    [Show full text]
  • The Instrumentation Amplifier Handbook
    The Instrumentation Amplifier Handbook Including Applications Neil P. Albaugh Burr- Brown Corporation Tucson, Arizona DRAFT COPY Contents: INSTRUMENTATION AMPLIFIERS 2-1 Overview 2-1 THE WHEATSTONE BRIDGE SENSOR 2-2 Error Sources 2-5 AMPLIFIER TOPOLOGIES 3-1 The Difference Amplifier 3-1 The “Classical” Three Op Amp Instrumentation Amplifier 3-3 Internal vs. External Gain Setting Resistors 3-7 The Two Op Amp Instrumentation Amplifier 3-8 AVOIDING INSTRUMENTATION AMPLIFIER PITFALLS 4-1 Input Bias Current Effects 4-1 Avoiding the “Reference Pin” Trap 4-5 A Common Mistake: Floating Inputs 4-8 Common- Mode Voltage Limitations 4-11 Calculating Common Mode Voltage Range Painlessly 4-12 Maintaining “Truth In Output” 4-18 Noise Filtering The IA Input The Wrong Way—Making A Bad Situation Worse 4-20 SOLVING THE GROUND LOOP PROBLEM 5-1 What Are “Ground Loops”? 5-1 Op Amps and Ground Loops 5-1 Instrumentation Amplifiers and Ground Loops 5-2 OFFSET VOLTAGE TRIM 5-3 Trimming Offset Voltage At The Input 5-3 Trimming Offset Voltage Using REF Pin 5-4 BOOSTING THE OUTPUT 5-4 Driving Heavy Loads : The Wrong Way 5-4 Driving Heavy Loads : The Right Way 5-5 APPLICATION CIRCUITS: GENERAL 6-1 A +/-20V Input Diff Amp With +/-200V CMV Applications Circuit 6-1 Two and Three Op Amp IA Applications 6-3 Difference Amplifier Applications In Single- Ended Circuits 6-3 APPLICATIONS CIRCUITS: AUDIO 6-10 Low Noise Applications 6-10 Low Distortion Applications 6-11 DIFFERENCE AMPLIFIER INPUT RESISTANCE 6-12 APPLICATIONS CIRCUITS: CURRENT MEASUREMENT 7-1 Current Shunts 7-1
    [Show full text]
  • High EMI Resistivity CMOS Operational Amplifier
    International Journal of Computer Applications (0975 – 8887) Volume 111 – No 1, February 2015 High EMI Resistivity CMOS Operational Amplifier Lavlesh Sharma Shyam Akashe M.Tech. VLSI Student of Electronics Department, ITM Associate Professor of Electronics Department, ITM College College Gwalior, India Gwalior, India ABSTRACT preserving high gain and large gain-bandwidth (GBW) product. In this paper a high resistant EMI interference CMOS operational The proposed adjustment can be formulated by standard CMOS amplifier has been designed and simulated. It is designed by technology, and it neither requires extra levels of masking, such implementing easy modification of the differential pair with as triple well, nor external components. Furthermore, it can be active current load. The power amplifier seems to be leading the easily adapted on other Op-Amp topologies, improving their output voltage power with respect to the input supply given, the resistivity to EMI. two stage power amplifier was designed in this current technology and results are noted below. CMOS power amplifier 2. DESIGN STAGES is a type of power amplifier designed by using CMOS transistors In order to easily investigate the EMI effects on a generic connected together and get the output gain of amplifier .The amplifier, the interfering signals are represented by a sinusoidal desired input stage can be produce using standard CMOS waveform generated with zero dc mean value and superimposed technologies, and it also does not requires extra levels of on the pins connected to long wires (long wires, indeed, act as masking process, such as triple well, nor external components are antennas for EMI). This assumption represents a worst-case required.
    [Show full text]