CHAPTER 6

Basic FET Ampli®ers

6.0 PREVIEW In the last chapter, we described the operation of the FET, in particular the MOSFET, and analyzed and designed the dc response of circuits containing these devices. In this chapter, we emphasize the use of FETs in linear ampli®er applications. Although a major use of MOSFETs is in digital applications, they are also used in linear ampli®er circuits. There are three basic con®gurations of single-stage or single-transistor FET ampli®ers. These are the common-source, source-follower, and com- mon-gate con®gurations. We investigate the characteristics of each con®gura- tion and show how these properties are used in various applications. Since MOSFET integrated circuit ampli®ers normally use MOSFETs as load devices instead of resistors because of their small size, we introduce the technique of usingMOSFET enhancement or depletion devices as loads. These three con- ®gurations form the building blocks for more complex ampli®ers, so gaining a good understanding of these three ampli®er circuits is an important goal of this chapter. In integrated circuit systems, ampli®ers are usually connected in series or cascade, forming a multistage con®guration, to increase the overall voltage gain, or to provide a particular combination of voltage gain and output resis- tance. We consider a few of the many possible multistage con®gurations, to introduce the analysis methods required for such circuits, as well as their properties. JFET ampli®ers are also considered. These circuits, again, tend to be specialized, so the JFET discussion is brief.

6.1 THE MOSFET AMPLIFIER In Chapter 4, we discussed the reasons linear ampli®ers are necessary in analog electronic systems. In this chapter, we continue the analysis and design of linear ampli®ers that use ®eld-effect transistors as the amplifyingdevice. The term small signal means that we can linearize the ac equivalent circuit. We will de®ne what is meant by small signal in the case of MOSFET circuits. The term linear ampli®ers means that we can use superposition so that the dc analysis and ac

313 314 Part I Semiconductor Devices and Basic Applications

analysis of the circuits can be performed separately and the total response is the sum of the two individual responses. The mechanism with which MOSFET circuits amplify small time-varying signals was introduced in the last chapter. In this section, we will expand that discussion usingthe graphical technique, dc load line, and ac load line. In the process, we will develop the various small-signal parameters of linear circuits and the correspondingequivalent circuits. There are four possible equivalent circuits that can be used. These are listed in Table 4.3 of Chapter 4. The most common equivalent circuit that is used for the FET ampli®ers is the transconductance ampli®er, in which the input signal is a voltage and the output signal is a current. The small-signal parameters associated with this equivalent circuit are developed in the follow- ingsection.

6.1.1 Graphical Analysis, LoadLines, andSmall-Signal Parameters Figure 6.1 shows an NMOS common-source circuit with a time-varying vol- tage source in series with the dc source. We assume the time-varying input signal is sinusoidal. Figure 6.2 shows the transistor characteristics, dc load line, and Q-point, where the dc load line and Q-point are functions of vGS, VDD, RD, and the transistor parameters. For the output voltage to be a linear function of the input voltage, the transistor must be biased in the saturation region. (Note that, although we primarily use n-channel, enhancement-mode MOSFETs in our discussions, the same results apply to the other MOSFETs.)

VDD

i i D D RD

vDS (sat) vO + Time Q-point vDS + vi Time – I V v + v DQ GSQ i – GS – + VGSQ –

V V v Figure 6.31 Equivalent DSQ DD DS circuit NMOS source- follower, for determining Time output resistanceFigure 6.1 NMOS common-source circuit with time-varying Figure 6.2 Common-source transistor characteristics, dc load signal source in series with line, and sinusoidal variation in gate-to-source voltage, drain gate dc source current, and drain-to-source voltage

Also shown in Figure 6.2 are the sinusoidal variations in the gate-to-source voltage, drain current, and drain-to-source voltage, as a result of the sinusoidal

source vi. The total gate-to-source voltage is the sum of VGSQ and vi.Asvi increases, the instantaneous value of vGS increases, and the bias point moves up Chapter 6 Basic FET Amplifiers 315

the load line. A larger value of vGS means a larger drain current and a smaller value of vDS. For a negative vI (the negative portion of the sine wave), the instantaneous value of vGS decreases below the quiescent value, and the bias point moves down the load line. A smaller vGS value means a smaller drain current and increased value of vDS. Once the Q-point is established, we can develop a mathematical model for the sinusoidal, or small-signal, variations in gate-to-source voltage, drain-to-source voltage, and drain current. The time-varyingsignalsource vi in Figure 6.1 generates a time-varying component of the gate-to-source voltage. In this case, vgs ˆ vi, where vgs is the time-varying component of the gate-to-source voltage. For the FET to operate as a linear ampli®er, the transistor must be biased in the saturation region, and the instantaneous drain current and drain-to-source voltage must also be con- ®ned to the saturation region.

Transistor Parameters The instantaneous gate-to-source voltage is

vGS ˆ VGSQ ‡ vi ˆ VGSQ ‡ vgs 6:1† where VGSQ is the dc component and vgs is the ac component. The instanta- neous drain current is

2 iD ˆ Kn vGS À VTN † 6:2† SubstitutingEquation (6.1) into (6.2) produces

2 2 iD ˆ Kn‰VGSQ ‡ vgs À VTN Š ˆ Kn‰ VGSQ À VTN †‡vgsŠ 6:3 a†† or

2 2 iD ˆ Kn VGSQ À VTN † ‡ 2Kn VGSQ À VTN †vgs ‡ Knvgs 6:3 b††

The ®rst term in Equation (6.3(b)) is the dc or quiescent drain current IDQ, the second term is the time-varyingdrain current component that is linearly related to the signal vgs, and the third term is proportional to the square of the signal voltage. For a sinusoidal input signal, the squared term produces unde- sirable harmonics, or nonlinear distortion, in the output voltage. To minimize these harmonics, we require

vgs  2 VGSQ À VTN † 6:4† which means that the third term in Equation (6.3(b)) will be much smaller than the second term. Equation (6.4) represents the small-signal condition that must be satis®ed for linear ampli®ers. 2 Neglecting the vgs term, we can write Equation (6.3(b))

iD ˆ IDQ ‡ id 6:5† Again, small-signal implies linearity so that the total current can be separated into a dc component and an ac component. The ac component of the drain current is given by

id ˆ 2Kn VGSQ À VTN †vgs 6:6† The small-signal drain current is related to the small-signal gate-to-source voltage by the transconductance gm. The relationship is 316 Part I Semiconductor Devices and Basic Applications

id gm ˆ ˆ 2Kn VGSQ À VTN † 6:7† vgs The transconductance is a transfer coef®cient relatingoutput current to input voltage and can be thought of as representing the gain of the transistor. The transconductance can also be obtained from the derivative

@i g ˆ D ˆ 2K V À V † 6:8 a†† m @v n GSQ TN GS vGSˆVGSQˆconst: which can be written p gm ˆ 2 KnIDQ 6:8 b†† The drain current versus gate-to-source voltage for the transistor biased in the saturation region is given in Equation (6.2) and is shown in Figure 6.3. The transconductance gm is the slope of the curve. If the time-varyingsignal vgs is suf®ciently small, the transconductance gm is a constant. With the Q-point in the saturation region, the transistor operates as a current source that is linearly controlled by vgs. If the Q-point moves into the nonsaturation region, the transistor no longer operates as a linearly controlled current source.

iD

Time I DQ Slope = gm

Time

VTh VGS vGS Figure 6.3 Drain current versus gate-to-source voltage characteristics, with superimposed sinusoidal signals

As shown in Equation (6.8(a)), the transconductance is directly propor- tional to the conduction parameter Kn, which in turn is a function of the width- to-length ratio. Therefore, increasing the width of the transistor increases the transconductance, or gain, of the transistor.

Example 6.1 Objective: Calculate the transconductance of an n-channel MOSFET. 1 Consider an n-channel MOSFET with parameters VTN ˆ 1V, 2†nCox ˆ 2 20 mA=V , and W=L ˆ 40. Assume the drain current is ID ˆ 1 mA. Solution: The conduction parameter is  1 W K ˆ  C ˆ 20† 40† mA=V2 ) 0:80 mA=V2 n 2 n ox L Chapter 6 Basic FET Amplifiers 317

Assumingthe transistor is biased in the saturation region,the transconductance is determined from Equation (6.8(b)), p p gm ˆ 2 KnIDQ ˆ 2 0:8† 1† ˆ 1:79 mA=V

Comment: The transconductance of a bipolar transistor is gm ˆ ICQ=VT †, which is 38.5 mA/V for a collector current of 1 mA. The transconductance values of MOSFETs tend to be small compared to those of BJTs. However, the advantages of MOSFETs include high input impedance, small size, and low power dissipation.

AC Equivalent Circuit From Figure 6.1, we see that the output voltage is

vDS ˆ vO ˆ VDD À iDRD 6:9† UsingEquation (6.5), we obtain

vO ˆ VDD À IDQ ‡ id †RD ˆ VDD À IDQRD†Àid RD 6:10† The output voltage is also a combination of dc and ac values. The time- varying output signal is the time-varying drain-to-source voltage, or

vo ˆ vds ˆÀid RD 6:11† Also, from Equations (6.6) and (6.7), we have

id ˆ gmvgs 6:12† In summary, the followingrelationships exist between the time-varying signals for the circuit in Figure 6.1. The equations are given in terms of the instantaneous ac values, as well as the phasors. We have

vgs ˆ vi 6:13 a†† or

Vgs ˆ Vi 6:13 b†† and

id ˆ gmvgs 6:14 a†† or

Id ˆ gmVgs 6:14 b†† Also, vo v ˆÀi R 6:15 a†† ds d D id or + R v D V ˆÀI R 6:15 b†† v + gs ds d D i – – The ac equivalent circuit in Figure 6.4 is developed by setting the dc sources in Figure 6.1 equal to zero. The small-signal relationships are given in Equations (6.13), (6.14), and (6.15). As shown in Figure 6.1, the drain Figure 6.4 AC equivalent current, which is composed of ac signals superimposed on the quiescent circuit of common-source value, ¯ows through the voltage source VDD. Since the voltage across this ampli®er with NMOS transistor 318 Part I Semiconductor Devices and Basic Applications

source is assumed to be constant, the sinusoidal current produces no sinusoidal voltage component across this element. The equivalent ac impedance is there- fore zero, or a short circuit. Consequently, in the ac equivalent circuit, the dc

voltage sources are equal to zero. We say that the node connecting RD and VDD is at signal ground.

6.1.2 Small-Signal Equivalent Circuit Now that we have the ac equivalent circuit for the NMOS ampli®er circuit, (Figure 6.4), we must develop a small-signal equivalent circuit for the transis- tor. Initially, we assume that the signal frequency is suf®ciently low so that any capacitance at the gate terminal can be neglected. The input to the gate thus appears as an open circuit, or an in®nite resistance. Equation (6.14) relates the small-signal drain current to the small-signal input voltage, and Equation (6.7)

shows that the transconductance gm is a function of the Q-point. The resulting simpli®ed small-signal equivalent circuit for the NMOS device is shown in Figure 6.5. (The phasor components are in parentheses.)

D + id (Id) GD G + + + vds (Vds) id (Id) gmvgs v (V ) v (V ) vgs (Vgs) ds ds gs gs (gmVgs) – – – – S S (a) (b)

Figure 6.5 (a) Common-source NMOS transistor with small-signal parameters and (b) simpli®ed small-signal equivalent circuit for NMOS transistor

This small-signal equivalent circuit can also be expanded to take into account the ®nite output resistance of a MOSFET biased in the saturation region. This effect, discussed in the last chapter, is a result of the nonzero slope in the iD versus vDS curve. We know that

2 iD ˆ Kn‰ vGS À VTN † 1 ‡ vDS†Š 6:16† where  is the channel-length modulation parameter and is a positive quantity. The small-signal output resistance, as previously de®ned, is  @i À1 r ˆ D 6:17† o @v DS vGS ÀVGSQˆconst: or

2 À1 À1 ro ˆ‰Kn VGSQ À VTN † Š ‰IDQŠ 6:18† This small-signal output resistance is also a function of the Q-point parameters. Chapter 6 Basic FET Amplifiers 319

The expanded small-signal equivalent cicuit of the n-channel MOSFET is shown in Figure 6.6 in phasor notation. Note that this equivalent circuit is a transconductance ampli®er (see Table 4.3) in that the input signal is a voltage and the output signal is a current. This equivalent circuit can now be inserted into the ampli®er ac equivalent circuit in Figure 6.4 to produce the circuit in Figure 6.7. We may note that the small-signal equivalent circuit for the MOSFET circuit is very similar to that of the BJT circuits considered in Chapter 4.

GD + + Id Vo Vgs gmVgs ro Vds + + + V – – Vi – Vgs gmVgs ro RD ds S – – Figure 6.6 Expanded small- signal equivalent circuit, Figure 6.7 Small-signal equivalent circuit of including output resistance, for common-source circuit with NMOS transistor NMOS transistor model

Example 6.2 Objective: Determine the small-signal voltage gain of a MOSFET circuit.

For the circuit in Figure 6.1, assume parameters are: VGSQ ˆ 2:12 V, VDD ˆ 5V, 2 and RD ˆ 2:5k . Assume transistor parameters are: VTN ˆ 1V,Kn ˆ 0:80 mA=V , and  ˆ 0:02 VÀ1. Assume the transistor is biased in the saturation region. Solution: The quiescent values are

2 2 IDQ  Kn VGSQ À VTN † ˆ 0:8† 2:12 À 1† ˆ 1:0mA and

VDSQ ˆ VDD À IDQRD ˆ 5 À 1† 2:5†ˆ2:5V Therefore,

VDSQ ˆ 2:5V> VDS sat†ˆVGS À VTN ˆ 1:82 À 1 ˆ 0:82 V which means that the transistor is biased in the saturation region, as initially assumed, and as required for a linear ampli®er. The transconductance is

gm ˆ 2Kn VGSQ À VTN †ˆ2 0:8† 2:12 À 1†ˆ1:79 mA=V and the output resistance is

À1 À1 ro ˆ‰IDQŠ ˆ‰ 0:02† 1†Š ˆ 50 k From Figure 6.7, the output voltage is

Vo ˆÀgmVgs rokRD†

Since Vgs ˆ Vi, the small-signal voltage gain is

Vo Av ˆ ˆÀgm rokRd †ˆÀ 1:79† 50k2:5†ˆÀ4:26 Vi 320 Part I Semiconductor Devices and Basic Applications

Comment: Because of the relatively low value of transconductance, MOSFET circuits tend to have a lower small-signal voltage gain than comparable bipolar circuits. Also, the small-signal voltage gain contains a minus sign, which means that the sinusoidal output voltage is 180 degrees out of phase with respect to the input sinusoidal signal.

Problem Solving Method: MOSFET AC Analysis Since we are dealingwith linear ampli®ers, superposition applies, which means that we can perform the dc and ac analyses separately. The analysis of the MOSFET ampli®er proceeds as follows:

1. Analyze the circuit with only the dc sources present. This solution is the dc or quiescent solution. The transistor must be biased in the saturation region in order to produce a linear ampli®er. 2. Replace each element in the circuit with its small-signal model, which means replacingthe transistor by its small-signalequivalent cicuit. 3. Analyze the small-signal equivalent circuit, setting the dc source compo- nents equal to zero, to produce the response of the circuit to the time- varyinginput signals only.

Test Your Understanding

6.1 For an n-channel MOSFET biased in the saturation region, the parameters are 2 À1 Kn ˆ 0:5mA=V , VTN ˆ 0:8 V, and  ˆ 0:01 V , and IDQ ˆ 0:75 mA. Determine gm and ro. (Ans. gm ˆ 1:22 mA=V, ro ˆ 1:33 k ) 1 2 6.2 The parameters of an n-channel MOSFET are: VTN ˆ 1V, 2 nCox ˆ 18 mA=V , and  ˆ 0:015 VÀ1. The transistor is to be biased in the saturation region with

IDQ ˆ 2 mA. Design the width-to-length ratio such that the transconductance is gm ˆ 3:4 mA/V. Calculate ro for this condition. (Ans. W=L ˆ 80:6, ro ˆ 33:3k )

6.3 For the circuit shown in Figure 6.1, VDD ˆ 10 V and RD ˆ 10 k . The transistor 2 parameters are: VTN ˆ 2V, Kn ˆ 0:5mA=V , and  ˆ 0. (a) Determine VGSQ such that IDQ ˆ 0:4 mA. Calculate VDSQ. (b) Calculate gm and ro, and determine the small-signal voltage gain. (c) If vi ˆ 0:4 sin !t, ®nd vds. Does the transistor remain in the saturation region? (Ans. (a) VGSQ ˆ 2:89 V, VDSQ ˆ 6 V; (b) gm ˆ 0:89 mA/V, ro ˆ1, Av ˆÀ8:9; (c) vds ˆÀ3:56 sin !t, yes)

The previous discussion was for an n-channel MOSFET ampli®er. The same basic analysis and equivalent circuit also applies to the p-channel tran- sistor. Figure 6.8(a) shows a circuit containing a p-channel MOSFET. Note

that the power supply voltage VDD is connected to the source. (The subscript DD can be used to indicate that the supply is connected to the drain terminal.

Here, however, VDD is simply the usual notation for the power supply voltage in MOSFET circuits.) Also note the change in current directions and voltage polarities compared to the circuit containingthe NMOS transistor. Figure 6.8(b) shows the ac equivalent circuit, with the dc voltage sources replaced Chapter 6 Basic FET Amplifiers 321

VDD

+ vSG + + vsg – + v – SD v – sd – v + vO i – vo + + vi i – D RD id R VGG D –

(a) (b) Figure 6.8 (a) Common-source circuit with PMOS transistor and (b) corresponding ac equivalent circuit by ac short circuits, and all currents and voltages shown are the time-varying components. In the circuit of Figure 6.8(b), the transistor can be replaced by the equiva- lent circuit in Figure 6.9. The equivalent circuit of the p-channel MOSFET is the same as that of the n-channel device, except that all current directions and voltage polarities are reversed. The ®nal small-signal equivalent circuit of the p-channel MOSFET ampli- ®er is shown in Figure 6.10. The output voltage is

Vo ˆ gmVsg RokRD† 6:19†

I GDd GD V – – – o

V g V r V + V g V r R sg m sg o sd Vi – sg m sg o D

+ + + S S Figure 6.9 Small-signal Figure 6.10 Small-signal equivalent circuit equivalent circuit of PMOS of common-source ampli®er with PMOS transistor transistor model

The control voltage Vsg, given in terms of the input signal voltage, is

Vsg ˆÀVi 6:20† and the small-signal voltage gain is

Vo Av ˆ ˆÀgm rokRD† 6:21† Vi This expression for the small-signal voltage gain of the p-channel MOSFET ampli®er is exactly the same as that for the n-channel MOSFET ampli®er. The negative sign indicates that a 180-degree phase reversal exists between the ouput and input signals, for both the PMOS and the NMOS circuit. 322 Part I Semiconductor Devices and Basic Applications

We may again note that if the polarity of the small-signal gate-to-source voltage is reversed, then the small-signal drain current direction is reversed and the small-signal equivalent cicuit of the PMOS device is exactly identical to that of the NMOS device. However, the author prefers to use the small-signal equivalent circuit in Figure 6.9 to be consistent with the voltage polarities and current directions of the PMOS transistor.

6.1.3 Modeling the Body Effect As mentioned in Section 5.1.7, Chapter 5, the body effect occurs in a MOSFET in which the substrate, or body, is not connected to the source. For an NMOS device, the body is connected to the most negative potential in the circuit and will be at signal ground. Figure 6.11(a) shows the four-terminal MOSFET with dc voltages and Figure 6.11(b) shows the device with ac voltages. Keep in mind that vSB must be greater or equal to zero. The simpli®ed current-voltage relation is

2 iD ˆ Kn vGS À VTN † 6:22† and the threshold voltage is given by hiq q VTN ˆ VTNO ‡ 2f ‡ vSB À 2f 6:23†

Figure 6.11 The four-terminal NMOS device with (a) dc voltages and (b) ac voltages

If an ac component exists in the source-to-body voltage, vSB, there will be an ac component induced in the threshold voltage, which causes an ac compo- nent in the drain current. Thus, a back-gate transconductance can be de®ned as 

@iD À@iD @iD @VTN gmb ˆ ˆ ˆÀ Á 6:24† @vBS Q-pt @vSB Q-pt @VTN @vSB Q-pt UsingEquation (6.22), we ®nd

@iD ˆÀ2Kn vGS À VTN †ˆÀgm 6:25 a†† @VTN and usingEquation (6.23), we ®nd @V TN ˆ p   6:25 b†† @vSB 2 2f ‡ vSB The back gate transconductance is then Chapter 6 Basic FET Amplifiers 323

gmb ˆ À Àgm†Á †ˆgm 6:26†

Includingthe body effect, the small-signalequivalent circuit of the MOSFET is shown in Figure 6.12. We note the direction of the current and the polarity of the small-signal source-to-body voltage. If vbs > 0, then vSB decreases, VTN decreases, and iD increases. The current direction and voltage polarity are thus consistent.

Figure 6.12 Small-signal equivalent circuit of NMOS device including bodyeffect

1=2 For f ˆ 0:35 V and ˆ 0:35 V , the value of  from Equation (6.25(b)) is   0:23. Therefore,  will be in the range 0    0:23. The value of vbs will depend on the particular circuit.

In general, we will neglect gmb in our hand analyses and designs, but will investigate the body effect in PSpice analyses.

Test Your Understanding

6.4 The parameters for the circuit in Figure 6.8 are VDD ˆ 12 V and RD ˆ 6k . The 2 transistor parameters are: VTP ˆÀ1V, Kp ˆ 2mA=V , and  ˆ 0. (a) Determine VSG such that VSDQ ˆ 7 V. (b) Determine gm and ro, and calculate the small-signal voltage gain. (Ans. (a) VSG ˆ 1:65 V; (b) gm ˆ 2:6 mA/V, ro ˆ1, Av ˆÀ15:6) 6.5 Show that, for an NMOS transistor biased in the saturation region, with a drain current of IDQ, the transconductance can be expressed as given in Equation (6.8(b)), that is p gm ˆ 2 KnIDQ

6.6 A transistor has the same parameters as those given in Exercise 6.1. In addition, 1=2 the body effect coef®cient is ˆ 0:40 V and f ˆ 0:35 V. Determine the value of  and the back gate transconductance gmb for (a) vSB ˆ 1 V and (b) vSB ˆ 3V.

6.2 BASIC TRANSISTOR AMPLIFIER CONFIGURATIONS As we have seen, the MOSFET is a three-terminal device. Three basic single- transistor ampli®er con®gurations can be formed, depending on which of the three transistor terminals is used as signal ground. These three basic con®g- urations are appropriately called common source, common drain (source fol- lower),andcommon gate. These three circuit con®gurations correspond to the common-emitter, emitter-follower, and common-base con®gurations 324 Part I Semiconductor Devices and Basic Applications

usingBJTs. The similarities and differences between the FET and BJT circuits will be discussed. The input and output resistance characteristics of ampli®ers are important in determining loading effects. These parameters, as well as voltage gain, for the three basic MOSFET circuit con®gurations will be determined in the fol- lowingsections. The characteristics of the three types of ampli®ers will then allow us to understand under what condition each ampli®er is most useful. Initially, we will consider MOSFET ampli®er circuits that emphasize dis- crete designs, in that resistor biasing will be used. The purpose is to become familiar with basic MOSFET ampli®er designs and their characteristics, using biasingtechniques similar to those used in BJT ampli®ers in previous chapters. In Section 6.7, we will begin to consider integrated circuit MOSFET designs that involve all-transistor circuits and current source biasing. These initial designs provide an introduction to more advanced MOS ampli®er designs that will be considered in Part II of the text.

6.3 THE COMMON-SOURCE AMPLIFIER In this section, we consider the ®rst of the three basic circuitsÐthe common- source ampli®er. We will analyze several basic common-source circuits, and will determine small-signal voltage gain and input and output impedances.

6.3.1 A Basic Common-Source Configuration For the circuit shown in Figure 6.13, assume that the transistor is biased in the

saturation region by resistors R1 and R2, and that the signal frequency is suf®ciently large for the coupling capacitor to act essentially as a short circuit. The signal source is represented by a Thevenin equivalent circuit, in which the

signal voltage source vI is in series with an equivalent source resistance RSi.As we will see, RSi should be much less than the ampli®er input resistance, Ri ˆ R1kR2, in order to minimize loadingeffects. Figure 6.14 shows the resulting small-signal equivalent circuit. The small-

signal variables, such as the input signal voltage Vi, are given in phasor form.

VDD

RD R1 C v RSi C1 O

vi + – R2

Figure 6.13 Common-source circuit with voltage divider biasing and coupling capacitor Chapter 6 Basic FET Amplifiers 325

Ri Ro Rsi G D Vo + + Id V + g V r i – R1 R2 Vgs m gs o RD Vds

– – S

Figure 6.14 Small-signal equivalent circuit, assuming coupling capacitor acts as a short circuit

Since the source is at ground potential, there is no body effect. The output voltage is

Vo ˆÀgmVgs rokRD† 6:27† The input gate-to-source voltage is  Ri Vgs ˆ Á Vi 6:28† Ri ‡ RSi so the small-signal voltage gain is  Vo Ri Av ˆ ˆÀgm rokRD†Á 6:29† Vi Ri ‡ RSi We can also relate the ac drain current to the ac drain-to-source voltage, as Vds ˆÀId RD†. Figure 6.15 shows the dc load line, the transistion point, and the Q-point, which is in the saturation region. As previously stated, in order to provide the maximum symmetrical output voltage swing and keep the transistor biased in the saturation region, the Q-point must be near the middle of the saturation region. At the same time, the input signal must be small enough for the ampli- ®er to remain linear.

iD VDD ID(max) = RD

VDS (sat) = VGS – VTN

Transition point

Q-point 1 IDQ dc load line, slope = – RD

VDSQ VDD vDS

Figure 6.15 DC load line and transition point separating saturation and nonsaturation regions 326 Part I Semiconductor Devices and Basic Applications

The input and output resistances of the ampli®er can be determined from Figure 6.14. The input resistance to the ampli®er is Ris ˆ R1kR2. Since the low- frequency input resistance lookinginto the gateof the MOSFET is essentially in®nite, the input resistance is only a function of the bias resistors. The output resistance lookingback into the output terminals is found by settingthe inde- pendent input source Vi equal to zero, which means that Vgs ˆ 0. The output resistance is therefore Ro ˆ RDkro:

Example 6.3 Objective: Determine the small-signal voltage gain and input and output resistances of a common-source ampli®er.

For the circuit shown in Figure 6.13, the parameters are: VDD ˆ 10 V, R1 ˆ 70:9k , R2 ˆ 29:1k , and RD ˆ 5k . The transistor parameters are: 2 À1 VTN ˆ 1:5V, Kn ˆ 0:5mA=V , and  ˆ 0:01 V . Assume RSi ˆ 4k . Solution: DC Calculations: The dc or quiescent gate-to-source voltage is   R2 29:1 VGSQ ˆ VDD†ˆ 10†ˆ2:91 V R1 ‡ R2 70:9 ‡ 29:1 The quiescent drain current is

2 2 IDQ ˆ Kn VGSQ À VTN † ˆ 0:5† 2:91 À 1:5† ˆ 1mA and the quiescent drain-to-source voltage is

VDSQ ˆ VDD À IDQRD ˆ 10 À 1† 5†ˆ5V

Since VDSQ > VGSQ À VTN , the transistor is biased in the saturation region.

Small-signal Voltage Gain: The small-signal transconductance gm is then

gm ˆ 2Kn VGSQ À VTN †ˆ2 0:5† 2:91 À 1:5†ˆ1:41 mA=V

and the small-signal output resistance ro is À1 À1 ro ‰IDQŠ ˆ‰ 0:01† 1†Š ˆ 100 k The ampli®er input resistance is

Ri ˆ R1kR2 ˆ 70:9k29:1 ˆ 20:6k From Figure 6.14 and Equation (6.29), the small-signal voltage gain is   Ri 20:6 Av ˆÀgm rokR†D†Á ˆÀ 1:41† 100k5† Ri ‡ RSi 20:6 ‡ 4 or

Av ˆÀ5:62

Input andOutput Resistances: As already calculated, the ampli®er input resistance is

Ri ˆ R1kR2 ˆ 70:9k29:1 ˆ 20:6k and the ampli®er output resistance is

Ro ˆ RDkro ˆ 5k100 ˆ 4:76 k

Comment: The resulting Q-point is in the center of the load line but not in the center of the saturation region. Therefore, this circuit does not achieve the maximum symme- trical output voltage swing in this case. Chapter 6 Basic FET Amplifiers 327

Discussion: The small-signal input gate-to-source voltage is  Ri 20:6 Vgs ˆ Á Vi ˆ Á Vi ˆ 0:837†ÁVi Ri ‡ RSi 20:6 ‡ 4

Since RSi is not zero, the ampli®er input signal Vgs is approximately 84 percent of the signal voltage. This is again called a loading effect. Even though the input resistance to the gate of the transistor is essentially in®nite, the bias resistors greatly in¯uence the ampli®er input resistance and loadingeffect.

Test Your Understanding

6.7 Consider the circuit in Figure 6.1 with circuit parameters VDD ˆ 5V,RD ˆ 5k , 2 VGSQ ˆ 2 V, and with transistor paramaeters Kn ˆ 0:25 mA=V , VTN ˆ 0:8 V, and  ˆ 0. (a) Calculate the quiescent values IDQ and VDSQ. (b) Calculate the transconduc- tance gm. (c) Determine the small-signal voltage gain Av ˆ vo=vi. (Ans. (a) IDQ ˆ 0:36 mA, VDSQ ˆ 3:2 V; (b) gm ˆ 0:6mA=V, ro ˆ1; (c) Av ˆÀ3:0) 6.8 For the circuit in Figure 6.1, the circuit and transistor parameters are given in

Exercise 6.2. If vi ˆ 0:1 sin !t V, determine iD and vDS. (Ans. iD ˆ 0:36 ‡ 0:06 sin !t† mA, vDS ˆ 3:2 À 0:3 sin !t† V)

Design Example 6.4 Objective: Design the bias of a MOSFET such that the Q-point is in the middle of the saturation region.

Consider the circuit in Figure 6.16 with transistor parameters VTN ˆ 1V, 2 À1 Kn ˆ 1mA=V , and  ˆ 0:015 V . Let Ri ˆ R1kR2 ˆ 100 k . Design the circuit such that IDQ ˆ 2 mA and the Q-point is in the middle of the saturation region.

VDD = 12 V

RD ID = 2 mA R1 vO CC

vi + – R2

Figure 6.16 Common-source NMOS transistor circuit

Solution: The load line and the desired Q-point are given in Figure 6.17. If the Q-point is to be in the middle of the saturation region, the current at the transition point must be 4 mA. 328 Part I Semiconductor Devices and Basic Applications

i 1 D Load line, slope = – RD

VDS (sat) = VGS – VTN

4 mA Q-point

2 mA VGSQ = 2.41 V

VDS t (sat) VDSQ = 7 V VDD = 12 V vDS

Figure 6.17 DC load line and transition point for NMOS circuit shown in Figure 6.16

We can now calculate VDS(sat) at the transition point. The subscript t indicates transition point values. To determine VGSt, we use 2 2 IDt ˆ 4 ˆ Kn VGSt À VTN † ˆ 1 VGSt À 1† which yields

VGSt ˆ 3V Therefore

VDSt ˆ VGSt À VTN ˆ 3 À 1 ˆ 2V

If the Q-point is in the middle of the saturation region, then VDSQ ˆ 7 V, which would yield a 10 V peak-to-peak symmetrical output voltage. From Figure 6.16, we can write

VDSQ ˆ VDD À IDQRD or

VDD À VDSQ 12 À 7 RD ˆ ˆ ˆ 2:5k IDQ 2 We can determine the required quiescent gate-to-source voltage from the current equation, as follows:

2 2 IDQ ˆ 2 ˆ Kn VGSQ À VTN † ˆ 1† VGSQ À 1† or

VGSQ ˆ 2:41 V Then   R2 1 R1R2 VGSQ ˆ 2:41 ˆ VDD†ˆ VDD† R1 ‡ R2 R1 R1 ‡ R2 Ri 100† 12† ˆ Á VDD ˆ R1 R1 which yields

R1 ˆ 498 k and R2 ˆ 125 k We can then determine the small-signal equivalent circuit parameters from the Q-

point values. The transconductance is gm ˆ 2:82 mA/V, the transistor output resistance is ro ˆ 33:3k , and the small-signal voltage gain, assuming an ideal signal source, is Chapter 6 Basic FET Amplifiers 329

Vo Av ˆ ˆÀgm rokRD†ˆÀ 2:82† 33:3k2:5†ˆÀ6:56 Vi

Comment: Establishingthe Q-point in the middle of the saturation region allows the maximum symmetrical swingin the output voltage,while keepingthe transistor biased in the saturation region.

Design Pointer: If the circuit were to contain by pass or load capacitors, then an ac load line would be superimposed on the ®gure at the Q-point. Establishingthe Q-point in the middle of the saturation region, then, may not be optimal in terms of obtaining the maximum symmetrical swing.

6.3.2 Common-Source Amplifier with Source Resistor

A source resistor RS tends to stabilize the Q-point against variations in tran- sistor parameters (Figure 6.18). If, for example, the value of the conduction parameter varies from one transistor to another, the Q-point will not vary as much if a source resistor is included in the circuit. However, as shown in the following example, a source resistor also reduces the signal gain. This same effect was observed in BJT circuits when an emitter resistor was included. The circuit in Figure 6.18 is an example of a situation in which the body effect should be taken into account. The substrate (not shown) would normally be connected to the À5 V supply, so that the body and substrate terminals are not at the same potential. However, in the followingexample, we will neglect this effect.

+5 V

Ω RD = 7 k Ω R1 = 165 k vO CC

v + i – Ω R2 = 35 k Ω RS = 0.5 k

–5 V Figure 6.18 Common-source circuit with source resistor and positive and negative supply voltages

Example 6.5 Objective: Determine the small-signal voltage gain of a common- source circuit containinga source resistor.

Consider the circuit in Figure 6.18. The transistor parameters are VTN ˆ 0:8V, 2 Kn ˆ 1mA=V , and  ˆ 0: 330 Part I Semiconductor Devices and Basic Applications

Solution: From the dc analysis of the circuit, we ®nd that VGSQ ˆ 1:50 V, IDQ ˆ 0:50 mA, and VDSQ ˆ 6:25 V. The small-signal transconductance is

gm ˆ 2Kn VGS À VTN †ˆ2 1† 1:50 À 0:8†ˆ1:4mA=V and the small-signal resistance is

À1 ro ‰IDQŠ ˆ1 Figure 6.19 shows the resulting small-signal equivalent circuit.

Vo +

V + g V i – R1 R2 Vgs m gs RD –

RS

Figure 6.19 Small-signal equivalent circuit of NMOS common-source ampli®er with source resistor

The output voltage is

Vo ˆÀgmVgsRD

Writinga KVL equation from the input around the gate±sourceloop, we ®nd

Vi ˆ Vgs ‡ gmVgs†RS ˆ Vgs 1 ‡ gmRS†

or

Vi Vgs ˆ 1 ‡ gmRS The small-signal voltage gain is

Vo ÀgmRD Av ˆ ˆ Vi 1 ‡ gmRS

We may note that if gm were large, then the small-signal voltage gain would be approxi- mately

Av ÀRD RSŠ Substituting the appropriate parameters into the actual voltage gain expression, we ®nd À 1:4† 7† A ˆ ˆÀ5:76 v 1 ‡ 1:4† 0:5†

Comment: A source resistor reduces the small-signal voltage gain. However, as dis- cussed in the last chapter, the Q-point is more stabilized against variations in the transistor parameters. We may note that the approximate voltage gain gives

Av ÀRD=RS ˆÀ14. Since the transconductance of MOSFETs is generally low, the approximate gain expression is a poor one at best. Chapter 6 Basic FET Amplifiers 331

Discussion: We mentioned that includinga source resistor tends to stabilize the cir- cuit characteristics against any changes in transistor parameters. If, for example, the conduction parameter Kn varies by Æ20 per cent, we ®nd the followingresults.

2 Kn (mA/V ) gm (mA/V) Av 0.8 1.17 À5:17 1.0 1.40 À5:76 1.2 1.62 À6:27

The change in Kn produces a fairly large change in gm. The resultingchangein the voltage gain is approximately Æ9:5 per cent. This change is larger than might be expected because the initial value of gM is smaller than that of the bipolar circuit.

Test Your Understanding

6.9 For the circuit shown in Figure 6.20, the transistor parameters are Kp ˆ 1 mA/ 2 V , VTP ˆÀ1 V, and  ˆ 0. The source-to-drain voltage is vSD ˆ 3 ‡ 0:46 sin !t V, and the quiescent drain current is IDQ ˆ 0:5 mA. Determine RD, VGG, vi, and the small-signal voltage gain. (Ans. RD ˆ 4k , VGG ˆ 3:29 V, Av ˆÀ5:64, vi ˆ‡0:0816 sin !t V) 6.10 The common-source ampli®er in Figure 6.21 has transistor parameters 2 À1 Kp ˆ 2mA=V , VTP ˆÀ2 V, and  ˆ 0:01 V . (a) Determine IDQ and VSDQ. (b) Calculate the small-signal voltage gain. (Ans. (a) IDQ ˆ 4:56 mA, VSDQ ˆ 7:97 V; (b) Av ˆÀ6:04)

+9 V

Ω RS = 1.2 k +5 V

CC1 CS

v + v v i – O + v Ω O – i RG = 100 k + RD R = 1 kΩ VGG D –

–9 V Figure 6.20 Figure for Exercise 6.9 Figure 6.21 Figure for Exercise 6.10

6.3.3 Common-Source Circuit with Source Bypass Capacitor A source bypass capacitor added to the common-source circuit with a source resistor will minimize the loss in the small-signal voltage gain, while maintain- ingthe Q-point stability. The Q-point stability can be further increased by 332 Part I Semiconductor Devices and Basic Applications

replacingthe source resistor with a constant-current source. The resulting circuit is shown in Figure 6.22, assuming an ideal signal source. If the signal frequency is suf®ciently large so that the bypass capacitor acts essentially as an ac short-circuit, the source will be held at signal ground.

+5 V

Ω RD = 7 k

vO

v + Ω i – RG = 200 k CS

IQ = 0.5 mA

–5 V Figure 6.22 NMOS common-source circuit with source bypass capacitor

Example 6.6 Objective: Determine the small-signal voltage gain of a circuit biased with a constant-current source and incorporatinga source bypass capacitor.

For the circuit shown in Figure 6.22, the transistor parameters are: VTN ˆ 0:8V, 2 Kn ˆ 1mA=V , and  ˆ 0. Solution: Since the dc gate current is zero, the dc voltage at the source terminal is

VS ˆÀVGSQ, and the gate-to-source voltage is determined from 2 IDQ ˆ IQ ˆ Kn VGSQ À VTN † or

2 0:5 ˆ 1† VGSQ À 0:8† which yields

VGSQ ˆÀVS ˆ 1:51 V The quiescent drain-to-source voltage is

VDSQ ˆ VDD À IDQRD À VS ˆ 5 À 0:5† 7†À À1:51†ˆ3:01 V The transistor is therefore biased in the saturation region. The small-signal equivalent circuit is shown in Figure 6.23. The output voltage is

Vo +

+ g V Ω Vi – RG Vgs m gs RD = 7 k –

Figure 6.23 Small-signal equivalent circuit, assuming the source bypass capacitor acts as a short circuit Chapter 6 Basic FET Amplifiers 333

Vo ˆÀgmVgsRD

Since Vgs ˆ Vi, the small-signal voltage gain is

Vo Av ˆ ˆÀgmRD ˆÀ 1:4† 7†ˆÀ9:8 Vi

Comment: Comparing the small-signal voltage gain of 9.8 in this example to the 5.76 calculated in Example 6.5, we see that the magnitude of the gain increases when a source bypass capacitor is included.

Test Your Understanding

*D6.11 The common-source ampli®er in Figure 6.24 has transistor parameters 1 2 VTN ˆ 1:5V, 2 nCox ˆ 20 mA=V , and  ˆ 0. Design the circuit such that IDQ ˆ 0:5 mA and the small-signal voltage gain is Av ˆÀ4:0. (Ans. For example: For VGS ˆ 2:5 V, then W=L ˆ 25, RD ˆ 4:0k ) 6.12 Consider the common-source ampli®er in Figure 6.25 with transistor para- 2 meters VTN ˆ 1:8V, Kn ˆ 0:15 mA=V , and  ˆ 0. (a) Calculate IDQ and VDSQ. (b) Determine the small-signal voltage gain. (c) Discuss the purpose of RD and its effect on the small-signal operation of the ampli®er. (Ans. (a) IDQ ˆ 1:05 mA, VDSQ ˆ 4:45 V; (b) Av ˆÀ2:65)

+5 V

VDD = 15 V

RD Ω vO RD = 10 k Ω RG = 5 M vo C C1 CC2 v + Ω Ω i – RG = 50 k RL = 5 k CS I v + Q i –

–5 V Figure 6.24 Figure for Exercise 6.11 Figure 6.25 Figure for Exercise 6.12

*6.13 For the circuit in Figure 6.26, the n-channel depletion-mode transistor 2 parameters are: Kn ˆ 0:8mA=V , VTN ˆÀ2 V, and  ˆ 0. (a) Calculate IDQ. (b) Find RD such that VDSQ ˆ 6 V. (c) Determine the small-signal voltage gain. (Ans. (a) IDQ ˆ 0:338 mA; (b) RD ˆ 7:83 k ; (c) Av ˆÀ1:58)

6.14 The parameters of the transistor shown in Figure 6.27 are: VTP ˆ‡0:8V, 2 À1 Kp ˆ 0:5mA=V , and  ˆ 0:02 V . (a) Determine RS and RD such that IDQ ˆ 0:8 mA and VSDQ ˆ 3 V. (b) Find the small-signal voltage gain. (Ans. (a) RS ˆ 5:67 k , RD ˆ 3:08 k ; (b) Av ˆÀ3:73) 334 Part I Semiconductor Devices and Basic Applications

+5 V

VDD = 10 V

RS

RD CC vO CS CC vO v + Ω i – RG = 1 M v + Ω i – RG = 200 k RD Ω RS = 4 k

–5 V

Figure 6.26 Figure for Exercise 6.13 Figure 6.27 Figure for Exercise 6.14

6.4 THE SOURCE-FOLLOWER AMPLIFIER The second type of MOSFET ampli®er to be considered is the common-drain circuit. An example of this circuit con®guration is shown in Figure 6.28. As seen in the ®gure, the output signal is taken off the source with respect to

ground and the drain is connected directly to VDD. Since VDD becomes signal ground in the ac equivalent circuit, we have the name common drain. The more common name is source follower. The reason for this name will become appar- ent as we proceed through the analysis.

VDD

R1 C RSi C

vO vi + – R2 RS

Figure 6.28 NMOS source-follower or common-drain ampli®er

6.4.1 Small-Signal Voltage Gain The dc analysis of the circuit is exactly the same as we have already seen, so we will concentrate on the small-signal analysis. The small-signal equivalent cir- cuit, assumingthe couplingcapacitor acts as a short circuit, is shown in Figure

6.29(a). The drain is at signal ground, and the small-signal resistance ro of the transistor is in parallel with the dependent current source. Figure 6.29(b) is the same equivalent circuit, but with all signal grounds at a common point. We are again neglecting the body effect. The output voltage is Chapter 6 Basic FET Amplifiers 335

RSi Vin GD Ri + R Si Vin g V + V – V Vgs m gs ro gs o

+ + V R  R – Vo V R  R gmVgs R ro i – 1 2 S i – 1 2 D

RS

(a) (b) Figure 6.29 (a) Small-signal equivalent circuit of NMOS source-follower and (b) small- signal equivalent circuit of NMOS source-follower with all signal grounds at a common point

Vo ˆ gmVgs† Rskro† 6:30† Writinga KCL equation from input to output results in the following:

Vin ˆ Vgs ‡ Vo ˆ Vgs ‡ gmVgs Rskro† 6:31 a†† Therefore, the gate-to-source voltage is 2 3 1 V 6 7 in 6 gm 7 vgs ˆ ˆ 4 5 Á Vin 6:31 b†† 1 ‡ gm Rskro† 1 ‡ Rskro† gm Equation (6.31(b)) is written in the form of a voltage-divider equation, in which the gate-to-source of the NMOS device looks like a resistance with a value of 1=gm. More accurately, the effective resistance lookinginto the source terminal (ignoring ro)is1=gm. The voltage Vin is related to the source input voltage Vi by  Ri Vin ˆ Á Vi 6:32† Ri ‡ RSi where Ri ˆ R1kR2 is the input resistance to the ampli®er. SubstitutingEquations (6.31(b)) and (6.32) into (6.30), we have the small- signal voltage gain:  Vo gm RSkro† Ri Av ˆ ˆ Á 6:33 a†† Vi 1 ‡ gm RSkro† Ri ‡ RSi or  Rskro Ri Av ˆ Á 6:33 b†† 1 Ri ‡ RSi ‡ Rskro gm which again is written in the form of a voltage-divider equation. An inspection of Equation 6.33(b) shows that the magnitude of the voltage gain is always less than unity. This result is consistent with the results of the BJT emitter-follower circuit. 336 Part I Semiconductor Devices and Basic Applications

Example 6.7 Objective: Calculate the small-signal voltage gain of the source-fol- lower circuit in Figure 6.28.

Assume the circuit parameters are VDD ˆ 12 V, R1 ˆ 162 k , R2 ˆ 463 k , and 2 RS ˆ 0:75 k , and the transistor parameters are VTN ˆ 1; 5V, Kn ˆ 4mA=V , and À1  ˆ 0:01 V . Also assume RSi ˆ 4k .

Solution: The dc analysis results are IDQ ˆ 7:97 mA and VGSQ ˆ 2:91 V. The small- signal transconductance is therefore

gm ˆ 2Kn VGSQ À VTN †ˆ2 4† 2:91 À 1:5†ˆ11:3mA=V and the small-signal transistor resistance is

À1 À1 ro ‰IDQŠ ˆ‰ 0:01† 7:97†Š ˆ 12:5k The ampli®er input resistance is

Ri ˆ R1kR2 ˆ 162k463 ˆ 120 k The small-signal voltage gain then becomes

gm RSkro† Ri 11:3† 0:75k12:5† 120 Av ˆ Á ˆ Á ˆ‡0:860 1 ‡ gm RSkro† Ri ‡ RSi 1 ‡ 11:3† 0:75k12:5† 120 ‡ 4

Comment: The magnitude of the small-signal voltage gain is less than 1. An examina- tion of Equation (6.33(b)) shows that this is always true. Also, the voltage gain is positive, which means that the output signal voltage is in phase with the input signal voltage. Since the output signal is essentially equal to the input signal, the circuit is called a source follower.

Discussion: The expression for the voltage gain of the source follower is essentially identical to that of the bipolar emitter follower. Since the transconductance of the BJT is, in ingeneral, larger than that of the MOSFET, the voltage gain of the emitter follower will be closer to unity than that of the MOSFET source follower.

Although the voltage gain is slightly less than 1, the source-follower is an extremely useful circuit because the output resistance is less than that of a common-sosurce circuit. A small output resistance is desirable when the circuit is to act as an ideal voltage source and drive a load circuit without suffering any loadingeffects.

Test Your Understanding

6.15 For an NMOS source-follower circuit, the parameters are gm ˆ 4 mA/V and ro ˆ 50 k . (a) Find the no load RS ˆ1† small-signal voltage gain and the output resistance. (b) Determine the small-signal voltage gain when a 4 k load is connected to

the output. (Ans. (a) Av ˆ 0:995, Ro  0:25 k ; (b) Av ˆ 0:937) D6.16 The source-follower circuit in Figure 6.28 has transistor parameters 2 À1 VTN ˆ‡0:8V, Kn ˆ 1mA=V , and  ˆ 0:015 V . Let VDD ˆ 10 V, RSi ˆ 200 , and R1 ‡ R2 ˆ 400 k . Design the circuit such that IDQ ˆ 1:5 mA and VDSQ ˆ 5V. Determine the small-signal voltage gain and the output resistance. (Ans.

RS ˆ 3:33 k , R1 ˆ 119 k , R2 ˆ 281; k , Av ˆ 0:884, and Ro ˆ 0:36 k ) Chapter 6 Basic FET Amplifiers 337

Design Example 6.8 Objective: Design a speci®c source follower with a p-channel enhancement-mode MOSFET.

For the circuit in Figure 6.30, the transistor parameters are VTP ˆÀ2V, 0 2 kp ˆ 40 mA=V , and  ˆ 0. The circuit parameters are VDD ˆ 20 V and RSi ˆ 4k . The circuit is to be designed such that VSDQ ˆ 10 V, IDQ ˆ 2:5 mA, and Ri ˆ 50 k , and the transistor width-to-length ratio is to be designed such that the small-signal voltage gain is Av ˆ 0:90:

VDD

RS R Ri 1 vO C RSi C1

vi + – R2

Figure 6.30 PMOS source follower

Solution: From the dc analysis, we have

VDD ˆ VSDQ ‡ IDQRS or

20 ˆ 10 ‡ 2:5RS The required source resistance value is therefore

RS ˆ 4k The small-signal voltage gain of this circuit is the same as that of a source-follower usingan NMOS device. From Equation (6.33(a)), we have  Vo gmRS Ri Av ˆ ˆ Á Vi 1 ‡ gmRS Ri ‡ RSi or  g 4† 50 0:90 ˆ m Á 1 ‡ gm 4† 50 ‡ 4 which yields g 4† 0:972 ˆ m 1 ‡ gm 4† Therefore, the required small-signal transconductance is

gm ˆ 8:68 mA=V Since the transconductance can be written as p gm ˆ 2 KpIDQ 338 Part I Semiconductor Devices and Basic Applications

we have q À3 À3 8:68  10 ˆ 2 Kp 2:5  10 †

which yields K ‡ p ˆ 7:53  10À3 A=V2 The conduction parameter, which is a function of the width-to-length ratio, is  ! W 1 W 40  10À6 K ˆ 7:53  10À3 ˆ k 0 ˆ p L 2 p L 2

which means that the width-to-length ratio is W ˆ 377 L This is a relatively large p-channel transistor. Completingthe dc analysis, we have

2 IDQ ˆ Kp VSGQ ‡ VTP† or

2 2:5 ˆ 7:53 VSGQ À 2† which yields a quiescent source-to-gate voltage of

VSGQ ˆ 2:58 V The quiescent source-to-gate voltage can also be written as  R2 VSGQ ˆ VDD À IDQRS†À VDD† R1 ‡ R2 Since  R2 1 R1R2 1 ˆ ˆ Ri R1 ‡ R2 R1 R1 ‡ R2 R1 we have  1 2:58 ˆ‰20 À 2:5† 4†Š À 50† 20† R1

the bias resistor R1 is then found to be

R1 ˆ 135 k Since

Ri ˆ R1kr2 ˆ 50 k then

R2 ˆ 79:4k

Comment: In order to achieve the desired speci®cations, a relatively large transcon- ductance is required, which means that a large transistor is needed. If the load effect

were reduced, that is, if RI were made larger, the required size of the transistor could be reduced. Chapter 6 Basic FET Amplifiers 339

6.4.2 Input andOutput Impedance

The input resistance Ri as de®ned in Figure 6.29(b), for example, is the Thevenin equivalent resistance of the bias resistors. Even though the input resistance to the gate of the MOSFET is essentially in®nite, the input bias resistances do provide a loadingeffect. This same effect was seen in the com- mon-source circuits. To calculate the output resistance, we set all independent small-signal sources equal to zero, apply a test voltage to the output terminals, and measure a test current. Figure 6.31 shows the circuit we will use to determine the output resistance of the source-follower shown in Figure 6.28. We set Vi ˆ 0 and apply a test voltage Vx. Since there are no capacitances in the circuit, the output impedance is simply an output resistance, which is de®ned as

Vx Ro ˆ 6:34† Ix

Ro RSi + Vgs –

Ix g V r + R1 R2 m gs RS o – Vx

Figure 6.31 Equivalent circuit of NMOS source-follower, for determining output resistance

Writinga KCL equation at the output source terminal produces

Vx Vx Ix ˆ gmVgs ˆ ‡ 6:35† RS ro Since there is no current in the input portion of the circuit, we see that Vgs ˆÀVx. Therefore, Equation (6.35) becomes  1 1 Ix ˆ Vx gm ‡ ‡ 6:36 a†† RS ro or

Ix 1 1 1 ˆ ˆ gm ‡ ‡ 6:36 b†† Vx Ro RS ro The output resistance is then

1 Ro ˆ kRSkro 6:37† gm

From Figure 6.31, we see that the voltage Vgs is directly across the current source gmVgs. This means that the effective resistance of the device is 1=gm. The output resistance given by Equation (6.37) can therefore be written directly. This result also means that the resistance lookinginto the source terminal (ignoring ro)is1=gm, as previously noted. 340 Part I Semiconductor Devices and Basic Applications

Example 6.9 Objective: Calculate the output resistance of a source-follower circuit. Consider the circuit shown in Figure 6.28 with circuit and transistor parameters given in Example 6.7.

Solution: The results of Example 6.7 are: RS ˆ 0:75 k , ro ˆ 12:5k , and gm ˆ 11:3mA=V. UsingFigure6.31 and Equation (6.37), we ®nd 1 1 Ro ˆ kRSkro ˆ k0:75k12:5 gm 11:3 or

Ro ˆ 0:0787 k ˆ 78:7

Comment: The output resistance of a source-follower circuit is dominated by the transconductance parameter. Also, because the output resistance is very low, the source-follower tends to act like an ideal voltage source, which means that the output can drive another circuit without signi®cant loading effects.

Test Your Understanding

*6.17 Consider the circuit shown in Figure 6.30 with circuit parameters VDD ˆ 5V, RS ˆ 5k , R1 ˆ 70:7k , R2 ˆ 9:3k , and RSi ˆ 500 . The transistor parameters are: 2 VTP ˆÀ0:8V, Kp ˆ 0:4mA=V , and  ˆ 0. Calculate the small-signal voltage gain Av ˆ vo=vi and the output resistance Ro seen lookingback into the circuit. (Ans. Av ˆ 0:817, Ro ˆ 0:915 k ) D6.18 The transistor in the source-follower circuit shown in Figure 6.32 is biased

with a constant current source. The transistor parameters are: VTN ˆ 2V, 0 2 À1 kn ˆ 40 mA=V , and  ˆ 0:01 V . The load resistor is RL ˆ 4k . (a) Design the tran- sistor width-to-length ratio such that gm ˆ 2 mA/V when I ˆ 0:8 mA. What is the cor- respondingvalue for VGS? (b) Determine the small-signal voltage gain and the output resistance Ro. (Ans. (a) W=L ˆ 62:5, VGS ˆ 2:8 V; (b) Av ˆ 0:886, Ro  0:5k )

+9 V

Ro CC v + R = vo i – G 100 kΩ

I RL

–9 V Figure 6.31 Equivalent circuit of NMOS source-follower, for determining output resistance

*D6.19 The parameters of the transistor in the source-follower circuit shown in 2 À1 Figure 6.33 are: VTP ˆÀ2V, Kp ˆ 2mA=V , and  ˆ 0:02 V . Design the circuit such that IDQW ˆ 3 mA. Determine the open-circuit RL ˆ1† small-signal voltage Chapter 6 Basic FET Amplifiers 341

+5 V

RS

vo CC1 CC2

RL v + R = i – G 500 kΩ

–5 V Figure 6.33 Figure for Exercise 6.19

gain. What value of RL will result in a 10 percent reduction in the gain? (Ans. RS ˆ 0:593 k , Av ˆ 0:737, RL ˆ 1:35 k )

6.5 THE COMMON-GATE CONFIGURATION The third ampli®er con®guration is the common-gate circuit. To determine the small-signal voltage and current gains, and the input and output impedances, we will use the same small-signal equivalent circuit for the transistor that was used previously. The dc analysis of the common-gate circuit is the same as that of previous MOSFET circuits.

6.5.1 Small-Signal Voltage andCurrent Gains In the common-gate con®guration, the input signal is applied to the source terminal and the gate is at signal ground. The common-gate con®guration shown in Figure 6.34 is biased with a constant-current source IQ. The gate resistor RD prevents the buildup of static charge on the gate terminal, and the capacitor CG ensures that the gate is at signal ground. The coupling capacitor CC1 couples the signal to the source, and coupling capacitor CC2 couples the output voltage to load resistance RL. The small-signal equivalent circuit is shown in Figure 6.35. The small- signal transistor resistance ro is assumed to be in®nite. The output voltage is

Ri C C RSi C1 C2 vo

ii v + I i – Q RD RL

RG CG V – V+

Figure 6.34 Common-gate circuit 342 Part I Semiconductor Devices and Basic Applications

Ri gmVgs Ro RSi S V – o I i V V + gs i – + RD Io RL G

Figure 6.35 Small-signal equivalent circuit of common-gate ampli®er

Vo ˆÀ gmVgs† RDkRL† 6:38†

Writingthe KVL equation around the input, we ®nd

Vi ˆ IiRSi À Vgs 6:39†

where Ii ˆÀgmVgs. The gate-to-source voltage can then be written as ÀV V À gs ˆ 6:40† 1 ‡ gmRSi The small-signal voltage gain is found to be

Vo gm RDkRL† Av ˆ ˆ 6:41† Vi 1 ‡ gmRSi Also, since the voltage gain is positive, the output and input signals are in phase. In many cases, the signal input to a common-gate circuit is a current. Figure 6.36 shows the small-signal equivalent common-gate circuit with a Norton equivalent circuit as the signal source. We can calculate a current gain. The output current Io can be written  RD Io ˆ ÀgmVgs† 6:42† RD ‡ RL At the input we have

Vgs Ii ˆ gmVgs ‡ ˆ 0 6:43† RSi

Figure 6.36 Small-signal equivalent circuit of common-gate ampli®er with a Norton equivalent signal source Chapter 6 Basic FET Amplifiers 343 or  RSi Vgs ˆÀIi 6:44† 1 ‡ gmRSi The small-signal current gain is then  Io RD gmRSi Ai ˆ ˆ Á 6:45† Ii RD ‡ RL 1 ‡ gmRSi

We may note that if RD  RL and gmRSi  1, then the current gain is essen- tially unity as it is for an ideal BJT common-base circuit.

6.5.2 Input andOutput Impedance In contrast to the common-source and source-follower ampli®ers, the com- mon-gate circuit has a low input resistance because of the transistor. However, if the input signal is a current, a low input resistance is an advantage. The input resistance is de®ned as

ÀVgs Ri ˆ 6:46† Ii

Since Ii ˆÀgmVgs, the input resistance is 1 Ri ˆ 6:47† gm This result has been obtained previously. We can ®nd the output resistance by setting the input signal voltage equal to zero. From Figure 6.35, we see tht Vgs ˆÀgmVgsRSi, which means that Vgs ˆ 0. Consequently, gmVgs ˆ 0. The output resistance, lookingback from the load resistance, is therefore

Ro ˆ RD 6:48†

Example 6.10 Objective: For the common-gate circuit, determine the output vol- tage for a given input current.

For the circuit shown in Figure 6.36, the circuit parameters are: IQ ˆ 1 mA, ‡ À V ˆ 5V,V ˆÀ5V,RG ˆ 100 k , RD ˆ 4k , and RL ˆ 10 k . The transistor para- 2 meters are: VTN ˆ 1V, Kn ˆ 1mA=V , and  ˆ 0. Assume the input current is 100 sin !t mA. Solution: The quiescent gate-to-source voltage is determined from

2 IQ ˆ IDQ ˆ Kn VGSQ À VTN † or

2 1 ˆ 1 VGSQ À 1† which yields

VGSQ ˆ 2V The small-signal transconductance is 344 Part I Semiconductor Devices and Basic Applications

gm ˆ 2Kn VGSQ À VTN †ˆ2 1† 2 À 1†ˆ2mA=V

From Equation (6.45), we can write the output current as  RD gmRSi Io ˆ Ii Á RD ‡ RL 1 ‡ gmRSi

The output voltage is Vo ˆ IoRK , so we ®nd  RLRD gmRSi Vo ˆ Ii Á RD ‡ RL 1 ‡ gmRSi  10† 4† 2† 50† ˆ Á Á 0:1† sin !t 4 ‡ 10 1 ‡ 2† 50†

or

Vo ˆ 0:283 sin !t V

Comment: As with the BJT common-base circuit, the MOSFET common-gate ampli- ®er is useful if the input signal is a current

Test Your Understanding

RD6.20 For the circuit shown in Figure 6.34, the circuit parameters are: V‡ ˆ 5V, À V ˆÀ5V, RG ˆ 100 k , RL ˆ 4k , and IQ ˆ 0:5 mA. The transistor parameters are VTN ˆ 1 V and  ˆ 0. The circuit is driven by a signal current source Ii. Redesign RD and gm such that the transfer function Vo=Ii is 2.4 k and the output resistance is Ri ˆ 350 : Determine VGSQ and show that the transistor is biased in the saturation region. (Ans. gm ˆ 2:86 mA/V, RD ˆ 6k , VGSQ ˆ 1:35 V) 6.21 Consider the circuit shown in Figure 6.37 with circuit parameters V‡ ˆ 5V, À V ˆÀ5V, RS ˆ 4k , RD ˆ 2k , RL ˆ 4k and RG ˆ 50 k . The transistor para- 2 meters are: Kp ˆ 1mA=V , VTP ˆÀ0:8 V, and  ˆ 0. Draw the small-signal equivalent circuit, determine the small-signal voltage gain Av ˆ Vo=Vi, and ®nd the input resistance Ri. (Ans. Av ˆ 2:41, Ri ˆ 0:485 k )

Ri

CC1 CC2 vo

v + i – RS RD RL

RG CG V + V –

Figure 6.37 Figure for Exercise 6.21 Chapter 6 Basic FET Amplifiers 345

6.6 THE THREE BASIC AMPLIFIER CONFIGURATIONS: SUMMARY AND COMPARISON Table 6.1 is a summary of the small-signal characteristics of the three ampli®er con®gurations.

Table 6.1 Characteristics of the three MOSFET ampli®er con®gurations Con®guration Voltage gain Current gain Input resistance Output resistance

Common source Av > 1Ð RTH Moderate to high Source follower Av  1Ð RTH Low Common gate Av > 1 Ai  1 Low Moderate to high

The common-source ampli®er voltage gain is generally greater than 1. The voltage gain of the source-follower is slightly less than1, and that of the com- mon-gate circuit is generally greater than 1. The input resistance lookingdirectly into the gateof the common-source and source-follower circuits is essentially in®nite at low to moderate signal frequencies. However, the input resistance of these discrete ampli®ers is the

Thevenin equivalent resistance RTH of the bias resistors. In contrast, the input resistance to the common-gate circuit is generally in the range of only a few hundred ohms. The output resistance of the source follower is generally in the range of a few hundred ohms or less. The output resistance of the common-source and common-gate con®gurations is dominated by the resistance RD. In Chapters 10 and 11, we will see that the output resistance of these con®gurations is domi- nated by the resistance ro when transistors are used as load devices in ICs. The speci®c characteristics of these single-stage ampli®ers are used in the design of multistage ampli®ers.

6.7 SINGLE-STAGE INTEGRATED CIRCUIT MOSFET AMPLIFIERS In the last chapter, we considered three all-MOSFET inverters and plotted the voltage transfer characteristics. All three inverters use an n-channel enhance- ment-mode driver transistor. The three types of load devices are an n-channel enhancement-mode device, an n-channel depletion-mode device, and a p-chan- nel enhancement-mode device. The MOS transistor used as a load device is referred to as an active load. We mentioned that these three circuits can be used as ampli®ers. In this section, we revisit these three circuits and consider their ampli®er characteristics. We will emphasize the small-signal equivalent circuits. This section serves as an introduction to more advanced MOS integrated circuit ampli®er designs considered in Part II of the text.

6.7.1 NMOS Amplifiers with Enhancement Load The characteristics of an n-channel enhancement load device were presented in the last chapter. Figure 6.38(a) shows an NMOS enhancement load transistor, 346 Part I Semiconductor Devices and Basic Applications

iD

VDS (sat) = VGS – VTNL

Transistor characteristics iD(max)

iD

+ vDS –

VTNL vDD vDS (a) (b) Figure 6.38 (a) NMOS enhancement-mode transistor with gate and drain connected in a load device con®guration and (b) current±voltage characteristics of NMOS enhancement load transistor

and Figure 6.38(b) shows the current±voltage characteristics. The threshold

voltage is VTNL. Figure 6.39(a) shows an NMOS ampli®er with enhancement load. The

driver transistor is MD and the load transistor is ML. The characteristics of transistor MD and the load curve are shown in Figure 6.39(b). The load curve is essentially the mirror image of the i±v characteristic of the load device. Since the iÀv characteristics of the load device are nonlinear, the load curve is also

nonlinear. The load curve intersects the voltage axis at VDD À VTNL, which is the point where the current in the enhancement load device goes to zero. The transistion point is also shown on the curve. The voltage transfer characteristic is also useful in visualizing the opera- tion of the ampli®er. This curve is shown in Figure 6.39(c). When the enhance- ment-mode driver ®rst begins to conduct, it is biased in the saturation region. For use as an ampli®er, the circuit Q-point should be in this region, as shown in both Figures 6.39(b) and (c). We can now apply the small-signal equivalent circuits to ®nd the voltage gain. In the discussion of the source-follower, we found that the equivalent

resistance lookinginto the source terminal (with RS ˆ1) was Ro ˆ 1=gm†kro. The small-signal equivalent circuit of the inverter is given in Figure 6.40, where the subscripts D and L refer to the driver and load transistors, respectively. We are again neglecting the body effect of the load transistor. The small-signal voltage gain is then



Vo 1 Av ˆ ˆÀgmD roD roL 6:49† Vi gmL

Since, generally, 1=gmL  roL and r=gmD  roD, the voltage gain, to a good approximation is given by Chapter 6 Basic FET Amplifiers 347

VDD

iD iD

+ iD(max) ML vDSL + – vGSL – vO Transition point + Q-point MD vDSD + + – Load curve vi – vGSD – + V GS V – DD vDSD = vO VTNL

(a) (b)

vO

MD MD in MD in cut-off saturation nonsaturation

VDD – VTNL Cutoff point

Q-point

Transition point

0 VTND vGSD (c)

Figure 6.39 (a) NMOS ampli®er with enhancement load device; (b) driver transistor characteristics and enhancement load curve with transition point; and (c) voltage transfer characteristics of NMOS ampli®er with enhancement load device

Figure 6.40 Small-signal equivalent circuit of NMOS inverter with enhancement load device. 348 Part I Semiconductor Devices and Basic Applications

s s ÀgmD KnD W=L†D Av ˆ ˆÀ ˆÀ 6:50† gmL KnL W=L†L

The voltage gain, then, is related to the size of the two transistors.

Design Example 6.11 Objective: Design the small-signal voltage gain of an NMOS ampli®er with enhancement load, and establish the Q-point in the middle of the saturation region. Consider the circuit shown in Figure 6.39(a) with transistor parameters 0 2 VTND ˆ VTNL ˆ 1V, kn ˆ 30 mA=V , W=L†L ˆ 1. The circuit parameter is VDD ˆ 5V. Design the circuit such that the voltage gain is jAvjˆ10. Solution: From Equation (6.50), we have s W=L†D jAvjˆ10 ˆ W=L†L

Therefore, the width-to-length ratio of the driver transistor must be   W W ˆ 10†2 ˆ 100† 1†ˆ100 L D L L

The conduction parameters are then  W 1 0 2 KnD ˆ kn ˆ 100† 15†)1:5mA=V L D 2

and  W 1 0 2 KnL ˆ kn ˆ 1† 15†)0:015 mA=V L L 2

We can determine the transition point by setting

vO ˆ vGSD À VTND

Therefore, s KnD vGSD À VTND ˆ VDD À VTNL†À vGSD À VTND† KnL

or r 1:5 v À 1 ˆ 5 À 1†À v À 1† GSD 0:015 GSD

which yields transition point values of

vGSD ˆ 1:36 V and vDSD À 0:36 V Chapter 6 Basic FET Amplifiers 349

Considering the resulting voltage transfer characteristics shown in Figure 6.41, the middle of the saturation region is halfway between the cutoff point

(vGSD ˆ VTND ˆ 1 V) and the transition point vGSD ˆ 1:36 V), or

VGSQ ˆ 1:18 V

vO (V) 5

Cut-off point 4

3

Q-point VDSDQ = 2.18 2

1 Transition point 0.36

0 1.0 1.2 1.4 1.6 vGSD (V) VGSQ = 1.18 V 1.36 V Figure 6.41 Voltage transfer characteristics and Q-point of NMOS ampli®er with enhancement load, for Example 6.11

Comment: These results show that a very large difference is required in the sizes of the two transistors to produce a gain of 10. In fact, a gain of 10 is about the largest practical gain that can be produced by an enhancement load device. A larger small-signal gain can be obtained by usinga depletion-mode MOSFET as a load device, as shown in the next section.

Design Pointer: The body effect of the load transistor was neglected in this analysis. The body effect will actally lower the small-signal voltage gain from that determined in the example.

Test Your Understanding

6.22 For the enhancement load ampli®er shown in ®gure 6.39(a), the parameters 0 2 are: VTND ˆ VTNL ˆ 0:8V,kn ˆ 40 mA=V , W=L†D ˆ 80, W=L†L ˆ 1, and VDD ˆ 5V. Determine the small-signal voltage gain. Determine VGS such that the Q-point is in the middle of the saturation region. (Ans. Av ˆÀ8:94, VGS ˆ 1:01 V) D6.23 For the enhancement load ampli®er shown in Figure 6.39(a), the parameters 0 2 are: VTND ˆ VTNL ˆ 1V, kn ˆ 30 ma=V , W=L†L ˆ 2, and VDD ˆ 10 V. Design the cir- cuit such that the small-signal voltage gain is jAvjˆ6 and the Q-point is in the center of the saturation region. (Ans. W=L†D ˆ 72, VGS ˆ 1:645 V) 350 Part I Semiconductor Devices and Basic Applications

6.7.2 NMOS Amplifier with Depletion Load Figure 6.42(a) shows the NMOS depletion-mode transistor connected as a load device and Figure 6.42(b) shows the current±voltage characteristics. The tran-

sition point is also indicated. The threshold voltage VTNL of this device is negative, which means that the vDS value at the transition point is positive. Also, the slope of the curve in the saturation region is not zero; therefore, a

®nite resistance ro exists in this region.

iD

iD vDS (sat) = – VTNL vGS = 0 iD(max) 1 + Slope = r v O DS Transition – point

vDD vDS (a) (b)

Figure 6.42 (a) NMOS depletion-mode transistor with gate and source connected in a load device con®guration and (b) current±voltage characteristic of NMOS depletion load transistor

Figure 6.43(a) shows an NMOS depletion load ampli®er. The transistor

characteristics of MD and the load curve for the cicuit are shown in Figure 6.43(b). The load curve, again, is the mirror image of the iÀv characteristic of the load device. Since the iÀv characteristics of the load device are nonlienar,

the load curve is also nonlinear. The transistion points for both MD and ML are also indicated. Point A is the transition point for MD, and point B is the transistion point for ML. The Q-point should be approximately midway between the two transition points.

The dc voltage VGSDQ biases transistor MD in the saturation region at the Q-point. The signal voltage vi superimposes a sinuosoidal gate-to-source vol- tage on the dc value, and the bias point moves along the load curve about the

Q-point. Again, both MD and ML must be biased in their saturation regions at all times. The voltage transfer characteristics of this circuit is shown in Figure 6.43(c). Region III corresponds to the condition in which both transistors are biased in the saturation region. The desired Q-point is indicated. We can again apply the small-signal equivalent circuit to ®nd the small- signal voltage gain. Since the gate-to-source voltage of the depletion-load device is held at zero, the equivalent resistance lookinginto the source term-

inal is Ro ˆ ro. The small-signal equivalent circuit of the inverter is given in Figure 6.44, where the subscripts D and L refer to the driver and load transistors, respectively. We are again neglecting the body effect of the load device. Chapter 6 Basic FET Amplifiers 351

VDD

iD iD

+ VGSDQ Load curve Q-point ML vDSL – A

vO

+ iD(max) MD vDSD – v + i – + VGSDQ B C – VDD vDSD

(a) (b)

vO I II III IIIV

VDD C

  VDD – VTNL B

Q-point

A

0 VTND vGSD (c)

Figure 6.43 (a) NMOS ampli®er with depletion load device; (b) driver transistor characteristics and depletion load curve, with transition points; and (c) voltage transfer characteristics

Figure 6.44 Small-signal equivalent circuit of NMOS inverter with depletion load device 352 Part I Semiconductor Devices and Basic Applications

The small-signal voltage gain is then

Vo Av ˆ ˆÀgmD roDkroL† 6:51† Vi

In this circuit, the voltage gain is directly proportional to the output resistances of the two transistors.

Example 6.12 Objective: Determine the small-signal voltage gain of the NMOS ampli®er with depletion load. For the circuit shown in Figure 6.43(a), assume transistor parameters of 2 2 VTND ˆ‡0:8V, VTNL ˆÀ1:5V, KnD ˆ 1mA=V , KnL ˆ 0:2mA=V , and À1 D ˆ L ˆ 0:01 V . Assume the transistors are biased at IDQ ˆ 0:2 mA. Solution: The transconductance of the driver is

p p gmD ˆ 2 KnDIDQ ˆ 2 1† 0:2† ˆ 0:894 mA=V

Since D ˆ L, the output resistances are

1 1 roD ˆ roL ˆ ˆ ˆ 500 k IDQ 0:01† 0:2†

The small-signal voltage gain is then

Av ˆÀgmD roDkroL†ˆÀ 0:894† 500k500†ˆÀ224

Comment: The voltage gain of the NMOS ampli®er with depletion load is, in general, signi®cantly larger than that with the enhancement load device. The body effect will lower the ideal gain factor.

Discussion: One aspect of this circuit design that we have not emphasized is the dc biasing. We mentioned that both transistors need to be biased in their saturation regions. From Figure 6.43(a), this dc biasing is accomplished with the dc source

VGSDQ. However, because of the steep slope of the transfer characteristics (Figure 6.43(c)), applyingthe ``correct'' voltagebecomes dif®cult. As we will see in the next section, dc biasing is generally accomplished with current source biasing.

Test Your Understanding

*6.24 For the depletion load ampli®er in Figure 6.43(a), the parameters are: 2 2 VTND ˆ 0:8V, VTNL ˆÀ1:2V, KnD ˆ 250 mA=V , KnL ˆ 25 mA=V , D ˆ L ˆ À1 0:01 V , and VDD ˆ 5 V. (a) Determine VGS such that the Q-point is in the middle of the saturation region. (b) Calculate the quiescent drain current. (c) Determine the small-

signal voltage gain. (Ans. (a) VGS ˆ 1:18 V; (b) IDQ ˆ 37 mA; (c) Av ˆÀ257) Chapter 6 Basic FET Amplifiers 353

6.7.3 NMOS Amplifier with PMOS Load Common-Source Ampli®er An ampli®er usingan n-channel enhancement-mode driver and a p-channel enhancement mode active load is shown in Figure 6.45(a) in a common-source con®guration. The p-channel active load transistor M2 is biased from M3 and IBias. This con®guration is similar to the MOSFET current source shown in Figure 5.39 in Chapter 5. With both n- and p-channel transistors in the same circuit, this circuit is now referred to as a CMOS ampli®er.

The iÀv characteristic curve for M2 is shown in Figure 6.45(b). The source- to-gate voltage is a constant and is established by M3. The driver transistor characteristics and the load curve are shown in Figure 6.45(c). The transistion points of both M1 and M2 are shown. Point A is the transistion point for M1 and point B is the transition point for M2. The Q-point, to establish an ampli- ®er, should be approximately halfway between points A and B, so that both transistors are biased in their saturation regions. The voltage transfer charac- teristics are shown in Figure 6.45(d). Shown on the curve are the same transi- tion points A and B and the desired Q-point. We again apply the small-signal equivalent circuits to ®nd the small-signal voltage gain. With vSG2 held constant, the equivalent resistance lookinginto the

Figure 6.45 (a) CMOS common-source ampli®er; (b) PMOS active load iÀv characteristic, (c) driver transistor characteristics with load curve, (d) voltage transfer characteristics 354 Part I Semiconductor Devices and Basic Applications

drain of M2 is just Ro ˆ rop. The small-signal equivalent circuit of the inverter is then as given in Figure 6.46. The subscripts n and p refer to the n-channel and p-channel transistors, respectively. We may note that the body terminal of

M1 will be tied to ground, which is the same as the source of M1, and the body terminal of M2 will be tied to VDD, which is the same as the source of M2. Hence, there is no body effect in this circuit. The small-signal voltage gain is

Vo Av ˆ ˆÀgmn ronkrop† Vi

Again for this circuit, the small-signal voltage gain is directly proportional to the output resistances of the two transistors.

Figure 6.46 Small-signal equivalent circuit of the CMOS common-source ampli®er

Example 6.13 Objective: Determine the small-signal voltage gain of the CMOS ampli®er. For the circuit shown in Figure 6.45(a), assume transistor parameters of 0 2 0 2 VTN ˆ‡0:8V, VTP ˆÀ0:8V, kn ˆ 80 mA=V , kp ˆ 40 mA=V , W=L†n ˆ 15, À1 W=L†p ˆ 30, and n ˆ p ˆ 0:01 V . Also, assume IBias ˆ 0:2 mA. Solution: The transconductance of the NMOS driver is s 0 p kn W gmn ˆ 2 KnIDQ ˆ 2 IBias 2 L n s 0:08 ˆ 2 15† 0:2† ˆ 0:693 mA=V 2

Since n À p, the output resistances are 1 1 ron ˆ rop ˆ ˆ ˆ 500 k IDQ 0:01† 0:2†

The small-signal voltage gain is then

Av ˆÀgm ronkrop†ˆÀ 0:693† 500k500†ˆÀ173

Comment: The voltage gain of the CMOS ampli®er is on the same order of magnitude as the NMOS ampli®er with depletion load. However, the CMOS ampli®er does not suffer from the body effect. Chapter 6 Basic FET Amplifiers 355

Discussion: In the circuit con®guration shown in Figure 6.45(a), we must again apply a dc voltage to the gate of M1 to achieve the ``proper'' Q-point. We will show in later chapters usingmore sophisticated circuits how the Q-point is more easily established with current-source biasing. However, this circuit demonstrates the basic principles of the CMOS common-source ampli®er.

CMOS Source-Follower and Common-Gate Ampli®ers The same basic CMOS circuit con®guration can be used to form CMOS source-follower and common-gate con®gurations. Figure 6.47(a) and (b) show these circuits.

We see that for the source-follower circuit, the active load M2† is an n- channel rather than a p-channel device. The input is applied to the gate of M1 and the output is at the source of M1. For the common-gate ampli®er, the active load M2† is again a p-channel device. The input is applied to the source of M1 and the output is at the drain of M1. We may note that in both the source-follower and common-gate circuits, the body effect will need to be taken into account. In both circuits, the body terminal of the amplifyingtransistor M1 will be connected to the most negative voltage, which is not the same as the source terminal. We will consider these types of circuits in detail in later chapters.

Figure 6.47 (a) CMOS source-follower ampli®er; (b) CMOS common-gate ampli®er

6.8 MULTISTAGE AMPLIFIERS In most applications, a single-transistor ampli®er will not be able to meet the combined speci®cations of a given ampli®cation factor, input resistance, and output resistance. For example, the requried voltage gain may exceed that which can be obtained in a single-transistor circuit. 356 Part I Semiconductor Devices and Basic Applications

Transistor ampli®er circuits can be connected in series, or cascaded,as shown in Figure 6.48. This may be done either to increase the overall small- signal voltage gain, or provide an overall voltage gain greater than 1, with a very low output resistance. The overall voltage gain may not simply be the product of the individual ampli®cation factors. Loadingeffects, in general, need to be taken into account. There are many possible multistage con®gurations; we will examine a few here, in order to understand the type of analysis required.

+ + Stage 1 Stage 2 vi vo AV1 AV2 – AV1 –

Ri1 Ro1 Ri2 Ro2 Figure 6.48 Generalized two-stage ampli®er

6.8.1 DC Analysis The circuit shown in Figure 6.49 is a cascade of a common-source ampli®er followed by a source-follower ampli®er. As shown previously, the common- source ampli®er provides a small-signal voltage gain and the source-follower has a low output impedance.

V + = 5 V

RD1 Ri R1

RSi CC R M1 M2 o CC2 vo vi + – R 2 R = RS1 CS RS2 L 4 kΩ

V – = –5 V Figure 6.49 Common-source ampli®er in cascade with source-follower Chapter 6 Basic FET Amplifiers 357

Design Example 6.14 Objective: Design the biasingof a multistageMOSFET circuit to meet speci®c requirements. Consider the circuit shown in Figure 6.49 with transistor parameters 2 2 Kn1 ˆ 500 mA=V , Kn2 ˆ 200 mA=V , VTN1 ˆ VTN2 ˆ 1:2 V, and 1 ˆ 2 ˆ 0. Design the circuit such that IDQ1 ˆ 0:2 mA, IDQ2 ˆ 0:5 mA, VDSQ1 ˆ VDSQ2 ˆ 6 V, and Ri ˆ 100 k . Let RSi ˆ 4k :

Solution: For output transistor M2, we have

VDSQ2 ˆ 5 À À5†ÀIDQ2RS2 or

6 ˆ 10 À 0:5†RS2 which yields RS2 ˆ 8k . Also,

2 IDQ2 ˆ Kn2 VGS2 À VTN2† or

2 0:5 ˆ 0:2 VGS2 À 1:2† which yields

VGS2 ˆ 2:78 V

Since VDSQ2 ˆ 6 V, the source voltage of M2 is VS2 ˆÀ1 V. With VGS2 ˆ 2:78 V, the gate voltage on M2 must be

VG2 ˆÀ1 ‡ 2:78 ˆ 1:78 V

The resistor RD1 is then 5 À 1:78 R ˆ ˆ 16:1k D1 0:2

For VDSQ1 ˆ 6 V, the source voltage of M1 is

VS1 ˆ 1:78 À 6 ˆÀ4:22 V

The resistor RS1 is then À4:22 À À5† R ˆ ˆ 3:9k S1 0:2

For transistor M1, we have

2 IDQ1 ˆ Kn1 VGS1 À VTN1† or

2 0:2 ˆ 0:50 VGS1 À 1:2† which yields

VGS1 ˆ 1:83 V

To ®nd R1 and R2, we can write  R2 VGS1 ˆ 10†ÀIDQ1RS1 R1 ‡ R2 Since 358 Part I Semiconductor Devices and Basic Applications

 R2 1 R1R2 1 ˆ Á ˆ Á Ri R1 ‡ R2 R1 R1 ‡ R2 R1

then

1 1:83 ˆ 100† 10†À 0:2† 3:9† R1

which yields R1 ˆ 383 k . From R ˆ 100 k , we ®nd that R2 ˆ 135 k . Comment: Both transistors are biased in the saturation region, which is desired for linear ampli®ers.

Figure 6.50 shows a cascode circuit with n-channel MOSFETs. Transistor

M1 is connected in a common source con®guration and M2 is connected in a common-gate con®guration. The advantage of this type of circuit is a higher frequency response, which is discussed in a later chapter.

V + = 5 V

RD R1 vO CG M2

R2 CC M1

v + i – R3 RS CS

V – = –5 V Figure 6.50 NMOS cascode circuit

Design Example 6.15 Objective: Design the biasingof the cascode circuit to meet speci®c requirements.

For the circuit shown in Figure 6.50, the transistor parameters are: VTN1 ˆ 2 VTN2 ˆ 1:2V, Kn1 ˆ Kn2 ˆ 0:8mA=V , and 1 ˆ 2 ˆ 0. Let R1 ‡ R2 ‡ R3 ˆ 300 k and RS ˆ 10 k . Design the circuit such that IDQ ˆ 0:4 mA and VDSQ1 ˆ VDSQ2 ˆ 2:5V.

Solution: The dc voltage at the source of M1 is

VS1 ˆ IDQRS À 5 ˆ 0:4† 10†À5 ˆÀ1V Chapter 6 Basic FET Amplifiers 359

Since M1 and M2 are identical transistors, and since the same current exists in the two transistors, the gate-to-source voltage is the same for both devices. We have

2 ID ˆ Kn VGS À VTN † or

2 0:4 ˆ 0:8 VGS À 1:2† which yields

VGS ˆ 1:91 V Then,  R3 VG1 ˆ 5†ˆVGS ‡ VS1 R1 ‡ R2 ‡ R3 or  R 3 5†ˆ1:91 À 1 ˆ 0:91 300 which yields

R3 ˆ 54:6k

The voltage at the source of M2 is

VS2 ˆ VDSQ2 ‡ VS2 ˆ 2:5 À 1 ˆ 1:5V Then,  R2 ‡ R3 VG2 ˆ 5†ˆVGS ‡ VS2 R1 ‡ R2 ‡ R3 or  R ‡ R 2 3 5†ˆ1:91 ‡ 1:5 ˆ 3:41 V 300 which yields

R2 ‡ R3 ˆ 204:6k and

R2 ˆ 150 k Therefore

R1 ˆ 95:4k

The voltage at the drain of M2 is

VD2 ˆ VDSQ2 ‡ VS2 ˆ 2:5 ‡ 1:5 ˆ 4V The drain resistor is therefore

5 À VD2 5 À 4 RD ˆ ˆ ˆ 2:5k IDQ 0:4

Comment: Since VDS ˆ 2:5V> VGS À VTN ˆ 1:91 À 1:2 ˆ 0:71 V, each transistor is biased in the saturation region. 360 Part I Semiconductor Devices and Basic Applications

6.8.2 Small-Signal Analysis The midband small-signal voltage gain of multistage ampli®ers is determined by assumingthat all external couplingcapacitors act as short circuits and insertingthe small-signalequivalent circuits for the transistors.

Example 6.16 Objective: Determine the small-signal voltage gain of a multistage cascade circuit. Consider the circuit shown in Figure 6.49 with transistor and circuit parameters given in Example 6.14. Solution: The small-signal transconductance parameters are

gm1 ˆ 2Kn1 VGS1 À VTN1†ˆ2 0:50† 1:83 À 1:2†ˆ0:63 mA=V and

gm2 ˆ 2Kn2 VGS2 À VTN2†ˆ2 0:2† 2:78 À 1:2†ˆ0:632 mA=V The small-signal equivalent circuit is shown in Figure 6.51.

Ri

gm2Vgs2 RSi + – Vo + Vgs2 V + i – R1 R2 Vgs1 RD1 RS2 RL gm1Vgs1 –

Figure 6.51 Small-signal equivalent circuit of NMOS cascade circuit

The output voltage is

Vo ˆ gm2Vgs2 Rs2kRL† Also,

Vgs2 ‡ Vo ˆÀgm1Vgs1RD1 where  Ri Vgs1 ˆ Á Vi Ri ‡ RSi Then  Ri Vgs2 ˆÀgm1RD1 Á Vi À Vo Ri ‡ RSi Therefore  Ri Vo ˆ gm2 Àgm1RD1 Á Vi À Vo Rs2kRL† Ri ‡ RSi The small-signal voltage gain is then Chapter 6 Basic FET Amplifiers 361

 Vo Àgm1Gm2Rd1 Rs2kRL† Ri Av ˆ ˆ Á Vi 1 ‡ gm2 RS2kRL† Ri ‡ RSi or  À 0:63† 0:632† 16:1† 8k4† 100 A ˆ Á ˆÀ6:13 v 1 ‡ 0:632† 8k4† 100 ‡ 4

Comment: Since the small-signal voltage gain of the source-follower is slightly less than 1, the overall gain is due essentially to the common-source input stage. also, as shown previously, the output resistance of the source-follower is small, which is desir- able in many applications.

Example 6.17 Objective: Determine the small-signal voltage gain of a cascode circuit. For the circuit shown in Figure 6.50, the transistor and circuit parameters are as given in Example 6.15. The input signal to the circuit is an ideal voltage source. Solution: Since the transistors are identical, the small-signal transconductance para- meters of the two transistors are equal. Therefore,

gm1 ˆ gm2 ˆ 2Kn VGS À VTN †ˆ2 0:8† 1:91 À 1:2†ˆ1:14 mA=V

The small-signal equivalent circuit is shown in Figure 6.52. Transistor M1 supplies the source current of M2 with the signal current gm1Vi†. Transistor M2 acts as a current- follower and passes this current on to its drain terminal. The output voltage is therefore

Vo ˆÀgm1Vgs1RD

Since Vgs1 ˆ Vi, the small-signal voltage gain is

Vo Av ˆ ˆÀgm1RD Vi or

Av ˆÀ 1:14† 2:5†ˆÀ2:85

gm2Vgs2 = gm1Vgs1

Vo + + Vi – R3 R2 Vgs1 gm1Vgs1 RD

–

Figure 6.52 Small-signal equivalent circuit of NMOS cascode circuit

Comment: The small-signal voltage gain is essentially the same as that of a single common-source ampli®er stage. The addition of a common-gate transistor will increase the frequency bandwidth, as we will see in a later chapter. 362 Part I Semiconductor Devices and Basic Applications

Test Your Understanding

6.25 For the cascade circuit shown in Figure 6.49, the transistor and circuit para-

meters are given in Example 6.15. Calculate the small-signal output resistance Ro. (The small-signal equvialent circuit is shown in Figure 6.15.) (Ans. Ro ˆ 1:32 k ) *D6.26 The supply voltages to the cascade circuit shown in Figure 6.49 are changed ‡ À 2 to V ˆ 10 V and V ˆÀ10 V. The transistor parameters are: Kn1 ˆ Kn2 ˆ 1mA=V , À1 VTN1 ˆ VTN2 ˆ 2 V, and 1 ˆ 2 ˆ 0:01 V . (a) Let RL ˆ 4k , and design the circuit such that IDQ1 ˆ IDQ2 ˆ 2 mA, VDSQ1 ˆ VDSQ2 ˆ 10 V, and Ris ˆ 200 k . (b) Calculate the small-signal voltage gain and the output resistance Ro. (Ans. (a) RS2 ˆ 5k , RD1 ˆ 3:3k , RS1 ˆ 1:71 k , R1 ˆ 586 k , R2 ˆ 304 k ; (b) Av ˆÀ8:06, Ro ˆ 0:330 k ) D6.27 The supply voltages to the cascode circuit shown in Figure 6.50 are changed ‡ À 2 to V ˆ 10 V and V ˆÀ10 V. The transistor parameters are: Kn1 ˆ Kn2 ˆ 1:2mA=V , VTN1 ˆ VTN2 ˆ 2 V, and 1 ˆ 2 ˆ 0. (a) Let R1 ‡ R2 ‡ R3 ˆ 500 k , and Rs ˆ 10 k . Design the circuit such that IDQ ˆ 1 mA and VDSQ1 ˆ VDSQ2 ˆ 3:5 V. (b) Determine the small-signal voltage gain. (Ans. (a) R3 ˆ 145:5k , R2 ˆ 175 k , R1 ˆ 179:5k , RD ˆ 3k ; (b) Av ˆÀ6:57)

6.9 BASIC JFET AMPLIFIERS Like MOSFETs, JFETs can be used to amplify small time-varyingsignals. Initially, we will develop the small-signal model and equivalent circuit of the JFET. We will then use the model in the analysis of JFET ampli®ers.

6.9.1 Small-Signal Equivalent Circuit Figure 6.53 shows a JFET circuit with a time-varying signal applied to the gate. VDD The instantaneous gate-to-source voltage is

i v ˆ V ‡ v ˆ V ‡ v 6:53† D RD GS GS i GS gs where v is the small-signal gate-to-source voltage. Assuming the transistor is vO gs + biased in the saturation region, the instantaneous drain current is iG vDS 2 – vGS + iD ˆ IDSS 1 À 6:54† v V v + GS P i – – + where IDSS is the saturation current and VP is the pinchoff voltage. VGS SubstitutingEquation (6.53) into (6.54), we obtain –  V v 2 i ˆ I 1 À GS À gs 6:55† Figure 6.53 JFET common- D DSS VP VP source circuit with time- varying signal source in series If we expand the squared term, we have with gate dc source 2  VGS VGS vgs ÀÁ2 iD ˆ IDSS 1 À À2IDSS 1 À ‡ IDSS vgsP 6:56† VP VP VP

The ®rst term in Equation (6.56) is the dc or quiescent drain current IDQ, the second term is the time-varyingdrain current component, which is linearly Chapter 6 Basic FET Amplifiers 363

related to the signal votlage vgs, and the third term is proportional to the square of the signal voltage. As in the case of the MOSFET, the third term produces a nonlinear distortion in the output current. To minimize this distortion, we will usually impose the followingcondition:  v gs VGS  21À 6:57† VP VP Equation (6.57) represents the small-signal condition that must be satis®ed for JFET ampli®ers to be linear. 2 Neglecting the term vgs in Equation (6.56), we can write

iD ˆ IDQ ‡ id 6:58† where the time-varyingsignalcurrent is  2IDSS VGS id ˆ‡ 1 À vgs 6:59† ÀVP† VP The constant relating the small-signal drain current and small-signal gate-to- source voltage is the transconductance gm. We can write

id ˆ gmvgs 6:60† where  2IDSS VGS gm ˆ‡ 1 À 6:61† ÀVP† VP

Since VP is negative for n-channel JFETs, the transconductance is positive. A relationship that applies to both n-channel and p-channel JFETs is  2IDSS VGS gm ˆ 1 À 6:62† jVPj VP We can also obtain the transconductance from

@i g ˆ D 6:63† m @v GS vGS ˆVGSQ Since the transconductance is directly proportional to the saturation current IDSS, the transconductance is also a function of the width-to-length ratio of the transistor. Since we are lookinginto a reverse-biased pn junction, we assume that the input gate current ig is zero, which means that the small-signal input resistance is in®nite. Equation (6.54) can be expanded to take into account the ®nite output resistance of a JFET biased in the saturation region. The equation becomes

2 vGS iD ˆ IDSS 1 À 1 ‡ vDS† 6:64† VP The small-signal output resistance is  @i À1 r ˆ D 6:65† o @v DS vGS ˆconst: UsingEquation (6.64), we obtain 364 Part I Semiconductor Devices and Basic Applications

"# 2 À1 VGS ro ˆ IDSS 1 À 6:66 a†† VP

GDor + 1 r ‰I ŠÀ1 ˆ 6:66 b†† Vgs gmVgs ro o DQ IDQ – S The small-signal equivalent circuit of the n-channel JFET, shown in Figure 6.54, is exactly the same as that of the n-channel MOSFET. The small-signal Figure 6.54 Small-signal equivalent circuit of the p-channel JFET is also the same as that of the p- equivalent circuit of n-channel JFET channel MOSFET. However, the polarity of the controllinggate-to-source voltage and the direction of the dependent current source are reversed from those of the n-channel device.

6.9.2 Small-Signal Analysis Since the small-signal equivalent circuit of the JFET is the same as that of the MOSFET, the small-signal analyses of the two types of circuits are identical. For illustration purposes, we will analyze two JFET circuits.

Example 6.18 Objective: Determine the small-signal voltage gain of JFET ampli- ®er.

Consider the circuit shown in Figure 6.55 with transistor parameters IDSS ˆ 12 mA, À1 VP ˆÀ4 V, and  ˆ 0:008 V . Determine the small-signal voltage gain Av ˆ vo=vi.

VDD = 20 V

Ω RD = 2.7 k Ω R1 = 420 k vo C C2 Ω CC1 RL = 4 k

v + i R = 180 kΩ Ω – 2 RS = 2.7 k CS

Figure 6.55 Common-source JFET circuit with source resistor and source bypass capacitor

Solution: The dc quiescent gate-to-source voltage is determined from  R2 VGSQ ˆ VDD À IDQRS R1 ‡ R2

where Chapter 6 Basic FET Amplifiers 365

2 VGSQ IDQ ˆ IDSS 1 À VP

Combiningthese two equations produces   180 V 2 V ˆ 20†À 12† 2:7† 1 À GSQ GSQ 180 ‡ 420 À4† which reduces to

2 2:025VGSQ ‡ 17:2VGSQ ‡ 26:4 ˆ 0

The appropriate solution is

VGSQ ˆÀ2:01 V

The quiescent drain current is

2 2 VGSQ À2:01† IDQ ˆ IDSS 1 À ˆ 12† 1 À ˆ 2:97 mA VP À4†

The small-signal parameters are then   2IDSS VGS 2 12† À2:01† gm ˆ 1 À ˆ 1 À ˆ 2:98 mA=V ÀVP† VP 4† À4† and

1 1 ro ˆ ˆ ˆ 42:1k IDQ 0:008† 2:97†

The small-signal equivalent circuit is shown in Figure 6.56.

Vo +

V + g V R i – R1 R2 Vgs m gs ro RD L –

Figure 6.56 Small-signal equivalent circuit of common-source JFET, assuming bypass capacitor acts as a short circuit

Since Vgs ˆ Vi, the small-signal voltage gain is

Vo Av ˆ ˆÀgm rokRDkRL† Vi or

Av ˆÀ 2:98† 42:1k2:7k4†ˆÀ4:62

Comment: The voltage gain of JFET ampli®ers is the same order of magnitude as that of MOSFET ampli®ers. 366 Part I Semiconductor Devices and Basic Applications

Design Example 6.19 Objective: Design a JFET source-follower circuit with a speci®ed small-signal voltage gain. For the source-follower circuit shown in Figure 6.57, the transistor parameters are: À1 IDSS ˆ 12 mA, VP ˆÀ4 V, and  ˆ 0:01 V . Determine RS and IDQ such that the small-signal voltage gain is at least Av ˆ vo=vi ˆ 0:90.

+10 V

CC1 CC2 vo

v + Ω Ω i – RG = 50 k RS RL = 10 k

–10 V

Figure 6.57 JFET source-follower circuit

Solution: The small-signal equivalent circuit is shown in Figure 6.58. The output voltage is

Vo ˆ gmVgs RSkRLkro† Also

Vi ˆ Vgs ‡ Vo or

Vgs ˆ Vi À Vo Therefore, the output voltage is

Vo ˆ gm Vi À Vo† RSkRLkro† The small-signal voltage gain becomes

Vo gm RskRLkro† Av ˆ ˆ Vi 1 ‡ gm RskRLkro†

As a ®rst approximation, assume ro is suf®ciently large for the effect of ro to be neglected.

g V m gs ro

+ Vgs – Vo

V + i – RG RS RL

Figure 6.58 Small-signal equivalent circuit of JFET source-follower circuit Chapter 6 Basic FET Amplifiers 367

The transconductance is   2IDSS VGS 2 12† VGS gm ˆ 1 À ˆ 1 À ÀVP† VP 4 À4†

If we pick a nominal transconductance value of gm ˆ 2 mA/V, then VGS ˆÀ2:67 V and the quiescent drain current is

2 2 VGS À2:67† IDQ ˆ IDSS 1 À ˆ 12† 1 À ˆ 1:33 mA VP À4†

The value of RS is then determined from

ÀVGS À À10† 2:67 ‡ 10 RS ˆ ˆ ˆ 9:53 k IDQ 1:33

Also, the value of ro is

1 1 ro ˆ ˆ ˆ 75:2k IDQ 0:01† 1:33†

The small-signal voltage gain, including the effect of ro,is

gm RSkRLkro† 2† 9:53k10k75:2† Av ˆ ˆ ˆ 0:902 1 ‡ gm RskRLkro† 1 ‡ 2† 9:53k10k75:2†

Comment: This particular design meets the design criteria, but the solution is not unique.

In the last example, we chose a value of transconductance and continued through the design. A more detailed examination shows that both gm and RS depend upon the drain current IDQ in such a way that the product gmRS is approximately a constant. This means the small-signal voltage gain is insensi- tive to the initial value of the transconductance.

Test Your Understanding

6.28 Reconsider the JFET ampli®er shown in Figure 6.55 with transistor parameters given in Example 6.19. Determine the small-signal voltage gain if a 20 k resistor is in series with the signal source vi. (Ans. Av ˆÀ3:98† RD6.29 For the JFET ampli®er shown in Figure 6.55, the transistor parameters are: À1 IDSS ˆ 4 mA, VP ˆÀ3 V, and  ˆ 0:005 V . Let RL ˆ 4k , RS ˆ 2:7k , and R1 ‡ R2 ˆ 500 k . Redesign the circuit such that IDQ ˆ 1:2 mA and VDSQ ˆ 12 V. Calculate the small-signal voltage gain. (Ans. RD ˆ 3:97 k , R1 ˆ 453 k , R2 ˆ 47 k , Av ˆÀ2:87) *6.30 For the circuit shown in Figure 6.59, the transistor parameters are:

IDSS ˆ 6 mA, jVPjˆ2 V, and  ˆ 0. (a) Calculate the quiescent drain current and 368 Part I Semiconductor Devices and Basic Applications

VDD = 20 V

Ω Ω RS1 = 4 k R1 = 70 k CC1

CS Q1 Q2 CC2 + vi Ω vo – R2 = 430 k Ω RD1 = 4 k Ω Ω RS2 = 4 k RL = 2 k

Figure 6.59 Figure for Exercise 6.30

drain-to-source voltage of each transistor. (b) Determine the overall small-signal voltage

gain Av ˆ vo=vi. (Ans. (a) IDQ1 ˆ 1 mA, VSDQ1 ˆ 12 V, IDQ2 ˆ 1:27 mA, VDSQ2 ˆ 14:9V; (b) Av ˆÀ2:05) 6.31 Reconsider the source-follower circuit shown in Figure 6.57 with transistor À1 parameters IDSS ˆ 8 mA, VP ˆÀ3:5 V, and  ˆ 0:01 V . (a) Design the circuit such that IDQ ˆ 2 mA. (b) Calculate the small-signal voltage gain if RL approaches in®nity. (c) Determine the value of RL at which the small-signal gain is reduced by 20 percent from its value for (b). (Ans. (a) RS ˆ 5:88 k , (b) Av ˆ 0:923, RL ˆ 1:64 k )

6.10 SUMMARY

* The application of MOSFET transistors in linear ampli®er circuits was emphasized in this chapter. A small-signal equivalent circuit for the transistor was developed, which is used in the analysis and design of linear ampli®ers. * Three basic circuit con®gurations were considered: the common source, source fol- lower, and common gate. These three con®gurations form the basic building blocks for complex integrated circuits. The small-signal voltage gains and output resistances for these circuits were analyzed. The circuit characteristics of the three circuits were compared in Table 6.1. * The ac analysis of circuits with enhancement load devices, with depletion load devices, and complementary (CMOS) devices were analyzed. These circuits are examples of all MOSFET circuits and act as an introduction to more complex all MOSFET integrated circuits considered later in the text. * The small-signal equivalent circuit of a JFET was developed and used in the analysis of several con®gurations of JFET ampli®ers.

CHECKPOINT

After studyingthis chapter, the reader should have the ability to: \ Explain graphically the ampli®cation process in a simple MOSFET ampli®er circuit. (Section 6.1) \ Describe the small-signal equivalent circuit of the MOSFET and to determine the values of the small-signal parameters. (Section 6.1) Chapter 6 Basic FET Amplifiers 369

\ Apply the small-signal equivalent circuit to various MOSFET ampli®er circuits to obtain the time-varyingcircuit characteristics. \ Characterize the small-signal voltage gain and output resistance of a common-source ampli®er. (Section 6.3) \ Characterize the small-signal voltage gain and output resistance of a source-follower ampli®er. (Section 6.4) \ Characterize the small-signal voltage gain and output resistance of a common-gate ampli®er. (Section 6.5) \ Describe the operation of an NMOS ampli®er with either an enhancement load, a depletion load, or a PMOS load. (Section 6.7) \ Apply the MOSFET small-signal equivalent circuit in the analysis of multistage ampli®er circuits. (Section 6.8) \ Describe the operation and analyze basic JFET ampli®er circuits. (Section 6.9)

REVIEW QUESTIONS

1. Discuss, usingthe concept of a load line superimposed on the transistor character- istics, how a simple common-source circuit can amplify a time-varyingsignal. 2. How does a transistor width-to-length ratio affect the small-signal voltage gain of a common-source ampli®er?

3. Discuss the physical meaningof the small-signalcircuit parameter ro. 4. How does the body effect change the small-signal equivalent circuit of the MOSFET? 5. Sketch a simple common-source ampli®er circuit and discuss the general ac circuit characteristics (voltage gain and output resistance). 6. Discuss the general conditions under which a common-source ampli®er would be used. 7. Why, in general, is the magnitude of the voltage gain of a common-source ampli- ®er smaller than that of a bipolar common-emitter ampli®er? 8. What are the changes in the ac characteristics of a common-source ampli®er when a source resistor and a source bypass capacitor are incorporated in the design? 9. Sketch a simple source-follower ampli®er circuit and discuss the general ac circuit characteristics (voltage gain and output resistance). 10. Discuss the general conditions under which a source-follower ampli®er would be used. 11. Sketch a simple common-gate ampli®er circuit and discuss the general ac circuit characteristics (voltage gain and output resistance). 12. Discuss the general conditions under which a common-gate ampli®er would be used. 13. Compare the ac circuit characteristics of the common-source, source-follower, and common-gate circuits. 14. State the general advantage of using transistors in place of resistors in integrated circuits. 15. State at least two reasons why a multistage ampli®er circuit would be required in a design compared to using a single-stage circuit. 16. Give one reason why a JFET might be used as an input device in a circuit as opposed to a MOSFET. 370 Part I Semiconductor Devices and Basic Applications

PROBLEMS

Section 6.1 The MOSFET Amplifier

0 2 6.1 An NMOS transistor has parameters VTN ˆ 0:8V, kn ˆ 40 mA=V , and  ˆ 0. (a) Determine the width-to-length ratio W=L† such that gm ˆ 0:5 mA/V at ID ˆ 0:5mA when biased in the saturation region. (b) Calculate the required value of VGS. 0 6.2 A PMOS transistor has parameters VTP ˆÀ1:2V, kp ˆ 20 mA=V, and  ˆ 0. (a) Determine the width-to-length ratio W=L† such that gm ˆ 50 mA=VatID ˆ 0:1mA when biased in the saturation region. (b) Calculate the required value of VSG.

6.3 An NMOS transistor is biased in the saturation region at a constant VGS. The drain current is ID ˆ 3mAat VDS ˆ 5 V and ID ˆ 34 mA at VDS ˆ 10 V. Determine  and ro. 6.4 The minimum value of small-signal resistance of a PMOS transistor is to be À1 ro ˆ 100 k .If ˆ 0:012 V , calculate the maximum allowed value of ID. 6.5 Calculate the small-signal voltage gain of the circuit shown in Figure 6.1, for

gm ˆ 1 mA/V, ro ˆ 50 k , and RD ˆ 10 k . *D6.6 For the circuit shown in Figure 6.1, the transistor parameters are: À1 0 2 VTN ˆ‡0:8V, ˆ 0:015 V , and kn ˆ 60 mA=V . Let VDD ˆ 10 V. (a) Design the tran- sistor width-to-length ratio W=L† and the resistance RD such that IDQ ˆ 0:5 mA and VDSQ ˆ 6 V. (b) Calculate gm and ro. (c) What is the small-signal voltage gain Av ˆ vo=vi? *6.7 In our analyses, we assumed the small-signal condition given by Equation (6.4).

Now consider Equation (6.3b) and let vgs ˆ Vgs sin !t. Show that the ratio of the signal at frequency 2! to the signal at frequency ! is given by Vgs=‰4 VGS À VTN †Š. This ratio, expressed in a percentage, is called the second-harmonic distortion. [Hint: Use the trigo- 2 1 1 nometric identity sin  ˆ 2 À 2 cos 2.]

6.8 Usingthe results of Problem 6.7, ®nd the peak amplitude Vgs that produces a second-harmonic distortion of 1 percent if VGS ˆ 3 V and VTh ˆ 1V.

Section 6.3 Common-Source Amplifier 6.9 Calculate the small-signal voltage gain of a common-source ampli®er, such as that

shown in Figure 6.13, assuming gm ˆ 1 mA/V, ro ˆ 50 k , and RD ˆ 10 k . Also assume RSi ˆ 2k and R1kR2 ˆ 50 k . 6.10 A common-source ampli®er, such as shown in Figure 6.13 in the text, has para-

meters ro ˆ 100 k and RD ˆ 5k . Determine the transconductance of the transistor if the small-signal voltage gain is Av ˆÀ10. Assume RSi ˆ 0. 6.11 For the NMOS common-source ampli®er in Figure P6.11, the transistor para- 2 meters are: VTN ˆ 2V, Kn ˆ 1mA=V , and  ˆ 0. The circuit parameters are: VDD ˆ 12 V, RS ˆ 2k , RD ˆ 3k, R1 ˆ 300 k , and R2 ˆ 200 k . Assume RSi ˆ 2k and assume a load resistance RL ˆ 3k is capacitively coupled to the output. (a) Determine the quiescent values of ID and VDS. (b) Find the small-signal voltage gain. (c) Determine the maximum symmetrical swing in the output voltage.

6.12 In the circuit in Figure P6.11, VDD ˆ 15 V, RD ˆ 2k , RL ˆ 5k , RS ˆ 0:5k , and Rin ˆ 200 k . (a) Find R1 and R2 such that IDQ ˆ 3 mA for VTN ˆ 2V, 2 Kn ˆ 2mA=V , and  ˆ 0. (b) Determine the small-signal voltage gain.

6.13 Repeat Problem 6.11 if the source resistor is bypassed by a source capacitor CS. Chapter 6 Basic FET Amplifiers 371

VDD

RD Rin R1 CC2 vo CC1

RL vi + – R2 RS

Figure P6.11

*6.14 The transistor in the common-source ampli®er in Figure P6.14 has parameters 2 À1 ‡ VTN ˆ 1V, Kn ˆ 0:5mA=V , and  ˆ 0:01 V . The circuit parameters are: V ˆ 5V, À V ˆÀ5 V, and RD ˆ RL ˆ 10 k . (a) Determine IDQ to achieve the maximum sym- metrical swing in the output voltage. (b) Find the small-signal voltage gain. D6.15 For the common-source ampli®er in Figure P6.15, the transistor parameters 2 are: VTN ˆÀ1V, Kn ˆ 4mA=V , and  ˆ 0. The circuit parameters are VDD ˆ 10 V and RL ˆ 2k . (a) Design the circuit such that IDQ ˆ 2 mA and VDSQ ˆ 6 V. (b) Determine the small-signal voltage gain. (c) If vi ˆ Vi sin !t, determine the maximum value of Vi such that vo is an undistorted sine wave.

V +

VDD RD

CC2 v o RD CC1 CC2 RL vo C + R = C1 vi G – 200 kΩ RL + vi R = 1 MΩ IQ CS – G RS

V – Figure P6.14 Figure P6.15

*6.16 The transistor in the common-source circuit in Figure P6.15 has the same para- meters as given in Problem 6.15. The circuit parameters are VDD ˆ 5 V and RD ˆ RL ˆ 2k . (a) Find RS and VDSQ ˆ 2:5 V. (b) Determine the small-signal voltage gain. *6.17 Consider the PMOS common-source circuit in Figure P6.17 with transistor parameters VTP ˆÀ2 V and  ˆ 0, and circuit parameters RD ˆ RL ˆ 10 k . (a) Determine the values of Kp and RS such that VSDQ ˆ 6 V. (b) Determine the resulting value of IDQ and the small-signal voltage gain. (c) Can the values of Kp and RS from 372 Part I Semiconductor Devices and Basic Applications

+5 V

RS

C CC1 S

CC2 v + R = o vi G – 100 kΩ RD RL

–5 V Figure P6.17

part (a) be changed to achieve a larger voltage gain, while still meeting the requirements of part (a)? D6.18 For the common-source circuit in Figure P6.17, the PMOS transistor para- 2 meters are: VTP ˆÀ1:5V, Kp ˆ 5mA=V , and  ˆ 0. The load resistor is RL ˆ 2k . (a) Design the circuit such that IDQ ˆ 1 mA and VSDQ ˆ 5 V. (b) Determine the small- signal voltage gain Av ˆ vo=vi. (c) What is the maximum symmetrical swingin the output voltage? *D6.19 Design the common-source circuit in Figure P6.19 using an n-channel

MOSFET with  ˆ 0. The quiescent values are to be IDQ ˆ 6 mA, VGSQ ˆ 2:8 V, and VDSQ ˆ 10 V. The transconductance is gm ˆ 2:2 mA/V. Let RL ˆ 1k , Av ˆÀ1, and Rin ˆ 100 k . Find R1; R2; RS; RD; Kn, and VTN . *6.20 For the common-source ampli®er in Figure P6.20, the transistor parameters 2 À1 are: VTP ˆÀ1:5V, Kp ˆ 2mA=V , and  ˆ 0:01 V . The circuit is to drive a load resistance of RL ˆ 20 k . To minimize loadingeffects, the drain resistance should be RD  0:1RL. (a) Determine IQ such that the Q-point is in the center of the saturation region. (b) Determine the open-circuit RL ˆ1† small-signal voltage gain. (c) By what percentage does the small-signal voltage gain decrease when RL is connected?

+9 V VDD = 18 V

IQ

RD Rin R1 C C vo C1 S CC1 CC2 CC2 v + o vi R = 500 kΩ RL – G vi + – R2 RS RD RL

–9 V Figure P6.19 Figure P6.20 Chapter 6 Basic FET Amplifiers 373

D6.21 For the circuit shown in Figure P6.21, the transistor parameters are: VTP ˆ 2V, 2 Kp ˆ 0:5mA=V , and  ˆ 0. (a) Design the circuit such that IDQ ˆ 2 mA and VSDQ ˆ 6 V. (b) Determine the small-signal voltage gain Av ˆ vo=vi. *D6.22 Design a common-source ampli®er, such as that in Figure P6.22, to achieve a small-signal voltage gain of at least Av ˆ vo=vi ˆÀ10 for RL ˆ 20 k and Rin ˆ 200 k . Assume the Q-point is chosen at IDQ ˆ 1 mA and VDSQ ˆ 10 V. Let VTN ˆ 2 V, and  ˆ 0.

VDD = 20 V +10 V

R S RD Rin R1 vo CC1 CC CS CC2

v R + o L v Ω vi + i – RG = 200 k – R2 CS RS RD

–10 V Figure P6.21 Figure P6.22

Section 6.4 Source-Follower Amplifier

6.23 For an enhancement-mode MOSFET source-follower, gm ˆ 4mA=V and ro ˆ 50 k . Determine the no-load voltage gain and the output resistance. Calculate the small-signal voltage gain when a load resistance RS ˆ 2:5k is connected. 6.24 The transistor in the source-follower circuit in Figure P6.24 has parameters 2 À1 Kp ˆ 2mA=V , VTP ˆÀ2 V, and  ˆ 0:02 V . The circuit parameters are: RL ˆ 4k , RS ˆ 4k , R1 ˆ 1:24 M , and R2 ˆ 396 k . (a) Calculate IDQ and VSDQ. (b) Determine the small-signal gains Av ˆ vo=vi and Ai ˆ io=ii, and the output resistance Ro.

VDD = 10 V

R S Ro R1 vo CC1 CC2

i ii o RL v + i – R2

Figure P6.24 374 Part I Semiconductor Devices and Basic Applications

6.25 Consider the source-follower circuit in Figure P6.25 with transistor parameters 2 À1 VTN ˆ 1:2V, Kn ˆ 1mA=V , and  ˆ 0:01 V .IfIQ ˆ 1 mA, determine the small- signal voltage gain Av ˆ vo=vi and the output resistance Ro.

+5 V

CC1

Ro CC2 + R = v vi G o – 500 kΩ R = I L Q 4 kΩ

–5 V Figure P6.25

6.26 For the source-follower circuit shown in Figure P6.25, the transistor parameters 0 2 are: VTN ˆ 1V, kn ˆ 60 mA=V , and  ˆ 0. The small-signal voltage gain is to be Av ˆ vo=vi ˆ 0:95. (a) Determine the required width-to-length ratio W=L† for IQ ˆ 4 mA. (b) Determine the required IQ if W=L†ˆ60. *D6.27 In the source-follower circuit in Figure P6.27 with a depletion NMOS transis- 2 À1 tor, the device parameters are: VTN ˆÀ2V, Kn ˆ 5mA=V , and  ˆ 0:01 V . Design the circuit such that IDQ ˆ 5 mA. Find the small-signal voltage gain Av ˆ vo=vi and the output resistance Ro.

+5 V

CC1

Ro CC2 R = v + G vo i – 200 kΩ R = R L S 2 kΩ

–5 V Figure P6.27

6.28 Consider the circuit in Figure P6.27. Let RS ˆ 10 k and  ˆ 0. The open-circuit voltage gain RL ˆ1†is Av ˆ vo=vi ˆ 0:90. Determine gm and Ro. Determine the value of the voltage gain if a load resistor RL ˆ 2k is connected. D6.29 For the source-follower circuit in Figure P6.27, the transistor parameters are: 2 VTN ˆÀ2V, Kn ˆ 4mA=V , and  ˆ 0. Design the circuit such that Ro  200 . Determine the resulting small-signal voltage gain.

6.30 The current source in the source-follower circuit in Figure P6.30 is IQ ˆ 5mA 2 and the transistor parameters are: VTP ˆÀ2V, Kp ˆ 5mA=V , and  ˆ 0. (a) Determine the output resistance Ro. (b) Determine the value of RL that reduces the small-signal voltage gain to one-half the open-circuit RL ˆ1†value. Chapter 6 Basic FET Amplifiers 375

V + = 5 V

IQ Ro vo CC1 CC2

RL v + R = i – G 200 kΩ

V – = –5 V Figure P6.30

6.31 Consider the source-follower circuit shown in Figure P6.31. The most negative output signal voltage occurs when the transistor just cuts off. Show that this output voltage vo min† is given by

ÀI R v min†ˆ DQ S o R 1 ‡ S RL Show that the corresponding input voltage is given by

IDQ vi min†ˆÀ 1 ‡ gm RSkRL†† gm

D6.32 The transistor in the circuit in Figure P6.32 has parameters VTN ˆ 1V, 2 Kn ˆ 1mA=V , and  ˆ 0. The circuit parameters are VDD ˆ 5 V and Ri ˆ 300 k . (a) Design the circuit such that IDQ ˆ 1:7 mA and VDSQ ˆ 3 V. (b) Determine the small-signal voltage gain Av ˆ vo=vi and the output resistance Ro.

VDD

VDD Ri R1 CC1 CC1 R CC2 o + v vi o vO – RG vi + – R2 RS RS RL

Figure P6.31 Figure P6.32

Section 6.5 Common-Gate Configuration 6.33 For the common-gate circuit in Figure P6.33, the NMOS transistor parameters 2 are: VTN ˆ 1V, Kn ˆ 3mA=V , and  ˆ 0. (a) Determine IDQ and VDSQ. (b) Calculate gm and ro. (c) Find the small-signal voltage gain Av ˆ vo=vi. 6.34 Consider the PMOS common-gate circuit in Figure P6.34. The transistor para- 2 meters are: VTP ˆÀ1V, Kp ˆ 0:5mA=V , and  ˆ 0. (a) Determine RS and RD such that IDQ ˆ 0:75 mA and VSDQ ˆ 6 V. (b) Determine the input impedance Ri and the 376 Part I Semiconductor Devices and Basic Applications

Ro Ri CC1 CC2 vo

CC1 CC2 R = v i R = o 100 kΩ R R i L S D o 2 kΩ RG = v + Ω Ω Ω Ω CG i – RS = 10 k RD = 5 k RL = 4 k 50 k V + = +5 V V – = –5 V

V – = –5 V V + = +5 V Figure P6.33 Figure P6.34

output impedance Ro. (c) Determine the load current io and the output voltage vo,if ii ˆ 5 sin !t mA. 6.35 The parameters of the transistor in the circuit in Figure 6.34 in the text are: 2 ‡ VTN ˆ 2V, Kn ˆ 4mA=V , and  ˆ 0. The circuit parameters are: V ˆ 10 V, À V ˆÀ10 V, RG ˆ 100 k , RL ˆ 2k , and IQ ˆ 5 mA. (a) Find RD such that VDSQ ˆ 12 V. (b) Calculate gm and Ri. (c) Determine the small-signal voltage gain Av ˆ vo=vi. 6.36 For the common-gate ampli®er in Figure 6.37 in the text, the PMOS transistor 2 parameters are: VTP ˆÀ2V, Kp ˆ 2mA=V , and  ˆ 0. The circuit parameters are: ‡ À V ˆ 10 V, V ˆÀ10 V, RG ˆ 200 k , and RL ˆ 10 k . (a) Determine RS and RD such that IDQ ˆ 3 mA and VSDQ ˆ 10 V. (b) Determine the small-signal voltage gain Av ˆ vo=vi.

Section 6.7 Amplifiers with MOSFET LoadDevices D6.37 Consider the NMOS ampli®er with saturated load in Figure 6.39(a). The tran- 0 2 sistor parameters are: VTND ˆ VTNL ˆ 2V, kn ˆ 60 mA=V ,  ˆ 0, and W=L†L ˆ 0:5. Let VDD ˆ 10 V. (a) Design the circuit such that the small-signal voltage gain is jAvjˆ5 and the Q-point is in the center of the saturation region. (b) Determine IDQ and the dc value of vo. *6.38 For the NMOS ampli®er with depletion load in Figure 6.43(a), the transistor 2 2 parameters are: VTND ˆ 1:2V,VTNL ˆÀ2V,KnD ˆ 0:5mA=V , KnL ˆ 0:1mA=V , and À1 D ˆ L ˆ 0:02 V . Let VDD ˆ 10 V. (a) Determine VGS such that the Q-point is in the middle of the saturation region. (b) Calculate IDQ and the dc value of vo. (c) Determine the small-signal voltage gain. VDD = 10 V 6.39 Consider a saturated load device in which the gate and drain of an enhancement mode MOSFET are connected together. The transistor drain current becomes zero

when VDS ˆ 1:5 V. When VDS ˆ 3 V, the drain current is 0.8 mA. Determine the small-signal resistance at this operating point. ML

6.40 The parameters of the transistors in the circuit in Figure P6.40 are VTND ˆÀ1V, vO 2 2 KnD ˆ 0:5mA=V for transistor MD, and VTNL ˆ‡1V, KnL ˆ 30 mA=V for transistor ML. Assume  ˆ 0 for both transistors. (a) Calculate the quiescent drain current IDQ M D and the dc value of the output voltage. (b) Determine the small-signal voltage gain Av ˆ v + vo=vi about the Q-point. i – 6.41 A source-follower circuit with a saturated load is shown in Figure P6.41. The 2 transistor parameters are VTND ˆ 1V,KnD ˆ 1mA=V for MD, and VTNL ˆ 1V,KnL ˆ 2 Figure P6.40 0:1mA=V for ML. Assume  ˆ 0 for both transistors. Let VDD ˆ 9 V. (a) Determine Chapter 6 Basic FET Amplifiers 377

VDD

MD Ro v + CC i – vo + + VGG R – ML vDSL L –

Figure P6.41

VGG such that the quiescent value of vDSL is 4 V. (b) Show that the small-signalp open- circuit RL ˆ1†voltage gain about this Q-point is given by Av ˆ 1=‰1 ‡ KnL=KnD Š. (c) Calculate the small-signal voltage gain for RL ˆ 4k . 6.42 For the source-follower circuit with a saturated load, as shown in Figure P6.41, assume the same transistor parameters as given in Problem 6.41. (a) Determine the small- signal voltage gain if RL ˆ 10 k . (b) Determine the small-signal output resistance Ro.

Section 6.8 Multistage Amplifiers

2 *D6.43 The transistor parameters in the circuit in Figure P6.43 are: Kn1 ˆ 0:1mA=V , 2 Kp2 ˆ 1:0mA=V , VTN1 ˆ‡2V,VTD2 ˆÀ2 V, and 1 ˆ 2 ˆ 0. The circuit parameters are: VDD ˆ 10 V, RS1 ˆ 4k , and Rin ˆ 200 k . (a) Design the circuit such that IDQ1 ˆ 0:4 mA, IDQ2 ˆ 2 mA, VDSQ1 ˆ 4 V, and VSDQ2 ˆ 5 V. (b) Calculate the small- signal voltage gain Av ˆ vo=vi. (c) Determine the maximum symmetrical swingin the output voltage.

VDD

R RD1 S2 R1 Rin

CS2 M1 M2 CC vO + vi R – 2 C RS1 S1 RD2

Figure P6.43

D6.44 The transistor parameters in the circuit in Figure P6.43 are the same as those given in Problem 6.43. The circuit parameters are: VDD ˆ 10 V, RS1 ˆ 1k , Rin ˆ 200 k , RD2 ˆ 2k , and RS2 ˆ 0:5k . (a) Design the circuit such that the Q-point of M2 is in the center of the saturation region and IDQ1 ˆ 0:4 mA. (b) Determine the resultingvalues of IDQ2; VSDQ2; and VDSQ1. (c) Determine the resulting small-signal voltage gain. 378 Part I Semiconductor Devices and Basic Applications

D6.45 Consider the circuit in Figure P6.45 with transistor parameters Kn1 ˆ 2 Kn2 ˆ 200 mA=V , VTN1 ˆ VTN2 ˆ 0:8 V, and 1 ˆ 2 ˆ 0. (a) Design the circuit such that VDSQ2 ˆ 7 V and Rin ˆ 400 k . (b) Determine the resultingvalues of IDQ1, IDQ2, and VDSQ1. (c) Calculate the resulting small-signal voltage gain Av ˆ vo=vi and the output resistance Ro.

6.46 For the circuit in Figure P6.46, the transistor parameters are: Kn1 ˆ 2 Kn2 ˆ 4mA=V , VTN1 ˆ VTN2 ˆ 2 V, and 1 ˆ 2 ˆ 0. (a) Determine IDQ1, IDQ2, VDSQ1, and VDSQ2. (b) Determine gm1 and gm2. (c) Determine the overall small-signal voltage gain Av ˆ vo=vi.

VDD = 10 V

+10 V Rin R1 C C CC1 M M Ro 1 2 M1 CC2 CC3 vO v + RG = vo i – M2 vi + 400 kΩ – R2 R = R = S1 S2 R = R = R = R = 20 kΩ 6 kΩ S1 S2 D L 10 kΩ 10 kΩ 5 kΩ 2 kΩ

–10 V –10 V +10 V Figure P6.45 Figure P6.46

D6.47 For the cascode circuit in Figure 6.50 in the text, the transistor parameters are: 2 VTN1 ˆ VTN2 ˆ 1V, Kn1 ˆ Kn2 ˆ 2mA=V , and 1 ˆ 2 ˆ 0. (a) Let RS ˆ 1:2k and R1 ‡ R2 ‡ R3 ˆ 500 k . Design the circuit such that IDQ ˆ 3 mA and VDSQ1 ˆ VDSQ2 ˆ 2:5 V. (b) Determine the small-signal voltage gain Av ˆ vo=vi. D6.48 The supply voltages to the cascode circuit in Figure 6.50 in the text are changed to V‡ ˆ 10 V and VÀ ˆÀ10 V. The transistor parameters are: 2 Kn1 ˆ Kn2 ˆ 4mA=V , VTN1 ˆ VTN2 ˆ 1:5 V, and 1 ˆ 2 ˆ 0. (a) Let RS ˆ 2k , and assume the current in the bias resistors is 0.1 mA. Design the circuit such that

IDQ ˆ 5 mA and VDSQ1 ˆ VDSQ2 ˆ 3:5 V. (b) Determine the resultingsmall-signalvol- tage gain.

Section 6.9 Basic JFET Amplifiers 6.49 Consider the JFET ampli®er in Figure 6.53 with transistor parameters À1 IDSS ˆ 6 mA, VP ˆÀ3 V, and  ˆ 0:01 V . Let VDD ˆ 10 V. (a) Determine RD and VGS such that IDQ ˆ 4 mA and VDSQ ˆ 6 V. (b) Determine gm and ro at the Q-point. (c) Determine the small-signal voltage gain Av ˆ vo=vi where vo is the time-varying portion of the output voltage vO. 6.50 For the JFET ampli®er in Figure P6.50, the transistor parameters are:

IDSS ˆ 2 mA, VP ˆÀ2 V, and  ˆ 0. Determine gm, Av ˆ vo=vi, and Ai ˆ io=ii. D6.51 The parameters of the transistor in the JFET common-source ampli®er shown

in Figure P6.51 are: IDSS ˆ 8 mA, VP ˆÀ4:2 V, and  ˆ 0. Let VDD ˆ 20 V and RL ˆ 16 k . Design the circuit such that VS ˆ 2V, R1 ‡ R2 ˆ 100 k , and the Q- point is at IDQ ˆ IDSS=2 and VDSQ ˆ VDD=2. Chapter 6 Basic FET Amplifiers 379

VDD

VDD Ω RD = 8 k

vo

CC2 R CC D R1 Rin vo i R = C i S1 R = C C2 100 Ω L i C1 4 kΩ o + R = vi G – Ω io RL 50 k ii R = + R R S2 C vi 2 S 250 Ω S –

Figure P6.50 Figure P6.51

*D6.52 Consider the source-follower JFET ampli®er in Figure P6.52 with transistor À1 parameters IDSS ˆ 10 mA, VP ˆÀ5 V, and  ˆ 0:01 V . Let VDD ˆ 12 V and RL ˆ 0:5k . (a) Design the circuit such that Rin ˆ 100 k , and the Q-point is at IDQ ˆ IDSS=2 and VDSQ ˆ VDD=2: (b) Determine the resulting small-signal voltage gain Av ˆ vo=vI and the output resistance Ro. 6.53 For the p-channel JFET source-follower circuit in Figure P6.53, the transistor parameters are: IDSS ˆ 2 mA, VP ˆ‡1:75 V, and  ˆ 0. (a) Determine IDQ and VSDQ. (b) Determine the small-signal gains Av ˆ vo=vi and Ai ˆ io=ii. (c) Determine the max- imum symmetrical swingin the output voltage. D6.54 The p-channel JFET common-source ampli®er in Figure P6.54 has transistor parameters IDSS ˆ 8 mA, VP ˆ 4 V, and  ˆ 0. Design the circuit such that IDQ ˆ 4 mA, VSDQ ˆ 7:5V, Av ˆ vo=vi ˆÀ3, and R1 ‡ R2 ˆ 400 k .

VDD VDD = 10 V

Rin Ω R Ω RS = 5 k 1 R1 = 90 k R CC1 o CC1 vo vo CC2 i i CC2 ii RL = v + io i R2 R 10 kΩ – S RL v + Ω io i – R2 = 110 k

Figure P6.52 Figure P6.53 380 Part I Semiconductor Devices and Basic Applications

VDD = 20 V

R1 RS CC1

v v + O i – R2

RD

Figure P6.54

COMPUTER SIMULATION PROBLEMS

6.55 Consider the circuit in Figure 6.22 with transistor parameters given in Example 6.6. Using a computer analysis, investigate the effect of the channel-length modulation parameter  and the body-effect parameter on the small-signal voltage gain. 6.56 Usinga computer analysis, investigatethe effect of the transistor parameters  and on the small-signal voltage gain and output resistance of the source-follower circuit in Figure 6.28. The circuit and transistor parameters are given in Example 6.7. 6.57 For the common-gate circuit in Figure 6.34 the circuit and transistor parameters are as given in Example 6.10. Using a computer analysis, determine the small-signal

voltage gain, current gain, input resistance Ri, and output resistance (lookinginto the drain of the transistor). As part of the analysis, investigate the effect of the transistor parameters  and on the circuit characteristics. 6.58 Perform a computer analysis of Exercise 6.22, includingthe body effect. Determine the change in the small-signal voltage gain when the body effect is included. If the dc output voltage is approximately 2.5 V, determine the required change in the dc bias on the driver transistor when the body effect is included. 6.59 Repeat Problem 6.58 for Exercise 6.24.

DESIGN PROBLEMS

[Note: Each design should be correlated with a computer analysis.] *D6.60 A discrete common-source circuit with the con®guration shown in Figure 6.16 is to be designed to provide a voltage gain of 20 and a symmetrical output voltage swing.

The power supply voltage is VDD ˆ 5 V, the output resistance of the signal source is 0 2 À1 1k , and the transistor parameters are: VTN ˆ 0:8V,kn ˆ 40 mA=V , and  ˆ 0:01 V . Plot W=L and RD versus quiescent drain current. Determine W=L and RD for IDQ ˆ 0:1mA: *D6.61 For a common-gate ampli®er in Figure 6.37 the available power supplies are Æ10 V, the output resistance of the signal source is 200 , and the input resistance of the 0 2 ampli®er is to be 200 . The transistor parameters are: kp ˆ 30 mA=V , VTP ˆÀ2V, and  ˆ 0. The output load resistance is RL ˆ 5k . Design the circuit such that the output voltage has a peak-to-peak symmetrical swing of at least 5 V. Chapter 6 Basic FET Amplifiers 381

*D6.62 A source-follower ampli®er with the general con®guration shown in Figure 6.32 is to be designed. The available power supplies are Æ12 V, and the transistor 0 2 parameters are: VTN ˆ 1:5V, kn ˆ 40 mA=V , and  ˆ 0. The load resistance is RL ˆ 100 . Design the circuit such that 200 mW of signal power is delivered to the load. As part of the design, a constant-current source circuit is also to be designed. *D6.63 For an NMOS ampli®er with a depletion load, such as shown in Figure 6.43(a), the available power supplies are Æ5 V, and the transistor parameters are: 0 2 À1 1=2 VTN MD†ˆ‡1V, VTN ML†ˆÀ2V, kn ˆ 40 mA=V ,  ˆ 0:01 V , and ˆ 0:35 V . Design the circuit such that the small-signal voltage gain is at least jAvjˆ200 when the output is an open circuit. Use a constant-current source to establish the quiescent Q- point, and couple the signal source vi directly to the gate of MD. *D6.64 For the cascode circuit shown in Figure 6.50, the transistor parameters are: 0 2 VTN ˆ 1V,kn ˆ 40 mA=V , and  ˆ 0. Design the circuit such that the minimum open- circuit voltage gain is 10. Determine the maximum symmetrical swing in the output voltage.