Investigating CMOS Amplifier Design

Investigating CMOS Ampliﬁer Design Using the Degrees of Design Freedom Method

Euisoo Yoo

Department of Electrical and Computer Engineering

McGill University Montr´eal, Qu´ebec

May 2009

A thesis submitted to McGill University in partial fulﬁlment of the requirements of the degree of Master of Engineering

c Euisoo Yoo, 2009

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ACKNOWLEDGEMENTS

I’d like to start by thanking my supervisor, Professor Gordon Roberts, for the opportunity to conduct my research and design with him and the group in the MACS lab. With his enthusiasm, his inspiration, and his great efforts to explain things clearly and simply, he helped to make research fun for me. I learned a great deal under his supervision, which to me is so incredibly valuable. For this, I am eternally grateful. To all my friends at McGill, I thank you all for such a memorable experience. I will truly miss all of the interesting discussions, the all-nighters, and the pranks you pulled on me. They were certainly great times that I will never forget. I wish to thank my parents, my sister, my uncle, my aunt, my two cousins in Montréal for always being there. Finally, I thank the McGill staff for their support with departmental matters, keeping the servers alive and running, and for awards and financial support.

- ii - ABSTRACT

A design methodology based on generating the performance space of ampliﬁers by sweeping independent control variables has been investigated. The method is used to optimize the performance of CMOS ampliﬁers with respect to gain, bandwidth, noise, distortion and power directly in SPICE without the aid of mathematical models or external software routines. The method works in all SPICE programs from

Cadence to the student version of PSPICE. The technique is based on tuning the voltage of specific nodes of the amplifier using a self-biasing current source technique in conjunction with a replica amplifier circuit to span the entire performance space with a resolution of choice. The method has been tested with discrete implementation of the design. Both single-stage and multi-stage amplifiers are considered in this work. The method is generic, and it can be easily extended onto any amplifier topology for any performance measure.

- iii - ABREG´ E´

Une méthodologie de conception originale basée sur la production de l’espace des performances des amplificateurs en balayant les variables de contrôle indépendantes est examinée. Cette méthodologie peut optimiser des amplificateurs de CMOS par rapport au gain, àla bande passante, au bruit, àla déformation et àla puissance. L’espace des performances est recherchédirectement dans les logiciels SPICE sans l’aide d’aucun modèle mathématique ou des logiciels externes. Cette méthode fonc- tionne dans tous les logiciels SPICE, allant de Cadence àla version d’étudiant de PSPICE. La technique est basée sur la variation de tension dans des noeuds spécifiques de l’amplificateur en utilisant une source de courante dépendente et, en parrallèle, un circuit d’amplificateur copie pour créer l’espace des performances com- plet avec une résolution de choix. Cette méthodologie a ététestéavec les composantes séparées. Des amplificateurs àétage unique et àétages multiples sont considérés dans ce travail. Cette méthode est générique, et elle peut être facilement appliquée sur n’importe quelle topologie d’amplificateur pour n’importe quelle mesure de performance.

- iv - CLAIMS OF ORIGINALITY

This thesis contain the following original work • Investigation of the design by degrees of freedom method in the following am- pliﬁer structures: common-source, common-gate, common-drain, diﬀerential

ampliﬁer dicussed in Chapter 4.

• Separation of the node Vx in 1st and 2nd stage in master circuit of a multi-stage amplifier, using a different self-biased current source for each, to do DC biasing for each of the amplifier topologies in Chapter 5.

• Partial space exploration approach to multi-stage ampliﬁer design (cascaded ampliﬁer) and MATLAB program to do semi-automated partial space exploration discussed in subsection 5.1.1.

• Divide and conquer approach to multi-stage ampliﬁer design (two-stage opamp) discussed in subsection 5.1.2.

• Control variable reduction approach to multi-stage ampliﬁer design (folded cascode op amp) discussed in subsection 5.1.3.

• Extension of design by degrees of freedom method to a fully-differential amplifiers discussed in section 5.5. • Design verification using discrete electronics described in Chapter 6.

-v- TABLE OF CONTENTS

ACKNOWLEDGEMENTS ...... ii ABSTRACT ...... iii ABREG´ E...... ´ iv

CLAIMSOFORIGINALITY ...... v LISTOFTABLES ...... viii

LISTOFFIGURES ...... xi 1 Introduction...... 1

1.1 Motivation...... 1 1.2 ThesisStructure...... 3 2 Background on CMOS Ampliﬁer Design ...... 5 2.1 Classical Analog Design Overview ...... 5 2.1.1 CMOStechnology ...... 7 2.1.2 WhyIntegrated?...... 7 2.1.3 WhatisanAmpliﬁer?...... 8 2.1.4 PerformanceMetrics ...... 9 2.2 Stateoftheart ...... 21 2.2.1 gm/ID SynthesisApproach ...... 22 2.2.2 Computer-Aided Design based on Geometric Programming 27 2.2.3 Limitations...... 29 2.3 Summary ...... 31

3 Design by Degrees of Freedom ...... 32 3.1 Design by Degrees of Freedom Method ...... 32 3.2 Independent Control Variables ...... 33 3.3 Self-Biased Current Source Circuit ...... 38 3.4 Master-SlaveArrangement ...... 44

- vi - 3.5 Performance Simulation and Data Mining ...... 46 3.6 Summary ...... 49

4 Single-StageAmplifierDesign ...... 51 4.1 Common-SourceAmplifier ...... 51 4.2 Common-GateAmplifier ...... 67 4.3 Common-DrainAmplifier...... 69 4.4 DifferentialAmplifier ...... 70 4.5 Summary ...... 72

5 Multi-StageAmplifierDesign ...... 73 5.1 DesignHeuristics ...... 73 5.1.1 Partial Space Exploration Approach ...... 74 5.1.2 Divide and Conquer Approach ...... 75 5.1.3 Control Variable Reduction Approach ...... 77 5.2 Cascaded Amplifier Configuration ...... 77 5.3 Two-StageOpAmpConfiguration...... 82 5.4 Folded Cascode Op Amp Configuration ...... 90 5.5 Fully-Differential Design ...... 95 5.6 Comparisonofthethreemethods ...... 99 5.7 Summary ...... 102

6 DesignVerification ...... 103 6.1 Self-BiasedCurrentSource ...... 104 6.2 Common-SourceAmplifier ...... 107 6.3 Two-StageAmplifier ...... 115 6.4 Summary ...... 126

7 Conclusion...... 127 A OCEANcode: ControlVariableSweep...... 129

B MATLABcode: PartialSpaceExploration ...... 132 C MATLABcode:ProcessingWaveform ...... 139 References...... 140

- vii - LIST OF TABLES Table page

2–1 Node voltages and NMOS transistor’s region of operation...... 12 3–1 Number of design variables in different amplifier topologies...... 37 4–1 Trade-offsfortheCSAmplifier...... 67

4–2 Performance results for CS, CG, CD and DIFF amplifiers in CMOSP18 technology ...... 67 4–3 Trade-offsfortheCGAmplifier...... 69

4–4 Performance results for Vx=1.3V VoQ=1.1V Vp=0.7V Wn3=40µm Wp3=20µm Wp2=40µm Amplitude=100µV...... 69 4–5 Trade-oﬀsfortheCDampliﬁer...... 69

4–6 Trade-offsfortheDIFFamplifier...... 70 5–1 Trade-offs for the cascaded amplifier using partial space exploration method...... 81

5–2 Performance results for Cascaded, Folded Cascode, and Fully Diﬀeren- tial Folded Cascode ampliﬁers in CMOSP18 technology ...... 82 5–3 Performance comparison between divide and conquer approach and traditionalsimulationapproach...... 87

5–4 Performance comparison between compensated divide and conquer approach and traditional simulation approach...... 89 5–5 Trade-oﬀs for the 1st stage of the 2-stage operational ampliﬁer using divideandconquermethod...... 90

5–6 Trade-oﬀs for the 2nd stage of the 2-stage operational ampliﬁer using divideandconquermethod...... 90

- viii - 5–7 Trade-oﬀs for the 2-stage operational ampliﬁer using divide and con- quermethod...... 91

5–8 Controlvariablereductionmethod...... 94 5–9 Trade-oﬀs for the folded cascode ampliﬁer using control variable reduc- tionmethod...... 94

5–10 Trade-offs for the 1st stage of the fully-differential two-stage operational amplifierusingdivideandconquermethod...... 97 5–11 Trade-offs of the fully-differential two-stage operational amplifier using divideandconquermethod...... 98

5–12 Trade-offs for the fully-differential folded cascode amplifier using controlvariablereductionmethod...... 99

6–1 Performance measures for changing Vg for VoQ=0.6 N=1 P=1 VDD=4V.108

6–2 Performance measures for changing Vg for VoQ=0.6 N=1 P=1 VDD=1.2V.108

6–3 Performance measures for changing VoQ for Vg=2.97 N=1 P=1 VDD=1.2V.109 6–4 Performance measures for changing N for Vg=2.8 VoQ=0.5 P=1 VDD=4V.113

6–5 Performance measures for changing N for Vg=2.8 VoQ=0.5 P=1 VDD=1.2V.114 6–6 Performance measures for changing P for Vg=2.8 VoQ=0.7 N=1 VDD=4V.114

6–7 Performance measures for changing P for Vg=2.8 VoQ=0.7 N=1 VDD=1.2V.115

6–8 Performance measures for changing Vgd for VoQ=1.5 Vmid=2.825 Md=1 Mg=1Mp=1Mp2=1Mn2=1...... 121

6–9 Performance measures for changing Md for Vgd=1 VoQ=1.5 Vmid=2.825 Mg=1Mp=1Mp2=1Mn2=1...... 121

6–10 Performance measures for changing Mg for Vgd=1 VoQ=1.5 Vmid=2.825 Md=1Mp=1Mp2=1Mn2=1...... 124

6–11 Performance measures for changing Mp for Vgd=1 VoQ=1.5 Vmid=2.825 Mg=1Md=1Mp2=1Mn2=1...... 125

6–12 Performance measures for changing Mn2 for Vgd=1 VoQ=1.5 Vmid=2.825 Mg=1Mp=1Mp2=1Md=1...... 125

- ix - 6–13 Performance measures for changing Mp2 for Vgd=1 VoQ=1.5 Vmid=2.825 Mg=1Mp=1Md=1Mn2=1...... 126

-x- LIST OF FIGURES Figure page

2–1 Technology usage comparison. (Reference : Toshiba) ...... 8 2–2 Technology scaling down and integration of components onto a single chip.[1] ...... 9

2–3 Performancetrade-oﬀ.[2]...... 10

2–4 ID vs VDS for diﬀerent VGS [3]...... 12

2–5 Common-Source ampliﬁer with Vgn and Vgp forbias...... 13

2–6 SDR vs VoQ...... 16

2–7 SDR vs Vg...... 18

2–8 SDR vs VoQ forsmallinputamplitude...... 18

2–9 SDR vs Vg forsmallinputamplitude...... 19 2–10 Signal, noise, distortion vs input amplitude...... 20

2–11 Calculated (applying the model proposed in [4]) and measured gm/ID versus ID/(W/L) curves. Circles and squares for measured, solid and dashed for calculated data [5]...... 24

2–12Common-SourceAmplifier...... 25 3–1 Common-Source amplifier with an ideal current source and a capaci- tiveload...... 35 3–2 Common-Source amplifier with a diode connected transistor...... 35

3–3 CSampliﬁer...... 36 3–4 CGampliﬁer...... 36

3–5 CDampliﬁer...... 37

- xi - 3–6 DIFFampliﬁer...... 37

3–7 Equivalent circuit of the ideal op amp...... 38 3–8 Op-ampinfeedback...... 39 3–9 Self-biasing current source for CS ampliﬁer...... 40

3–10 Self-biasing current source for CG ampliﬁer...... 40 3–11 Self-biasing current source for CD ampliﬁer...... 40

3–12 Self-biasing current source for DIFF ampliﬁer...... 40 3–13 Self-biasing fully complementary CMOS folded cascode op amp. [6] . 42

3–14Differentialamplifier...... 43 3–15 Ideal vs non-ideal op amp tracking behavior...... 43 3–16 Common-Source amplifier in Master-Slave configuration...... 45

3–17 CS ampliﬁer data organized in Excel ...... 47 3–18FilteringthedatainExcel ...... 48

3–19FilteredresultsinExcel ...... 49 3–20 Filtered results using multiple constraints in Excel ...... 49

4–1 Common-Source ampliﬁer in Master-Slave conﬁguration...... 52

4–2 Gain vs Vg...... 54

4–3 Bandwidth vs Vg...... 55

4–4 Noise vs Vg...... 55

4–5 Distortion vs Vg...... 56

4–6 Power vs Vg...... 56

4–7 Gain vs VoQ...... 57

4–8 Bandwidth vs VoQ...... 58

4–9 Noise vs VoQ...... 58

- xii - 4–10 Distortion vs VoQ...... 59

4–11 SDR vs VoQ...... 59

4–12 Power vs VoQ...... 60

4–13 Gain vs Wn...... 61

4–14 Bandwidth vs Wn...... 61

4–15 Noise vs Wn...... 62

4–16 Distortion vs Wn...... 62

4–17 Power vs Wn...... 63

4–18 Gain vs Wp...... 64

4–19 Bandwidth vs Wp...... 65

4–20 Noise vs Wp...... 65

4–21 Distortion vs Wp...... 66

4–22 Power vs Wp...... 66 4–23 Common-Gate amplifier in master-slave configuration...... 68 4–24 Common-Drain amplifier in master-slave configuration...... 70

4–25 Differential amplifier in master-slave configuration...... 71 5–1 Flowchart of the MATLAB partial space exploration program. .... 76 5–2 Cascaded amplifier with ideal current sources...... 78

5–3 Cascaded ampliﬁer in master-slave conﬁguration...... 79

5–4 MATLAB plots showing partial space results for Vgd...... 80 5–5 MATLABiterationprompt...... 80 5–6 2-stage op-amp with ideal current sources...... 82

5–7 2-stage op-amp in master-slave conﬁguration...... 83 5–8 1ststagesimulationsetup...... 85

- xiii - 5–9 2ndstagesimulationsetup...... 85

5–10Combiningdatafrombothstages...... 85 5–11 Compensated 1st stage simulation setup...... 86 5–12 Compensated2nd stage simulation setup...... 86

5–13 Combining compensated data from both stages...... 86 5–14 Folded cascode ampliﬁer with ideal current sources...... 91

5–15 Folded cascode amplifier in master-slave configuration...... 92 5–16 Fully-differential amplifier...... 95

5–17 Fully-differential two-stage op amp in master-slave configuration. . . . 96 5–18 Fully-differential folded cascode amplifier in master-slave configuration. 100 6–1 Self-biasing current source for CS amplifier...... 104

6–2 Self-biased current source implementation with discrete components. . 105 6–3 Vout vs VoQ using LF357 and TL084 VDD=1.2 V...... 106

6–4 Vout vs VoQ using LF357 and TL084 VDD=4.0 V...... 106 6–5 CSampliﬁerschematic...... 107

6–6 Common Source ampliﬁer implementation with discrete components. 108

6–7 Experimental and simulated gain vs VoQ...... 110

6–8 Experimental and simulated bandwidth vs VoQ...... 110

6–9 Experimental and simulated noise vs VoQ...... 111

6–10 Experimental and simulated distortion vs VoQ...... 111

6–11 Experimental and simulated power vs VoQ...... 112 6–12 Schematic of stacked N-channel transistors in common-source ampliﬁer.112

6–13 Stacked N-channel transistors in common-source ampliﬁer implementation...... 113 6–14 2-Stage op-amp in master-slave conﬁguration...... 116

- xiv - 6–15 Two-Stage ampliﬁer implementation with discrete components. . . . . 117

6–16 Diﬀerential signal generation setup...... 117

6–17 Experimental and simulated gain vs VoQ...... 118

6–18 Experimental and simulated bandwidth vs VoQ...... 119

6–19 Experimental and simulated noise vs VoQ...... 119

6–20 Experimental and simulated distortion vs VoQ...... 120

6–21 Experimental and simulated power vs VoQ...... 120

6–22 Experimental and simulated gain vs Vx...... 122

6–23 Experimental and simulated bandwidth vs Vx...... 122

6–24 Experimental and simulated noise vs Vx...... 123

6–25 Experimental and simulated distortion vs Vx...... 123

6–26 Experimental and simulated power vs Vx...... 124

- xv - Chapter 1

Introduction

The work in this thesis investigates a CMOS ampliﬁer design method presented in the VLSI Design class at McGill University, Winter 2007 by Professor Gordon W.

Roberts. The design method addresses the growing need for a structured design and optimization methodology for amplifier design at the transistor level. A low-cost, fast and methodological way to design and optimize amplifier circuits using degrees of design freedom has been researched for this purpose in standard CMOS technology, as well as for discrete electronics. This work shows how the design concepts were proven through the application of the method on many different amplifier topologies. This chapter will discuss further the motivation for such methodologies, followed by the thesis structure.

1.1 Motivation

Ampliﬁers are one of the most basic building blocks in analog CMOS integrated circuits, which are widely used for communications, entertainment, multime- dia, biomedical, and many other applications that interface the physical world with the digital world. Despite the wide use in the world, analog CMOS circuit design is

-1- Chapter 1 generally viewed as a black art since there is no clear rational for selecting transistor sizes and circuit biasing. Moreover, one design solution does not necessarily translate into the solution of another circuit. It is generally accepted that every analog circuit must be customized for the task at hand, prolonging development cycles and increasing design risks. Circuit designers in the semiconductor industry are constantly working with the same analog circuit blocks but for different specifications. Many designers take their previous design, and tweak it to create a new circuit to meet new specifications. While this results in a suboptimal design solution, it also requires extra time and effort for designing a circuit every time a new specification is given, repeating the same design steps over and over. In addition, when the CMOS technology shrinks for the benefit of smaller transistor, faster digital logics, and lower power dissipation [7], designers in the semiconductor industry use the transistor aspect ratios from the previous technology as a starting point to port their design into the new technology. This usually results in vastly different performance from the previous technology because the technology- specific parameters have not been taken into account. The designer, then, usually has no choice but to sweep the design variables in many directions without any ex- pectation on the performance behavior in order to meet the specifications. This process can be very time consuming, as it too needs to be performed repeatedly for different specifications.

This suboptimal design practice calls for a need to step away from the current design methodologies, and develop a more structured and eﬃcient design method.

Thus, the goal in this work is developing a systematic CMOS ampliﬁer circuit design

2 Chapter 1 and optimization methodology that will help the designers to significantly reduce their time to design the same amplifiers for different specifications.

1.2 Thesis Structure

In Chapter 2, the thesis will start with the history of CMOS amplifiers and important amplifier performance metrics. Some of the current CMOS amplifier design and optimization methods will be reviewed as well. Chapter 3 will show the design method, and then dive into the issues of choosing the design variables which are essential to the design method. The circuitry required for this strategy will be described, such as servo-loop feedback biasing circuit and master-slave configuration. The simulation results of controlling the design variables for different amplifier topologies will be presented in Chapter 4. Four basic single-stage amplifier topologies will be investigated in this chapter. In Chapter 5, design strategies for multi-stage amplifiers will be introduced to overcome the excessive simulation time required on account of the increased number of control variables. Three methods will be shown through the design of a cascaded amplifier, a two-stage operational amplifier (Op- Amp), and a folded cascode amplifier. Extension to a fully-differential amplifier will be discussed in this chapter as well. The goal of these two chapters is to show how the optimal design solution can be achieved using the design method discussed in Chapter 3. This work will be followed by experimental results obtained from a discrete transistor implementation in Chapter 6. A chip was also fabricated in a 0.18 µm CMOS technology through CMC Microsystems, but due to the manufacturing defects of the 10 chips returned from fabrication, none were operational. Finally,

3 Chapter 1

Chapter 7 will discuss potential future work and summarize the material presented in this thesis.

4 Chapter 2

Background on CMOS Ampliﬁer Design

In this chapter, an overview on the analog transistor design will be given. This includes the reasons why CMOS technology and integrated circuits are preferred for analog circuit design. In addition, general background information and performance metrics of an ampliﬁer and two popular branches of ampliﬁer design will be presented along with its limitations: the gm/ID synthesis approach and the computer-aided design (CAD) method based on geometric programming.

2.1 Classical Analog Design Overview

Since the early days of electronics to the more sophisticated devices of today, the basic operation of electronics remained the same, that being, sending and receiving signals. A signal contains or conveys information about the state or behavior of a physical system. A signal can be considered to be of any detectable value of voltage, current, charge, etc. In general, signals can be divided into two categories: analog and digital. The main difference is that an analog signal is defined over a continuous range of time and a continuous range of amplitudes, whereas a digital signal is defined only at discrete values of amplitude and time.

-5- Chapter 2

During the last few decades, many experts predicted the demise of analog circuits. Digital signal processing algorithms were becoming increasingly more powerful while advances in integrated-circuit (IC) technology provided compact, eﬃcient implementation of these algorithms in silicon. Many functions traditionally realized in analog form could now be easily performed in the digital domain, suggesting that all processing of signals would eventually occur digitally. However, analog circuits are essential in many of today’s complex, high-performance systems mainly due to the fact that the physical world is inherently analog. This indicates that there will always be a need for analog circuitry to condition physical signals such as those associated with transducers, as well as to convert information from analog to digital for processing, and from digital back to analog for reuse in the physical world [8].

Compared to digital design, analog design is much more challenging in general. This is because while digital circuits deal with speed and power trade-oﬀ [1], analog circuits deal with a multi-dimentional performance trade-oﬀ of speed, power, gain, noise, distortion, etc.. Also, because of the precision required for analog circuits, it is much more sensitive to noise, cross-talk, and other interferances. Furthermore, high performance analog circuit designs can rarely be automated, typically requir- ing hand-crafted design and layout. It is also generally true that design, modeling and simulation of analog circuits require more experience and intuition than digital circuits.

In the following sections, a brief overview of the current state of analog design technology will be presented. In addition, an introduction to a generic amplifier and important characteristics of an amplifier will be briefly discussed.

6 Chapter 2

2.1.1 CMOS technology

In the mid-1960s, complementary metal-oxide-semiconductor (CMOS) devices1 were introduced, rapidly capturing the digital market. The main advantage of CMOS technology was that the gates only dissipated power during switching, and required very few devices in contrast to bipolar2 or GaAs3 counterparts. Also, the dimensions of metal-oxide-semiconductor (MOS) devices could be scaled down more easily than those of other types of transistors. As the speed of MOS transistors increased, CMOS technology was more and more favored in the analog circuit design as well [2]. In addition, very large scale integration of both digital4 and analog circuits5 for low cost can be achieved in CMOS technology. Due to these reasons, CMOS technology is now the mainstream technology for analog, digital and mixed-signal applications. The depiction of the transistor technology used in the past and more recently is shown in Figure 2–1.

2.1.2 Why Integrated?

A system which consisted of a large number of discrete components is power- hungry, huge, and expensive. Because of this, driven primarily by the memory and microprocessor market, integrated circuit technology has embraced analog design extensively, aﬀording a complexity, speed and precision that would be impossible to

1 both n-type and p-type transistors.

2 three-terminal device constructed of doped semiconductor material 3 Gallium arsenide, a compound of two elements, gallium and arsenic.

4 Digital signal processing, memory block. 5 analog to digital, digital to analog, ampliﬁers and ﬁlters.

7 Chapter 2

Figure 2–1: Technology usage comparison. (Reference : Toshiba) achieve using discrete implementations. Today, with the continued scaling down of semiconductor technology, more and more devices can be integrated onto a single chip using IC technology. An example of this integration is shown in Figure 2–2 [1].

2.1.3 What is an Ampliﬁer?

Signal amplification is the simplest signal processing task. The need for signal amplification arises because transducers6 produce signals that are weak7 . Such signals are too small for reliable processing, and processing is much easier if the signal magnitude is made larger. The block that accomplishes this task is the signal amplifier [9]. There are many different uses for electronic amplifiers today. For

6 a device that converts one type of energy or physical attribute to another for various purposes including measurement or information transfer. 7 In the microvolt (µV) or millivolt (mV) range and possessing little energy [9]

8 Chapter 2

Figure 2–2: Technology scaling down and integration of components onto a single chip. [1] example, power amplifier are used as the last amplifier in a transmission chain, typically designed for power efficiency. Audio amplifiers are usually built with BJTs or MOSFETs for input signal amplification. Operational amplifiers have high open loop gain and differential inputs to employ feedback for control of its transfer function, mostly applied to integrated circuits.

2.1.4 Performance Metrics

At this point, it is appropriate to discuss a few important performance metrics for ampliﬁers. In addition to gain and speed, such parameters as power dissipation, supply voltage, linearity, noise, or maximum voltage swings may be important depending on the nature of the application. Furthermore, the input and

9 Chapter 2

Figure 2–3: Performance trade-off. [2] output impedances determine how the circuit interacts with preceding and subse- quent stages. In practice, most of these parameters trade with each other, making the design a multi-dimensional optimization problem. This is one of the great challenges that analog circuit designer faces. An example of such trade-offs is illustrated in Figure 2–3, where the dotted line and arrows represent dependence of performance metrics between each other. This complex performance trade-off requires the designer’s intuition and experience to arrive at an acceptable compromise.

In this work, five fundamental performance measures are considered: gain, bandwidth, noise, distortion, and power dissipation. These performance measures were chosen because, in the author’s view, they are the most important characteristics of an amplifier. In any case, the performance measures chosen do not influence the design method. The method is generic, and it can include any performance measure.

This section will explore each of the ﬁve performance measures in detail.

10 Chapter 2

Gain

When amplifying a signal, care must be exercised so that the information contained in the signal is not changed and no new information is introduced. Thus, the output signal of the ampliﬁer should be an exact replica of that at the input, except for having a larger magnitude or possibly a phase shift. The input-output characteristic of an ampliﬁer is generally a nonlinear function that can be approximated by a polynomial,

2 n Vout(t)= a0 + a1Vin(t)+ a2Vin(t)+ ... + anVin(t) , (2.1) where Vin and Vout are the input and output signals, respectively. Parameter a0 is the operating point and a1 is the small-signal gain, also known as the ampliﬁer gain.

For a suﬃciently narrow range of Vin, the equation can be simpliﬁed to

Vout(t) ≈ a0 + a1Vin(t) , (2.2)

Distortion

Ideally, the information contained in the signal should not be changed after the signal ampliﬁcation. However, this is impossible due to the non-linear nature of a transistor and its diﬀerent modes of operation as shown by the I-V curve of a NMOS transistor in Figure 2–4.

MOSFET transistors have different modes of operation: cut-off, triode (linear), active (saturation), and velocity saturation due to the short-channel effect. Table 2–

1 summarizes the node voltages and the transistor’s region of operations, where VGT denotes the gate-source voltage minus the threshold voltage, VDS is the drain-source voltage, and VDSAT is the drain-source saturation voltage of a transistor.

11 Chapter 2

Figure 2–4: ID vs VDS for diﬀerent VGS [3].

Regions of Operation Node Voltages Cut-oﬀ VGT < 0 Triode VGT > 0 and VDS < VGT , VDSAT Active VGT > 0 and VGT < VDS, VDSAT Velocity Saturation VGT > 0 and VDSAT < VDS, VGT Table 2–1: Node voltages and NMOS transistor’s region of operation.

12 Chapter 2

Figure 2–5: Common-Source ampliﬁer with Vgn and Vgp for bias.

If, during the signal ampliﬁcation process, the mode of operation of a transistor changes due to the node voltage swing 8 , signiﬁcant change in the output waveform will occur. This is considered as signal distortion, and is obviously undesirable. In addition, as seen from Equation 2.1, the nonlinear nature of the transistors adds small harmonic distortion even if the transistor operates in the same mode. Harmonic distortion can be reduced if the operating point is placed where the best linearity is achieved, generally in the middle region of a transistor’s mode of operation. This also allows for the biggest output swing possible.

Let us consider the common-source (CS) ampliﬁer in Figure 2–5 where the gate of the PMOS transistor is biased by Vgp and the gate of the NMOS transistor is biased at Vgn, as well as AC signal (vin) is applied. This results in output volage having a DC (VoQ) component and a small-signal component (vout). If the NMOS transistor is to operate in the active mode with the greatest possible swing, the DC

8 bias point + signal amplitude goes above or below the intended boundary of operation.

13 Chapter 2

operating point of VoQ should be in the middle of the transistor’s active region. The triode mode boundary for the NMOS transistor is deﬁned as

VDSn = VGSn − Vtn = Vgn − Vtn (2.3) since the source of the NMOS transistor is tied to ground. As for the PMOS transistor, the triode mode boundary is deﬁned as

VDSp = VGSp − Vtp = Vgp − VDD − Vtp (2.4)

since its source is connected to VDD. Let us denote VDn as the minimum drain voltage of linear region of operation, and VDp as the maximum drain voltage of linear region of operation. Then, we can ﬁnd the middle point in the active region by ﬁnding the middle point between the lower boundary VDn and the upper boundary VDp as follows

VDn + VDp V − = . (2.5) D middle 2

From the schematic diagram in Figure 2–5, we see that VDn = VDSn and VDp = VDD

+ VDSp, thus, the middle point in the active region VD−middle can be rearranged as follows

VDSn + VDD + VDSp Vgn − Vtn + Vgp − Vtp V − = = (2.6) D middle 2 2

VD−middle is the DC operating point at the output node where the least distortion occurs and where the maximum input swing will occur. Therefore, ideally, we want the output operating point VoQ to be at VD−middle. For a given output operating point VoQ, the maximum input amplitude vin without causing the transistor to enter

14 Chapter 2 another region of operation can be calculated as follows

VoQ − A × vin1, max = VGSn + vin1, max − Vtn (2.7) for the NMOS transistor’s boundary, where A is the gain of the ampliﬁer. This equation can be re-written for vin1, max as follows

Vtn + VoQ − VGSn v 1 = . (2.8) in , max 1+ A

The PMOS transistor’s boundary is deﬁned as

VoQ + A × vin2, max = VDD + VGSp − Vtp , (2.9)

we can also re-write this equation for vin2, max as follows

VDD − VoQ + VGSp − Vtp v 2 = . (2.10) in , max A

Then, the maximum input amplitude vin, max is lower of the two amplitudes vin1, max and vin2, max, i.e.,

V + V − V V − V + V − V v = min( tn oQ GSn , DD oQ GSp tp ), (2.11) in, max 1+ A A which simpliﬁes to

V + V − V −V + V − V v = min( tn oQ gn , oQ gp tp ). (2.12) in, max 1+ A A since the source of NMOS transistor is tied to ground and the source of PMOS transistor is tied to VDD. Let us verify this theory through a simulation example. Driving the input of a

CS ampliﬁer of Figure 2–5 with a large AC input signal vin results in a large output

15 Chapter 2

Figure 2–6: SDR vs VoQ.

signal vout. The output signal appearing at the drain of the NMOS transistor will force the transistor to cross several regions of operation, resulting in a large amount of distortion. The ratio of signal to distortion component in the output signal is commonly referred as Signal-to-Distortion Ratio (SDR) and it can be obtained by making use of the following deﬁnition

Signal SDR = . (2.13) 2 2 2 Harmonic2 + Harmonic3 + Harmonic4 + ... p The changes in SDR value has been plotted against changing DC output voltage

9 VoQ in Figure 2–6. The simulation was performed in CMOSP18 technology. In

Figure 2–6, we observe a peak SDR when VoQ is near VDD/2, hence the lowest distortion. For symmetrical circuit conditions, i.e., VGSn = |VGSp| and Vtn = |Vtp|,

9 CMOSP18 is a design kit for TSMC’s 0.18-micron CMOS technology using Ca- dence tools released by CMC

16 Chapter 2

Equation 2.6 shows that VD−middle is at VDD/2. This is consistent with the simulation result shown in Figure 2–6.

According to Equation 2.6, adjusting VGSn, VGSp, Vtn, and Vtp will change where the peak SDR occurs. Let us consider the eﬀects of VGSn on SDR. Increasing Vgn, while keeping VoQ at 0.9 V results in a uniformly decreasing SDR as shown in Fig- ure 2–7. This agrees with Equation 2.6 since increasing Vgn, while keeping the other values constant under a symmetrical circuit conditions, will move VD−middle further and further away from 0.9 V, hence, decreasing SDR.

The other distortion component comes from the linearity of the ID versus VDS curve of Figure 2–4 within the same region of operation. Common sense tells us that we should have the best linearity in the middle of the transistor’s saturation region.

Figure 2–8 shows the SDR vs VoQ plot when a small input amplitude of 1 µV was applied at the input of the common-source ampliﬁer, such that the saturation-triode boundary of the transistor is not crossed. Figure 2–9 shows the SDR vs Vg plot with a small amplitude at the input. In both cases, Figures 2–8 and 2–9 show little diﬀerence from Figures 2–6 and 2–7. Interestingly enough, we can conclude that the minimum distortion, for both small and large input amplitude, can be achieved at the point found by Equation 2.6, and the maximum input amplitude can be then computed from Equation 2.11 for a given set of node voltages Vgn, Vgp and VoQ.

Noise

So far, we have looked at the small-signal gain of the amplifier and its distortion behavior. Another important parameter associated with an amplifier is its minimum input signal level. The minimum input signal level is determined by the amount of noise generated by the amplifier. Analog signals processed by an integrated circuit are

17 Chapter 2

Figure 2–7: SDR vs Vg.

Figure 2–8: SDR vs VoQ for small input amplitude.

18 Chapter 2

Figure 2–9: SDR vs Vg for small input amplitude. corrupted by two different types of noise: device electronic noise and environmental noise. The latter refers to random disturbances that a circuit experiences through the supply or ground lines, or through the substrate. Device electronic noise includes thermal noise generated by the random motion of electrons and low frequency flicker noise resulting from impurities in a conductive channel [2]. The power spectral density of the thermal noise and the flicker noise of a MOSFET is approximated by

2 2 1 K Si (f) = 4kT + (2.14) 3 gm WLCoxf where k is Boltzmann’s constant, T is the temperature in Kelvin, K is a constant dependent on device characteristics. Parameters W, L, Cox represent transistor’s width, length, and gate capacitance per unit area, and f is the frequency variable.

The rms value of a noise signal can be obtained by the following relationship [3]

V 2 = S2(f)df (2.15) n rms Z i

19 Chapter 2

Vin vs Vout 1200 Signal Noise Maximum 1000 Distortion Input Amplitude

800

600 Vout (V)

400 Minimum Input Amplitude 200

0 0 2 4 6 8 10 Vin (V) Figure 2–10: Signal, noise, distortion vs input amplitude.

An amplifier requires its input signal to be distinguishable from the noise, so that the amplified information will be collectible at the output. To summarize, signal, noise and distortion of a typical amplifier with respect to the input amplitude are plotted in Figure 2–10. The input amplitude where signal and noise intersect is defined as the minimum input amplitude level that the amplifier can correctly amplify. Any input signal below this level will be buried under the noise. On the other hand, the input amplitude where signal and distortion intersect is defined as the maximum input amplitude level that the amplifier can handle. Any input signal above this value will create excessive distortion and mask the input signal information.

20 Chapter 2

Bandwidth

Another important performance metric is amplifier bandwidth. The band of frequencies over which the gain of the amplifier is almost constant, to within a certain number of decibels (usually 3dB), is called the amplifier bandwidth. Normally the amplifier is designed so that its bandwidth coincides with the spectrum of the signals it is required to amplify. The bandwidth of an amplifier depends mainly on the parasitic capacitances and resistances in the circuit. In the case of a common-source amplifier, the bandwidth can be written using small-signal parameters as

1 g Bandwidth = m . (2.16) 2π CL

Power Dissipation

Finally, the power dissipated by the ampliﬁer is given by

P ower = VDD × I. (2.17)

It is possible to build a very high-performance ampliﬁer at the expense of power.

However the increasing circuit density and size of integrated systems tend to make low power consumption a primary concern [10], [11]. Hence, the power dissipation of the analog circuits must be kept to minimum.

2.2 State of the art

As discussed earlier, analog circuit design poses many great challenges and there is no straight-forward answer to the design problem. For an ampliﬁer design, this holds true due to the complex trade-oﬀs among many performance metrics. As a

21 Chapter 2 result, there has been an increased effort to simplify the design process. In this section, two main branches of these methods will be discussed. The first amplifier design method presented is based on the transconductance efficiency method denoted as the gm/ID method. The second design method described uses geometric programming principles. The shortcoming of both methods will be also discussed.

2.2.1 gm/ID Synthesis Approach

The gm/ID synthesis method was ﬁrst introduced in the 1990s by F. Silveira, D. Flandre and P. G. A. Jespers [5]. Since then, many papers refer to this methodology [12], [13], [14], and [15] for comparison and for possible improvements. In addition, there is a book [16] advocating analog ampliﬁer design through this approach and some top-rated university (Stanford and Berkley) amongst many in the

United States teach courses specifically focused on this design method. The strength of this method is its simplified approach. Typically, analog circuit designers reach their goal by taking advantage of their own experience while performing lots of simulations and optimizations. By using this methodology, circuit designers can tackle the problem even without an extensive experience in the field, since the methodology is straightforward, and is touted to give a near optimal solution [16]. In this method, the relationship between the ratio of the transconductance over

DC drain current, denoted gm/ID, and to what is referred as the normalized current

ID/(W/L) are considered as fundamental design parameters. The term gm/ID was chosen as a design variable for the following three reasons: 1) It is strongly related to the performance of analog circuits. 2) It gives an indication of the device operating region.

22 Chapter 2

3) It provides a tool for calculating the transistors dimensions.

The ratio gm/ID is strongly related to the performances of analog circuits because gm/ID ratio is a measure of the eﬃciency to translate current into transconductance. For example, the greater the gm/ID value, the greater the transconductance we obtain at a constant current value. Sometimes, this ratio is interpreted as a measure of the transconductance eﬃciency.

W Figure 2–11 shows the gm/ID ratio versus the normalized current ID/ L plot.

We can observe that the gm/ID ratio is maximum in the weak inversion region where

W the normalized current ID/ L is small, falling oﬀ in a linear fashion in the strong inversion region due to the charge transport velocity saturation eﬀect. Therefore, gm/ID is also an indicator of the mode of operation of the transistor.

Now, consider the dependence of gm/ID on the transistor size. The gm/ID ratio can be expressed as the derivative of the logarithmic of ID with respect to VG as shown below g 1 δI δlnI m = D = D . (2.18) ID ID δVG δVG We can rewrite this equation to equal the logarithmic of the derivative of normalized

W current ID/ L with respect to VG using the fact that

δln W L (2.19) δVG is 0 as follows, W W g δlnI δ(lnID − ln ) δlnID/ m = D = L = L . (2.20) ID δVG δVG δVG W Since the normalized current ID/ L is independent of the transistor size by deﬁnition, gm/ID is also independent of the transistor size. This suggests that the relationship

23 Chapter 2

Figure 2–11: Calculated (applying the model proposed in [4]) and measured gm/ID versus ID/(W/L) curves. Circles and squares for measured, solid and dashed for calculated data [5].

24 Chapter 2

Figure 2–12: Common-Source Ampliﬁer.

between gm/ID and the normalized current is a unique characteristic for all transistors

W of the same type in a given batch. This universal quality of the gm/ID versus ID/ L curve can be extensively exploited during the design phase, when the transistor aspect ratios (W/L) are unknown. Once a set of values gm/ID, gm, and ID is found, the W/L of the transistor can be determined unambiguously. To help understand this, a single transistor used as a common-source ampliﬁer is shown in Figure 2–12.

The transistor’s small-signal output conductance is

ID gd = , (2.21) VA where ID is the DC current delivered by the ideal current source, and VA is the early voltage of the transistor. The small-signal gain (A) and transistor unity-gain frequency (fT ) are given by

gm gm A = − = − VA , (2.22) gd ID

25 Chapter 2 and

1 gm fT = . (2.23) 2π CL

Given the values of VA and CL and the speciﬁcation for the bandwidth fT , gm can be derived from Equation 2.23 as

gm = 2πfT CL . (2.24)

Given the speciﬁcation for the gain A, ID can now be derived from Equations 2.22 and 2.24 as 2πf C I = − T L V . (2.25) D A A Subsequently, we can determine the transistor size W/L by looking at Figure 2–11 and ﬁnding the value of W/L that would result in the desired value of gm/ID. Other performance aspects can be taken into account as long as they are directly

W related to the gm/ID versus ID/ L relationship, i.e., to the current and small signal parameters. For large signal related performance aspects such as signal swing, an

ID − VG or gm/ID − VG relationship is required.

W The actual gm/ID versus ID/ L curve can be obtained in two ways: either ana- lytically, using a MOS transistor model that provides a continuous representation of the transistor current and small-signal parameters in all regions of operations, such as the models proposed in [4], or from measurements on a typical transistor. In order to obtain this curve from measurements, a mean curve representing measurements of large number of transistors has to be considered to account for process spreads. Fig-

W ure 2–11 shows the calculated and measured plots of gm/ID versus ID/ L for nMOS

26 Chapter 2 and pMOS silicon-on-oxide (SOI) fully-depleted transistors as well as for bulk transistors. The solid and dashed curves were obtained through calculation by applying the model presented in [4].

2.2.2 Computer-Aided Design based on Geometric Programming

Computer-Aided Design (CAD) methods are used extensively in the design of analog IC circuits. Using an automated design method, complexity of the design process and design time can be signiﬁcantly reduced. There are a lot of diﬀerent CAD methodologies available. The literature on CAD on analog circuits go back more than

20 years, including equation based methods such as Lagrangian relaxation10 , Semi- deﬁnite programming11 and simulation based methods such as, JiﬀyTune (IBM)12 and Adapt (Philips)13 . In this section, Computer-Aided Design based on Geometric

Programming will be discussed in detail. Design of a CMOS Op-Amp via geometric programming is an extremely fast method that can handle a wide variety of speci-

ﬁcations and constraints, and it can result in globally optimal designs [19]. This is an equation-based optimization method, where the circuit sizing problem is decribed

10 a relaxation technique which works by moving hard constraints into the objective so as to exact a penalty on the objective if they are not satisfied. 11 a subfield of convex optimization concerned with the optimization of a linear objective function over the intersection of the cone of positive semidefinite matrices with an affine space. 12 circuit optimization using time domain sensitivites [17]. 13 Iterative Analog Synthesis tool [18].

27 Chapter 2 through a set of equations that model the behaviour of the ampliﬁer and its building blocks. The approach is as accurate and as general as the underlying transistor models [20]. A Geometric Program is a type of mathematical optimization problem of the form:

minimize fo(x)

subject to gi(x) (2.26)

and x > 0 where x is a vector [x1,x2,...,xj,...,xn].

The objective function is fo(x) and each one of the constraint function gi(x) are posynomials if gi(x) ≤ 1 or monomials if gi(x) = 1 of the design variables x’s. In equation form, a posynomial function is described by

αij g(x)= Ci xj (2.27) Xi Yj where Ci’s are positive coeﬃcients and αij’s are arbitrary real numbers. With a logarithmic transformation on the design variables, the posynomial function can be written as

( αij zj ) g(z)= Cie j (2.28) P Xi where zj = ln xj. It can be easily shown that g(z) is a convex function [21] of the transformed variables zj’s. As a result, the op-amp design problem becomes a convex programming problem. The well known property of a convex programming problem is that any of its local minima is also a global minimum [22].

28 Chapter 2

Let’s go back to the CS ampliﬁer in Figure 2–12. A simple design optimization problem can be represented as: Minimize power consumption

subject to

Gain > GainSPEC

Bandwidth > BandwidthSPEC

By expressing these inequalities in circuit parameters, such as gm × ro for gain, and 1 gm for bandwidth as per equation 2.23, the two constraint functions g (x) and 2Π CL 1 g2(x) are obtained. The objective function can be expressed as fo(x)= ID × VDD. Minimize

fo(x1, x2, x3) = ID × VDD subject to

g1(x1, x2, x3) = gm × ro > GainSPEC

1 gm g (x1, x2, x3) = > BandwidthSPEC 2 2π CL where x1 = gm, x2 = ID, x3 = ro. Now, it is only a matter of solving convex programming problem using a computer program such as MATLAB, for a global optimal solution to be found. In case a solution cannot be found, the method will unambiguously detect that the problem is unfeasible [23].

2.2.3 Limitations

The above methods helped to increase designer’s productivity. However, these methods depend heavily on the quality of the mathematical models used to represent the transistor. For the gm/ID method, the gm/ID versus ID/(W/L) curve is critical to the design, and as for the optimization via geometric programming method, all

29 Chapter 2 the performance measures need to be represented using mathematical models. In the past, first-order transistor models taught in most textbooks were sufficient in char- acterizing transistors in the integrated circuit. However, due to the advancement in CMOS technology, the present first-order transistor models are no longer accurate when modeling transistors. Circuit simulators such as SPICE use experimental data curves to generate models for each technology. This ensures the simulated data closely resembles the behavior of real devices. The full order transistor models used by SPICE includes leakage, short-channel effects, and parasitic capacitances, which make it too complex to be used in the gm/ID method or the optimization via geometric programming method. Developing a good mathematical model of transistors behavior to be used in gm/ID or geometric programming methods takes a lot of effort, and they can only be as accurate as the models used in SPICE. Coming up with these models is a time consuming process, and the modeling effort often introduces additional error into the design process. Often this error is eliminated by further tuning the circuit with

SPICE models at the end of the design ﬂow. In many ways, repeating the design steps all over again using SPICE.

W In addition, the gm/ID method assumes that the normalized current ID/ L is constant for W and L, which is not true for short-channel devices [5], further creating mismatch between the desired operation and the actual operation.

30 Chapter 2

2.3 Summary

In this chapter, an overview of the classical analog design and amplifiers were presented. The rise of CMOS technology and IC technology was described. Im- portant characteristics and measures of performance of an amplifier, such as, gain, bandwidth, noise, distortion and power were explained in detail. Current amplifier design methods, such as gm/ID synthesis method and the CAD method based on geometric programming were discussed. The limitations of these methods were also highlighted, making way for the design by degrees of freedom method of the next chapter.

31 Chapter 3

Design by Degrees of Freedom

In this chapter, a design method based on sweeping the degrees of freedom in an amplifier is described. By the degrees of freedom in an amplifier, we are referring to the design variables in an amplifier, therefore the choice of the right design variables will be carefully considered. In addition, we will introduce a new circuit, such as the self-biased current source together with a master-slave arrangement that supplements this design method. This chapter also shows how to effectively design an amplifier based on the data gathered using this design strategy.

3.1 Design by Degrees of Freedom Method

Analog designers are constantly tweaking design variables such as ID, gm, ro, W or L to meet a set of design speciﬁcations. This is not only time consuming but also repetitive since they need to re-do the searching process whenever the speciﬁcations change.

If the circuit’s performances are stored for each combination of design variables, there would be no longer any need for repeating the same design steps over and over. This can be achieved by sweeping the control variables and storing the resulting

- 32 - Chapter 3 performance behaviors into a library. In order to do this, the control variables must be clearly defined, and should be easily controllable for sweeping purposes. The biasing conditions change when a control variable is changed, therefore, a feedback mechanism is used to regulate the biasing conditions through a self-biasing circuit that will be described in the following section. Finally, data mining section will show how the results of the sweeps can be used to design an arbitrary amplifier meeting specifications.

3.2 Independent Control Variables

Electronic ampliﬁer design generally begins with a hand analysis of the ampliﬁer, leading to an expression for various performance measures. For example, small-signal analysis is used to yield an expression for gain, bandwidth, and noise. Distortion is usually handled by working with a Taylor series expansion of the large-signal behavior of transistor operation driven by a sinusoidal signal. Power dissipation is normally found by a large-signal DC analysis. These expressions contained gm, ro and ID, which led people to use them as the basis of a set of control variables for circuit design.

In all cases, the expression found for the different amplifier performance measures can be traced back to the i-v equation for each transistor. Using a unified model of transistor behavior [24], the drain current can be written in terms of its gate, drain, source terminal voltages, as well as the transistor sizes W and L, as follows W V 2 I = k′ V V − min (1 + λV ) , (3.1) D L GT min 2 DS

33 Chapter 3 where

Vmin = min(VGT , VDS, VDSAT ) and the overdrive voltage is

VGT = VGS − Vt.

Here, VGS, VDS, VDSAT denote the gate-source voltage, drain-source voltage, and drain-source saturation voltage, respectively. The parameter Vt is the threshold voltage of the transistor. Interestingly enough, transistor small-signal parameters gm and ro can also be written in terms of these same node voltages as

W g = k′ V (3.2) m L GT and − W V 2 1 r = λk′ V V − min . (3.3) o L GT min 2 By looking at Equations 3.1, 3.2 and 3.3, both the large-signal and small-signal circuit behavior is clearly dependent on transistor node voltages and transistor di- mension W and L. This suggests that for every transistor, ﬁve variables VG, VD, VS, W and L control its behavior for both large and small-signal operation. In other words, these are the independent control variables for the circuit.

The control variables used traditionally, such as ID, gm, ro or the overdrive voltage VGT are, in fact, dependent variables. The advantage of using the proposed independent control variables are numerous. First, a straight-forward performance to control variable relationship can be observed. By keeping the rest of control variables constant, and moving only one control variable at a time, it is possible to see how the performance measures change against the control variable that is being swept. With

34 Chapter 3

Figure 3–1: Common-Source ampliﬁer Figure 3–2: Common-Source ampliﬁer with an ideal current source and a ca- with a diode connected transistor. pacitive load.

the commonly used dependent control variables (ID, gm, ro), augmenting gm aﬀects the other control variables, such as ID, ro, and VGT , therefore, it is not possible to relate performance measures to such control variables on a one-to-one basis.

Secondly, if a circuit solution is found in terms of gm,ID, ro, and VGT , it might lead to an inconsistent or impractical solution, as each variable depends on the others.

Whereas, using the proposed independent control variables described previously, all design possibilities are a combination of these 5 control variables. They form an independent and complete set of a basis function. At first, 5 independent control variables per transistor might seem a little too excessive. However, as transistors in a circuit share nodes with other transistors, many of these control variables collapse to a lesser number, significantly reducing the number of degrees of freedom in the design. For example, let’s look at a common-source amplifier in Figure 3–1. If the ideal current source is replaced by a diode connected transistor as shown in Figure 3–2, the common-source amplifier has two transistors,

35 Chapter 3

Figure 3–3: CS ampliﬁer. Figure 3–4: CG ampliﬁer.

and two distinct nodes (excluding power supply connections): Vin and Vout. There- fore, from the original 10 control variables (5 design variables × 2 transistors), the number of control variables collapse to 6 (2 nodes + W,L × 2 transistors). In general, a circuit consisting of N nodes (excluding power supply connections) and M transistors has N+2M degrees of design freedom. In many cases, analog designers set the transistor length to a fixed value, typically 1.5 - 2 times the minimum length [25], further reducing the number of control variables by one for each transistor, resulting in N+M degrees of design freedom overall. Applying this analysis to basic amplifier types shown in Figures 3–3, 3–4, 3–5 and 3–6, the number of control variables for the four standard single-stage CMOS amplifier topologies: common- source (CS), common-gate (CG), common-drain (CD) and differential (DIFF) amplifiers can be obtained. Table 3–1 lists the number of design variables for different amplifier topologies.

36 Chapter 3

Figure 3–5: CD ampliﬁer. Figure 3–6: DIFF ampliﬁer.

Circuit Parameters Degrees of Freedom Topology ♯ of Nodes (N) ♯ of Transistors (M) N+2M N+M Common-Source 2 2 6 4 Common-Drain 2 2 6 4 Common-Gate 3 3 9 6 Differential Amplifier 2 3 8 5 Table 3–1: Number of design variables in different amplifier topologies.

37 Chapter 3

Figure 3–7: Equivalent circuit of the ideal op amp.

3.3 Self-Biased Current Source Circuit

Consider the common-source ampliﬁer shown in Figure 3–3. It has 2 nodes and 1 transistor, resulting in 4 degrees of design freedom (Vout, Vin, W and L). Even though a current source is driving the drain terminal of this ampliﬁer, this current is dependent on these four control variables. As a result, if we wish to change the control variables without worrying about how much current should be supplied, we must replace the ideal current source with a dependent current source.

A simple way of achieving this is through the use of a transistor op amp arrangement in negative feedback. First, recall the basic properties of an op amp. A single-ended op amp with positive (Node 1), negative (Node 2) and output (Node 3) terminal is shown in Figure 3–7. It has the following characteristics [9]:

1. Inﬁnite input impedance 2. Zero output impedance

3. Zero common-mode gain 4. Inﬁnite open-loop gain A

38 Chapter 3

Figure 3–8: Op-amp in feedback.

5. Inﬁnite bandwidth Now, consider the circuit in Figure 3–8. It consists of an op amp with a transistor in its feedback path, as well as a grounded resistor connected at the positive terminal of the op amp. The op amp in this inverting conﬁguration will sense the voltage at its negative node, and will adjust its output voltage, such that the voltage at the positive node equals the voltage at its negative node. Note that the positive and negative nodes are interchanged because of the presence of a transistor in the feedback path 1 . We now have a device that can sense the voltage at its negative input terminal, and adjust its output such that the positive input terminals tracks this voltage.

1 the voltage gain from gate to drain carries a negative sign.

39 Chapter 3

Figure 3–9: Self-biasing current Figure 3–10: Self-biasing current source for CS ampliﬁer. source for CG ampliﬁer.

Figure 3–11: Self-biasing current Figure 3–12: Self-biasing current source for CD ampliﬁer. source for DIFF ampliﬁer.

40 Chapter 3

Applying this concept to the common-source ampliﬁer, a self-biased current source can be achieved as shown in Figure 3–9. Here the op amp drives the gate of

Mp such that the drain voltage is set to the voltage established by voltage source

VoQ. Basically, we have only replaced the resistor from Figure 3–8 by transistor Mn. We shall refer to this biasing arrangement as self-biasing to emphasize the fact that the current in the transistor is a dependent variable, rather than an independent one. A similar biasing approach is shown in 3–10, 3–11 and 3–12 for the other basic ampliﬁer ciruits of Figures 3–4, 3–5 and 3–6, respectively.

In all of these units, the added op amp does not influence the performance of the amplifier. The ideal op amp has infinite input resistance, and zero output resistance. Therefore, the positive node of the op amp in Figure 3–9 will not see any loading effect. The node Vb1 will also act as if an ideal voltage source is connected. Zero common-mode gain, and infinite differential gain of the ideal amplifier will make sure that the positive and negative node voltages of the op amp will be the same, no matter what input level appears. Finally, infinite bandwidth will ensure that any change in the input voltage will be immediately tracked by the op amp, instantaneously setting a new bias output voltage. The ideal op amp in Figure 3–7 works perfectly in the making of a self-biased current source. However, an ideal op amp is not available in the real physical world. What would happen to the self-biased current source if a non-ideal op amp was used instead? Two non-ideal amplifiers will be compared against the behavior of a self-biased current source with an ideal op-amp. This study will enable us to understand the practical trade-off involved in constructing the self-biasing current source.

41 Chapter 3

Figure 3–13: Self-biasing fully complementary CMOS folded cascode op amp. [6]

One desirable property of an ideal op amp is its rail-to-rail functionality. The op amp topology presented by Mandal [6] has this property. It has an added benefit that the op amp uses no bias voltages other than the two supply rails. The fully complementary nature of the folded cascode op amp shown in Figure 3–13 allows for rail-to-rail input voltage tracking. In addition, it does not require external biasing, which simplifies the op amp structure. The dimensions of the transistors are 1 µm / 500 nm for both the NMOS and PMOS transistors in CMOSP18 technology. The second amplifier is a simple differential amplifier shown in Figure 3–14.

The dimensions of the transistors are 1 µm / 500 nm for both the NMOS and PMOS transistors in CMOSP18 technology.

42 Chapter 3

Figure 3–14: Diﬀerential ampliﬁer.

Figure 3–15: Ideal vs non-ideal op amp tracking behavior.

43 Chapter 3

The simulation results are obtained and plotted in Figure 3–15. As observed in

Figure 3–15, there’s no real difference in tracking the voltage levels between an ideal op amp and transistor implemented amplifiers. Especially the high performance op amp tracks the VoQ as closely as an ideal op amp. The DIFF amplifier tails off at high voltage level, since it is not a complimentary design, but still tracks the input well for the range of normal operation for VoQ. Care must be exercised when building a self-biasing current sources. For example, the top transistor Mp of Figure 3–9 must be large enough to provide the necessary current that the bottom transistor requires, depending on the node voltages Vg and VoQ, and the transistor size Wn and Ln. If this condition is not satisfied, the feedback around the op amp will open and voltage tracking between VoQ and

Vout will not occur.

3.4 Master-Slave Arrangement

While the biasing circuits of Figure 3–9 enable full control of all node voltages in the circuit, AC signals will not ﬂow freely through the circuit. The self-biasing current source will try to compensate for any AC signal, and hold the drain node constant.

To get around this constraint, we make use of a master-slave biasing arrangement. Figure 3–16 shows the master-slave biasing arrangement for the common-source am- pliﬁer of Figure 3–9. The master circuit contains the self-biasing current source. The slave circuit is an exact replica of the master circuit without the self-biasing current source. The bias voltages are shared between the master and slave circuit, hence, the DC voltages of the master and slave circuit are identical across all nodes.

44 Chapter 3

Figure 3–16: Common-Source ampliﬁer in Master-Slave conﬁguration.

The self-biasing circuit together with the master-slave configuration is an excel- lent biasing circuit. It is extremely robust to process, supply voltage, temperature variations because the op-amp in feedback is able to adjust for any variations and track the reference signal VoQ. However, at this point in our discussion, it should be noted that the master biasing circuit and the self-biasing current source are only used to search the design space. It is not intended to be incorporated with the final design because it would require a lot of silicon area to include these structures2 in addition to the amplifier circuit itself. Rather, a simpler biasing circuit, such as a current mirror, would in all likelihood be created, once the desired biasing conditions are found.

2 Master-Slave arrangement requires double the silicon area of an ampliﬁer topology, in addition to 20 µm × 15 µm per op amp used for self-biasing.

45 Chapter 3

3.5 Performance Simulation and Data Mining

Using the above servo-loop feedback biasing circuit and master-slave arrangement, controlling the design variables is made possible. SPICE simulations are performed by sweeping each of the design variables and computing the performance metrics for each set of control variables. The parametric sweep can be performed directly in the existing circuit simulation tools, such as Analog Design Environment or script-based tools, such as OCEAN or SpectreMDL. An examplary code for parametric sweep in OCEAN can be found in the appendix A. The data generated by spanning the performance space can be easily organized into a library using even the simplest database tool such as Microsoft Excel.

Figure 3–17 shows the data for a common-source ampliﬁer organized into an

Excel file. The four control variables (Vg, VoQ, Wn, Wp) are listed at first, followed by gain, bandwidth, noise, FFT results for the signal, 2nd, 3rd, 4th harmonic, and the current through the supply. The FFT results and the current can be manipulated to yield distortion and power dissipation. Note that the bias points and the performance measures for each set of bias points are stored. At this point, an optimal design solution can be found quickly by looking at the data without the need for further simulation. This can be repeated for different specifications. For example, let us choose a gain of 100 V/V as a minimum condition. Figure 3–18 shows how the data is filtered using Excel and Figure 3–19 shows the resulting data list. This now gives 16 possible bias points and the sizing of the transistors that will give a common-source amplifier with a gain greater than 100 V/V. It is possible to use

ﬁlters on multiple performance measures simultaneously as well. For example, bias

46 Chapter 3 Figure 3–17: CS ampliﬁer data organized in Excel

47 Chapter 3

Figure 3–18: Filtering the data in Excel condition for a common-source ampliﬁer with a gain of 100 V/V, bandwidth of 8

MHz, consuming less than 0.21 mW is shown in Figure 3–20. We believe that this method is extremely powerful since only one set of simulation is required for each design topology. The results file contains all possible behaviors of the performances metrics with a choice of resolution that will be described in the next chapter. The value of this work is about showing how to generate these design spaces for each amplifier topology through the use of the control variables, servo-loop feedback biasing circuits and a master-slave arrangement. Furthermore, by exploring the design space, the trade-offs of the performance metrics can be viewed simply by plotting the results against the sweeped control variables. This will be explained in greater detail in the next chapter.

It is important to note that any performance measure can be considered for this work, it is simply a matter of choosing what to be saved in the results ﬁle.

48 Chapter 3

Figure 3–19: Filtered results in Excel

Figure 3–20: Filtered results using multiple constraints in Excel

3.6 Summary

In this chapter, a design methodology that identifies degrees of design freedom in an amplifier was described. The method consists of sweeping the degrees of design freedom, and saving all the performance information so that they can be re-used for different specifications. The degrees of design freedom are effectively the control variables in a circuit, and the choice of the independent control variables were discussed. The node voltages and the size of the transistors make the perfect independent design variables because they are independent and the number of variables usually collapse to a lesser number due to the sharing of the nodes in the circuit.

In addition, these control variables will always form an independent set that can be realized on a transistor level, unlike gm, ro and ID. It was shown that the total degrees of design freedom in a circuit consisting of N nodes and M transistors will be N+2M. In order to sweep these design variables, a self-biased current source was

49 Chapter 3 introduced. This biasing circuit consists of an op-amp and a transistor to provide a current, such that the two input terminals of the op-amp track each other in terms of voltage. In addition, the introduction of master-slave configuration separate DC biasing concerns from AC concerns. Finally, the data mining section showed how to design an amplifier quickly and efficiently using the filtering capabilities of Excel.

50 Chapter 4

Single-Stage Ampliﬁer Design

In this chapter, single-stage amplifiers will be designed using the biasing circuits and master-slave arrangement outlined in Chapter 3. Four basic amplifier topologies will be considered: common-source amplifier, common-gate amplifier, common-drain amplifier and differential amplifier. Gain, bandwidth, noise, distortion and power consumption results are obtained by sweeping each of the control variables. For the common-source amplifier, the performance space has been plotted against the control variables from the data. As for the other topologies, a summary of the relationships were derived and organized into a table from the gathered data.

4.1 Common-Source Ampliﬁer

A CS ampliﬁer using master-slave conﬁguration is setup as shown in Figure 4–

1. The performance space for a CS ampliﬁer can be obtained by sweeping the two voltage control variables: Vg, VoQ and the four transistor parameters Wn, Ln, Wp, Lp through a range of values. Interestingly enough, these six variables span the entire performance space for this topology. Alternatively, these six variables determine all possible bias points for the circuit.

- 51 - Chapter 4

Figure 4–1: Common-Source ampliﬁer in Master-Slave conﬁguration.

In reality however, we are often limited by simulation time in exploration of performance space. For the most part, this becomes a question of performance space resolution versus simulation time. An acceptable resolution size has to be chosen as a compromise to reduce the simulation time. For example, a sweep of two voltage control variables with a resolution of 10 mV will require 100 times more simulations than a sweep of voltages with a resolution of 100 mV. The number of simulations required increases exponentially as more control variables are involved. This is why it is crucial to choose the right resolution to be able to span the performance space in a timely manner without losing too much information. Another important consideration is the choice of simulation type. Each type of simulation adds significant time, as it has to be performed for each set of control variables. For the given 5 performance measures selected here, four different types of simulation will be selected: AC analysis is required to find gain and bandwidth of the circuit; noise analysis yields the noise value; transient analysis is used to find

52 Chapter 4 the distortion in the circuit and a DC analysis is performed to ﬁnd the static power dissipation. For a relatively simple circuit topology, such as the CS ampliﬁer of Figure 3– 16, on average, AC analysis takes about 40 ms, DC analysis takes about 10 ms, transient analysis takes about 220 ms, and noise analysis takes about 30 ms. The total simulation time is 0.3 second on a machine with 1024 Megabytes of ram and 450

MHz of processing speed running SunOS on a UNIX machine by Sun Microsystems. For this topology, if 10 different values for each voltage and width variable are used, in addition to 3 different values for each length, the performance space generated will contain 90 000 (10 × 10 × 10 × 10 × 3 × 3) distinct values for the control variables. We can expect a total simulation time of about 7.5 hours (90000 × 0.3s). This is a reasonable value given that these results would only have to be generated once for this amplifier type in a given technology.

The performance space is explored using the above setup, and the data has been organized into an excel ﬁle similar to the one shown in Figure 3–17 of the previous chapter. Some distinct sets of control variables have been taken out of the data pool to illustrate the relationship between the control variables and the performance measures. These are as follows:

Figure 4–2 shows the relationship between gate-controlled voltage Vg and the small-signal gain. Figure 4–3 shows bandwidth vs Vg. Figure 4–4 shows noise vs Vg.

Figure 4–5 shows distortion vs Vg. Figure 4–6 shows the power dissipation vs Vg.

The ♦ line uses the set VoQ = 1.2V, Wn = 20µm, Wp = 40µm, Ln = 0.5µm, Lp =

0.5µm. The 2 line uses the set VoQ = 0.6V, Wn = 40µm, Wp = 20µm, Ln =

0.5µm, Lp = 0.5µm. The ∆ line uses the set VoQ = 0.9V, Wn = 20µm, Wp =

53 Chapter 4

Figure 4–2: Gain vs Vg. ♦ : VoQ = 1.2V, Wn = 20µm, Wp = 40µm, Ln = 0.5µm, Lp = 0.5µm. 2 : VoQ = 0.6V, Wn = 40µm, Wp = 20µm, Ln = 0.5µm, Lp = 0.5µm. ∆ : VoQ = 0.9V, Wn = 20µm, Wp = 20µm, Ln = 0.5µm, Lp = 0.5µm.

20µm, Ln = 0.5µm, Lp = 0.5µm. They all show similar behaviors, increasing uniformly or decreasing uniformly above the threshold voltage Vtn which is around 0.5V for the CMOSP18 technology. Notice that the 2 line does not generate results above Vg = 0.8V , and the ♦ line’s results above Vg = 1.0V are also missing. This is because the top transistor Mp is not big enough to provide the current that the bottom transistor requires for the desired node voltages Vg and VoQ, as discussed in Section 3.3 of Chapter 3.

Now, let’s consider the performance measures vs VoQ. The three sets used in this simulation are: ♦(Vg = 0.5V, Wn = 40µm, Wp = 40µm, Ln = 0.5µm, Lp = 0.5µm),

2(Vg = 0.8V, Wn = 20µm, Wp = 20µm, Ln = 0.5µm, Lp = 0.5µm), and ∆(VoQ =

1.1V, Wn = 20µm, Wp = 60µm, Ln = 0.5µm, Lp = 0.5µm). From Figures 4–7 and 4–8, it appears that the gain and the bandwidth do not change much while

54 Chapter 4

Figure 4–3: Bandwidth vs Vg. ♦ : VoQ = 1.2V, Wn = 20µm, Wp = 40µm, Ln = 0.5µm, Lp = 0.5µm. 2 : VoQ = 0.6V, Wn = 40µm, Wp = 20µm, Ln = 0.5µm, Lp = 0.5µm. ∆ : VoQ = 0.9V, Wn = 20µm, Wp = 20µm, Ln = 0.5µm, Lp = 0.5µm.

Figure 4–4: Noise vs Vg. ♦ : VoQ = 1.2V, Wn = 20µm, Wp = 40µm, Ln = 0.5µm, Lp = 0.5µm. 2 : VoQ = 0.6V, Wn = 40µm, Wp = 20µm, Ln = 0.5µm, Lp = 0.5µm. ∆ : VoQ = 0.9V, Wn = 20µm, Wp = 20µm, Ln = 0.5µm, Lp = 0.5µm.

55 Chapter 4

Figure 4–5: Distortion vs Vg. ♦ : VoQ = 1.2V, Wn = 20µm, Wp = 40µm, Ln = 0.5µm, Lp = 0.5µm. 2 : VoQ = 0.6V, Wn = 40µm, Wp = 20µm, Ln = 0.5µm, Lp = 0.5µm. ∆ : VoQ = 0.9V, Wn = 20µm, Wp = 20µm, Ln = 0.5µm, Lp = 0.5µm.

Figure 4–6: Power vs Vg. ♦ : VoQ = 1.2V, Wn = 20µm, Wp = 40µm, Ln = 0.5µm, Lp = 0.5µm. 2 : VoQ = 0.6V, Wn = 40µm, Wp = 20µm, Ln = 0.5µm, Lp = 0.5µm. ∆ : VoQ = 0.9V, Wn = 20µm, Wp = 20µm, Ln = 0.5µm, Lp = 0.5µm.

56 Chapter 4

Figure 4–7: Gain vs VoQ. ♦ : Vg = 0.5V, Wn = 40µm, Wp = 40µm, Ln = 0.5µm, Lp = 0.5µm. 2 : Vg = 0.8V, Wn = 20µm, Wp = 20µm, Ln = 0.5µm, Lp = 0.5µm. ∆ : VoQ = 1.1V, Wn = 20µm, Wp = 60µm, Ln = 0.5µm, Lp = 0.5µm. the amplifier operates in the active region. However, when the amplifier crosses the triode-active region boundary, the gain will drop and the bandwidth will increase significantly. As for distortion displayed in Figure 4–10, the results captured by the

♦ line shows a perfect V-shape, centered at VDD/2. The other two lines show some ﬂuctuations, however, neglecting the values below 0.5 V and above 1.3 V, where the transistors go in a diﬀerent operating region. The the lowest SDR occurs when VoQ are at 0.7 V and 0.8 V, respectively. This is more pronounced in Figure 4–11, where

SDR vs VoQ is shown. Interestingly, these peaks are where the noise at its lowest, as shown in Figure 4–9. The power consumption goes up slowly as VoQ increases, as shown in Figure 4–12.

Performance measures versus the width of the bottom transistor Mn are plotted in Figures 4–13, 4–14, 4–15, 4–16, and 4–17. The ♦ line uses the set Vg = 0.5, VoQ =

0.9V, Wp = 50µm, Ln = 0.5µm, Lp = 0.5µm. The 2 line uses the set Vg =

57 Chapter 4

Figure 4–8: Bandwidth vs VoQ. ♦ : Vg = 0.5V, Wn = 40µm, Wp = 40µm, Ln = 0.5µm, Lp = 0.5µm. 2 : Vg = 0.8V, Wn = 20µm, Wp = 20µm, Ln = 0.5µm, Lp = 0.5µm. ∆ : VoQ = 1.1V, Wn = 20µm, Wp = 60µm, Ln = 0.5µm, Lp = 0.5µm.

Figure 4–9: Noise vs VoQ. ♦ : Vg = 0.5V, Wn = 40µm, Wp = 40µm, Ln = 0.5µm, Lp = 0.5µm. 2 : Vg = 0.8V, Wn = 20µm, Wp = 20µm, Ln = 0.5µm, Lp = 0.5µm. ∆ : VoQ = 1.1V, Wn = 20µm, Wp = 60µm, Ln = 0.5µm, Lp = 0.5µm.

58 Chapter 4

Figure 4–10: Distortion vs VoQ. ♦ : Vg = 0.5V, Wn = 40µm, Wp = 40µm, Ln = 0.5µm, Lp = 0.5µm. 2 : Vg = 0.8V, Wn = 20µm, Wp = 20µm, Ln = 0.5µm, Lp = 0.5µm. ∆ : VoQ = 1.1V, Wn = 20µm, Wp = 60µm, Ln = 0.5µm, Lp = 0.5µm.

Figure 4–11: SDR vs VoQ. ♦ : Vg = 0.5V, Wn = 40µm, Wp = 40µm, Ln = 0.5µm, Lp = 0.5µm. 2 : Vg = 0.8V, Wn = 20µm, Wp = 20µm, Ln = 0.5µm, Lp = 0.5µm. ∆ : VoQ = 1.1V, Wn = 20µm, Wp = 60µm, Ln = 0.5µm, Lp = 0.5µm.

59 Chapter 4

Figure 4–12: Power vs VoQ. ♦ : Vg = 0.5V, Wn = 40µm, Wp = 40µm, Ln = 0.5µm, Lp = 0.5µm. 2 : Vg = 0.8V, Wn = 20µm, Wp = 20µm, Ln = 0.5µm, Lp = 0.5µm. ∆ : VoQ = 1.1V, Wn = 20µm, Wp = 60µm, Ln = 0.5µm, Lp = 0.5µm.

0.7V, VoQ = 0.7V, Wp = 60µm, Ln = 0.5µm, Lp = 0.5µm. The ∆ line uses the set

Vg = 1.1V, VoQ = 0.6V, Wp = 30µm, Ln = 0.5µm, Lp = 0.5µm. We can see an increase of the gain as Wn increased in Figure 4–13. Same goes for the bandwidth and power in Figures 4–14 and 4–17, respectively. On the other hand, noise goes down as Wn is increased as shown in Figure 4–15. Finally, distortion results shown in

Figure 4–16 show consistency with Equation 2.6. As Wn increases, the gate voltage of the top transistor Mp will change, and hence, the ideal mid point voltage for VD−middle changes. Hence, the distortion graph depends on whether this ideal voltage moves towards (2) or away (♦) from the given VoQ.

Note that the line with ∆ stops working when Wn becomes comparable to Wp because of the low width of Mp combined with a high current requirement due to the high Vg.

60 Chapter 4

Figure 4–13: Gain vs Wn. ♦ : Vg = 0.5, VoQ = 0.9V, Wp = 50µm, Ln = 0.5µm, Lp = 0.5µm. 2 : Vg = 0.7V, VoQ = 0.7V, Wp = 60µm, Ln = 0.5µm, Lp = 0.5µm. ∆ : Vg = 1.1V, VoQ = 0.6V, Wp = 30µm, Ln = 0.5µm, Lp = 0.5µm.

Figure 4–14: Bandwidth vs Wn. ♦ : Vg = 0.5, VoQ = 0.9V, Wp = 50µm, Ln = 0.5µm, Lp = 0.5µm. 2 : Vg = 0.7V, VoQ = 0.7V, Wp = 60µm, Ln = 0.5µm, Lp = 0.5µm. ∆ : Vg = 1.1V, VoQ = 0.6V, Wp = 30µm, Ln = 0.5µm, Lp = 0.5µm.

61 Chapter 4

Figure 4–15: Noise vs Wn. ♦ : Vg = 0.5, VoQ = 0.9V, Wp = 50µm, Ln = 0.5µm, Lp = 0.5µm. 2 : Vg = 0.7V, VoQ = 0.7V, Wp = 60µm, Ln = 0.5µm, Lp = 0.5µm. ∆ : Vg = 1.1V, VoQ = 0.6V, Wp = 30µm, Ln = 0.5µm, Lp = 0.5µm.

Figure 4–16: Distortion vs Wn. ♦ : Vg = 0.5, VoQ = 0.9V, Wp = 50µm, Ln = 0.5µm, Lp = 0.5µm. 2 : Vg = 0.7V, VoQ = 0.7V, Wp = 60µm, Ln = 0.5µm, Lp = 0.5µm. ∆ : Vg = 1.1V, VoQ = 0.6V, Wp = 30µm, Ln = 0.5µm, Lp = 0.5µm.

62 Chapter 4

Figure 4–17: Power vs Wn. ♦ : Vg = 0.5, VoQ = 0.9V, Wp = 50µm, Ln = 0.5µm, Lp = 0.5µm. 2 : Vg = 0.7V, VoQ = 0.7V, Wp = 60µm, Ln = 0.5µm, Lp = 0.5µm. ∆ : Vg = 1.1V, VoQ = 0.6V, Wp = 30µm, Ln = 0.5µm, Lp = 0.5µm.

Performance measures versus the width of the top transistor Mp are plotted in the Figures 4–18, 4–19, 4–20, 4–21, and 4–22. The ♦ line uses the set Vg =

0.5, VoQ = 0.9V, Wn = 50µm, Ln = 0.5µm, Lp = 0.5µm. The 2 line uses the set Vg = 0.8V, VoQ = 0.7V, Wn = 20µm, Ln = 0.5µm, Lp = 0.5µm. The ∆ line uses the set Vg = 1.1V, VoQ = 0.6V, Wn = 30µm, Ln = 0.5µm, Lp = 0.5µm. In this case, it is important to discard the data of the first 1-2 points because the dependent current source is barely working for these points, resulting in misleading or contradictory graphs. In any case, the gain, bandwidth, and noise all drop off slowly as Wp increases as shown in Figures 4–18, 4–19 and 4–20, respectively. The distortion does not change much as shown in Figure 4–21 and the power dissipation stays constant as shown in Figure 4–22. Contrary to what we saw in the previous case, in these figures, we see that for some simulation sets, the amplifier starts to

63 Chapter 4

Figure 4–18: Gain vs Wp. ♦ : Vg = 0.5, VoQ = 0.9V, Wn = 50µm, Ln = 0.5µm, Lp = 0.5µm. 2 : Vg = 0.8V, VoQ = 0.7V, Wn = 20µm, Ln = 0.5µm, Lp = 0.5µm. ∆ : Vg = 1.1V, VoQ = 0.6V, Wn = 30µm, Ln = 0.5µm, Lp = 0.5µm.

work as Wp increases. This is because with low Wp, the top transistor is not able to provide the current required to track the voltage at VoQ. Table 4–1 provides a summary of the information collected after spanning the whole performance space. We present the results in the form of arrows, indicating the performance metric dependency. The dashes represent insigniﬁcant change (less than 10 percent). For instance, in the case of gain, we see that it will decrease when the voltage Vg is increased. Conversely, we see the decrease in bandwidth with increasing Vg. In one respect, this table summaries the sign of the derivatives of the performance metrics with respect to the control variables.

A sweep of the length Mn and Mp shows that further optimization can be achieved by changing them as shown in Table 4–1, however, this is seldom done

64 Chapter 4

Figure 4–19: Bandwidth vs Wp. ♦ : Vg = 0.5, VoQ = 0.9V, Wn = 50µm, Ln = 0.5µm, Lp = 0.5µm. 2 : Vg = 0.8V, VoQ = 0.7V, Wn = 20µm, Ln = 0.5µm, Lp = 0.5µm. ∆ : Vg = 1.1V, VoQ = 0.6V, Wn = 30µm, Ln = 0.5µm, Lp = 0.5µm.

Figure 4–20: Noise vs Wp. ♦ : Vg = 0.5, VoQ = 0.9V, Wn = 50µm, Ln = 0.5µm, Lp = 0.5µm. 2 : Vg = 0.8V, VoQ = 0.7V, Wn = 20µm, Ln = 0.5µm, Lp = 0.5µm. ∆ : Vg = 1.1V, VoQ = 0.6V, Wn = 30µm, Ln = 0.5µm, Lp = 0.5µm.

65 Chapter 4

Figure 4–21: Distortion vs Wp. ♦ : Vg = 0.5, VoQ = 0.9V, Wn = 50µm, Ln = 0.5µm, Lp = 0.5µm. 2 : Vg = 0.8V, VoQ = 0.7V, Wn = 20µm, Ln = 0.5µm, Lp = 0.5µm. ∆ : Vg = 1.1V, VoQ = 0.6V, Wn = 30µm, Ln = 0.5µm, Lp = 0.5µm.

Figure 4–22: Power vs Wp. ♦ : Vg = 0.5, VoQ = 0.9V, Wn = 50µm, Ln = 0.5µm, Lp = 0.5µm. 2 : Vg = 0.8V, VoQ = 0.7V, Wn = 20µm, Ln = 0.5µm, Lp = 0.5µm. ∆ : Vg = 1.1V, VoQ = 0.6V, Wn = 30µm, Ln = 0.5µm, Lp = 0.5µm.

66 Chapter 4

Performance Metrics Control Variables Gain BW Noise Distortion Power Vg ↓ ↑ ↓ ↓ ↑ VoQ ↑↓ ↓↑ ↑↓ ↓↑ ↑ Wn ↑ ↑ ↓ ↑ ↑ Wp ↓ ↓ ↓ − − Ln ↑ ↓ − ↑ ↓ Lp ↑ ↓ ↑ ↑ − Table 4–1: Trade-oﬀs for the CS Ampliﬁer.

Gain BW Noise Distortion Power CS Amplifier 89.2 V/V 3.72 MHz 2.44 mVrms 0.578 nV 0.134 mW CG Amplifier 66.8 V/V 657 MHz 1.41 mVrms 287 nV 0.0124 mW CD Amplifier 0.825 V/V 302 MHz 0.168 mVrms 6.8 nV 0.00864 mW DIFF Amplifier 182 V/V 508 kHz 3.65 mVrms 0.691 nV 0.119 mW Table 4–2: Performance results for CS, CG, CD and DIFF amplifiers in CMOSP18 technology in IC design. So for the rest of this work, we will consider transistor length as a constant. To close off this section, performance result of four basic amplifier topologies including performance result of a common-source amplifier in CMOSP18 technology is included in Table 4–2 for a randomly chosen set of control variables. This result gives the reader an idea on the performance of a common-source amplifier designed with VDD = 1.8 V in CMOSP18 technology.

4.2 Common-Gate Ampliﬁer

Consider a CG ampliﬁer in a master-slave conﬁguration as shown in Figure 4–23.

The control variables for this ampliﬁer are: the source voltage Vx, the gate voltage Vp, the drain voltage VoQ and the transistor widths Wp, Wn and Wp2. This results in 6 independent control variables without considering the length of the transistors. The

67 Chapter 4

Figure 4–23: Common-Gate amplifier in master-slave configuration. performance space can be explored by sweeping these 6 variables. The collected data is organized into an excel file, using the same approach as for the common-source amplifier. A summary of the relationship between design variables and performance measures can be found in Table 4–3. To close off this section, performance results of a common-gate amplifier in

CMOSP18 technology is included in Table 4–2 for a randomly chosen set of control variables. This result gives the reader an idea on the performance of a common-gate ampliﬁer designed with VDD = 1.8 V in CMOSP18 technology.

68 Chapter 4

Performance Metrics Control Variables Gain BW Noise Distortion Power Vx ↓ ↑ ↑ ↓ ↑ Vp ↑ ↓ ↑ ↓ ↓ VoQ − − ↑↓ ↓↑ − Wp − ↑ ↓ − ↑ Wn − ↓ ↓ ↓ − Wp2 − − − − − Table 4–3: Trade-oﬀs for the CG Ampliﬁer.

Gain BW Noise Distortion Power Performance 66.8 V/V 657 kHz 1.41 mVrms 0.287 µV 0.0124 mW Table 4–4: Performance results for Vx=1.3V VoQ=1.1V Vp=0.7V Wn3=40µm Wp3=20µm Wp2=40µm Amplitude=100µV.

4.3 Common-Drain Ampliﬁer

The master-slave conﬁguration for the common drain ampliﬁer is shown in Fig- ure 4–24. It is set up in much the same way as described in Section 3.2 of Chapter 3.

The control variables for this topology are : Vg, VoQ, Wn and Wn2. The relationship between the control variables and the performance measures are shown in Table 4–5.

To close off this section, performance results of a common-drain amplifier in CMOSP18 technology is included in Table 4–2 for a randomly chosen set of control variables. This result gives the reader an idea on the performance of a common-drain amplifier designed with VDD = 1.8 V in CMOSP18 technology.

Performance Metrics Control Variables Gain BW Noise Distortion Power Vg ↓ ↑ − − ↑ VoQ ↑ ↓ ↓ ↓↑ ↓ Wn − − ↓ − − Wn2 − − ↓ − − Table 4–5: Trade-oﬀs for the CD ampliﬁer.

69 Chapter 4

Figure 4–24: Common-Drain ampliﬁer in master-slave conﬁguration.

4.4 Diﬀerential Ampliﬁer

The master-slave conﬁguration for the DIFF ampliﬁer is shown in Figure 4–25.

The identiﬁed control variables are: Vgd, VoQ, Wg, Wd and Wn. The data gathered by sweeping the control variables are put into an excel ﬁle, and a summary of relationship between control variables and performance measures is shown in Table 4–6.

Performance Metrics Control Variables Gain BW Noise Distortion Power Vgd − − ↓ ↓ − VoQ ↑ ↓ ↑ ↓↑ ↓ Wg ↑ ↑ ↓ ↑ − Wd ↓ ↑ ↓ ↓ ↑ Wn − − ↓ ↓ − Table 4–6: Trade-oﬀs for the DIFF ampliﬁer.

70 Chapter 4

Figure 4–25: Differential amplifier in master-slave configuration.

71 Chapter 4

To close off this section, performance results of a differential amplifier in CMOSP18 technology is included in Table 4–2 for a randomly chosen set of control variables. This result gives the reader an idea on the performance of a differential amplifier designed with VDD = 1.8 V in CMOSP18 technology.

4.5 Summary

In this chapter, single-stage ampliﬁers were designed using the self-biasing current source in conjunction with master-slave conﬁguration explained in Chapter 3.

Four basic topologies were considered: Common-Source Amplifier, Common-Gate Amplifier, Common-Drain Amplifier and Differential Amplifier. Each amplifier has been designed using the self-biased current source and a master-slave configuration. In the case of a common-source amplifier, the relationship between the control variables and the performance measures were captured by various plots. For the other single-stage amplifiers, the relationship was summarized into a table in their re- spective sections. In all amplifier topologies, we observed a drop in gain when the gate-source voltage is increased. On the other hand, bandwidth has increased when the gate-source voltage was increased. As for the noise, increase in width resulted in decrease in noise. Distortion has been mostly dependent on the output node voltage, usually maximum when output DC voltage was VDD/2. A summary of performance results is included in Table 4–2. This summary provides an idea on the performance of different amplifier topologies in CMOSP18 technology.

72 Chapter 5

Multi-Stage Ampliﬁer Design

In this chapter, design strategies for multi-stage amplifiers will be introduced to overcome the excessive simulation time required on account of the increased number of control variables. Three methods will be looked at: Partial Space Exploration, Divide and Conquer, and Control Variable Reduction methods. These methods will be applied to the design of a cascaded amplifier, a two-stage op amp and a folded cascode amplifier. The extention of these methods to a fully-differential topology will also be discussed.

5.1 Design Heuristics

Searching the complete performance space is a little bit more complicated for a multi-stage amplifier than for a single-stage amplifier. Consider a cascade of a DIFF amplifier and CG amplifier of the last chapter. The cascaded amplifier will have 10 total number of independent control variables. (5 variables for DIFF amp and

6 variables for CG amp, minus 1 shared node). Spanning the whole performance space for this topology having 10 independent control variables is diﬃcult, even at a modest resolution level since resolution♯ ofcontrolvariables simulations are required. For

- 73 - Chapter 5 instance, if we assume we have 10 steps for each control variable, then we would have to make 1010 separate SPICE analysis. Using the simulations conditions described in Section 3.3 of Chapter 3, this would entail a total simulation time of 34722 days. Clearly, this is not a viable approach. Instead, we need to look for searching methods that are faster, albeit, somewhat less optimal.

5.1.1 Partial Space Exploration Approach

The ﬁrst method is to look at a snapshot of the performance space, rather than the entire performance space. This method requires an intial condition where all transistors are operating in their saturation region with reasonably large W/L aspect ratios. The behavior of the performance space will be captured in the snapshot even though the optimal solution may not be found in the selected sub-space. This can be done by sweeping one design variable while keeping the other variables constant. By focusing on a single variable at a time, the number of sweeps required is no longer exponentially dependent on the number of control variables. Instead, the number of simulation steps will be

♯simulation steps = resolution step × number of control variables (5.1)

Obviously, this method has to be restarted if the solution is not found in the selected sub-space. This solution was implemented in MATLAB to automate the partial space exploration process as much as possible. The interactive MATLAB program searches the voltage space ﬁrst progressively from the input node to the output node and then the width space for each transistor is explored. An initial condition is required to start the simulation, typically a very relaxed condition where all transistors are in

74 Chapter 5 saturation mode. Then, the performances from a sweep of a single control variable will be shown to the user, such that a decision can be made. Subsequently, this process repeats and the next one will follow until there is no more control variables left. This approach will be looked into more fully in the next section where it is applied to a real ampliﬁer problem. The exemplary MATLAB code is included in appendix B and the ﬂowchart of the algorithm is shown in Figure 5–1.

5.1.2 Divide and Conquer Approach

The second method is based on distributing the multi-stage ampliﬁer performance requirements across individual stages based on the following circuit observa- tions: Overall gain is the product of individual stage gains, overall 3-dB bandwidth is the smallest of any individual stage bandwidths, noise is based on the front-end stage behavior and distortion is based on the ﬁnal-stage behavior. Total power requirement is the sum of the power of individual stages. Using the divide and conquer approach, the total number of simulation steps required can be described as follows:

♯simulation steps = resolution♯ of control variables in 1st stage

+resolution♯ of control variables in 2nd stage (5.2)

In the case of the DIFF-CG cascade, assuming 10 simulations sweeps per control variable, we would require 104 sweeps for the DIFF amplifier and 105 for the CG amplifier for a total number of sweeps of 104 + 105, assuming the input and output node voltages are held at a fixed potential. This method assumes the stages do not significantly load one another; otherwise, any loss of performance will need to be

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Figure 5–1: Flowchart of the MATLAB partial space exploration program.

76 Chapter 5 compensated for by assigning a larger performance requirement. This method will be applied to the two-stage op amp in the following section.

5.1.3 Control Variable Reduction Approach

The third method that we explored is a method based on reducing the number of control variables in the design. This approach is based on a designer’s intuition and observation of circuit behavior. For instance, the input and the output DC levels to the amplifier should be the same, typically midway between the supplies, say (VDD-VSS)/2. This reduces the number of control variables by 2. Further reduction can be made by setting the transistor widths to either fixed dimensions, or in terms of one another. For example, we can attempt to equalize the current density in each transistor (i.e., ID/W). This has the net effect of reducing the number of width control variables to one per stage. For the folded cascode amplifier of Section 5.4, the total number of control vairables becomes four: 2 voltage variables

(Vx and Vp) and 2 device widths (W1 and W2 for each stage). A very reasonable number of design variables in which to explore its performance space. This method will be shown in more detail later on in this chapter.

5.2 Cascaded Ampliﬁer Conﬁguration

To illustrate the amplifier design methodology with a multi-stage amplifier, a DIFF and a CG amplifier are cascaded as shown in Figure 5–2. The ideal current sources are replaced by self-regulating current sources together with a master-slave arrangement as shown in Figure 5–3. This amplifier cascade contains the essential components of a folded-cascode amplifier with the only difference being the lack of a cascode transistor in the current source. The output node of the DIFF amplifier

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Figure 5–2: Cascaded ampliﬁer with ideal current sources. shares the same node as the source terminal of the CG ampliﬁer, hence the number of degrees of freedom is reduced by one. As discussed previously, the total number of independent control variables is 10 (6 for CG amp and 5 for DIFF Amp, minus 1 shared node). The initial condition to set all the transistors to operate in the saturation region is as follows: Vgd=0.9, Vx=1.5, Vp=1.0, VoQ=0.9, Wg=20µm, Wd=20µm,

Wn1=20µm, Wn2=20µm, Wp=20µm, Wp2=20µm. The input amplitude is chosen to be 10 µV to not saturate the output. 50 Ω source resistors Rs are placed at the output of the source terminals. The source resistors will remain the same for the other multi-stage ampliﬁers. In the simulation, the node voltages were swept from 0.4 V to 1.8 V with an increment of 0.1 V, while the width of the transistors was swept from 1 µm to 100 µm with an increment of 10 µm. The MATLAB program in Appendix B automates the partial space exploration process and it was executed for this ampliﬁer. Figure 5–4 shows the snapshots of performance space generated by

Cadence, processed and captured by Matlab. It shows the performance measures in

78 Chapter 5 Figure 5–3: Cascaded ampliﬁer in master-slave conﬁguration.

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Vgd vs Gain 80

Gain (dB) 40 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Vgd (V)

4 x 10 Vgd vs 3dB−Frequency 15

0 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Frequency (Hz) Vgd (V) Vgd vs RMS Noise 0.06

0.04

0.02

0 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Vgd (V) RMS Noise (Vrms) Vgd vs Distortion 0.03

0.02

0.01

Distortion (V) 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Vgd (V)

−4 x 10 Vgd vs Power 1.5

0.5

Power (W) 0 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Vgd (V)

Figure 5–4: MATLAB plots showing partial space results for Vgd.

Figure 5–5: MATLAB iteration prompt.

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Performance Metrics Control Variables Gain BW Noise Distortion Power Vgd − − ↓ ↓ − 1 Vx ↓ ↑ ↓ ↓↑ Vp ↑ ↓ ↓ ↑ ↓ VoQ ↑↓ ↓↑ ↑↓ ↓↑ − Wg ↑ ↑ ↓ ↑ − Wd ↓ ↑ ↓ ↓ ↑ Wn1 − − − − − Wn2 ↓ ↑ ↓ ↑ − Wp ↓ ↑ ↓ ↓ ↑ Wp2 − − − ↓ − Table 5–1: Trade-oﬀs for the cascaded ampliﬁer using partial space exploration method.

relation to Vgd of the cascaded amplifier. Note that Figure 5–4 does not include any data for Vgd above 1.5 V. This is where the tracking of self-biasing current sources have failed because they could not provide the current required by the bottom transistors. After the sweep, the desired Vgd value is asked for as shown in Figure 5–5 to begin a new sweep for the next control variable using this desirved Vgd value. This process is repeated until the partial space of each control variable has been generated. The performance space for this cascaded amplifier configuration is generated using the partial space exploration method and a summary of the performance trade- offs is shown in Table 5–1. The gain and bandwidth trade-off is clearly visible, while a decrease in noise is also visible for increasing bias voltages Vgd, Vx, and Vp or increasing width of transistors Wg, Wd, Wn2, and Wp. To close off this section, performance results for various multi-stage amplifiers including a DIFF-CG cascaded amplifier in CMOSP18 technology is included in Table 5–2 for a randomly chosen set of control variables. This result gives the reader

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Topology Gain BW Noise Distortion Power Cascaded Amp 3630 V/V 22.4 kHz 53.9 mVrms 67.3 nV 0.122 mW F C Amp 1250 V/V 131 kHz 9.37 mVrms 1.74 nV 0.244 mW FD − F C Amp 6060 V/V 61.4 kHz 51.9 mVrms 3.93 µV 7.26 mW Table 5–2: Performance results for Cascaded, Folded Cascode, and Fully Diﬀerential Folded Cascode ampliﬁers in CMOSP18 technology

Figure 5–6: 2-stage op-amp with ideal current sources.

an idea of the performance of a DIFF-CG cascaded ampliﬁer designed with VDD = 1.8 V in CMOSP18 technology.

5.3 Two-Stage Op Amp Conﬁguration

A two-stage operational amplifier is considered in this section. A simplified representation of the two-stage operational amplifier is shown in Figure 5–6 and the two-stage operational amplifier using servo-loop current sources in a master-slave configuration is shown in Figure 5–7. This amplifier topology has 8 control variables: Vgd, Vx, VoQ, Wg, Wd, Wp, Wn2, Wp2. The compensation capacitor CC and

82 Chapter 5 Figure 5–7: 2-stage op-amp in master-slave conﬁguration.

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the compensation resistor RC are also independent control variables in this topology. Their values will aﬀect pole-zero position of this circuit, hence bandwidth. If a ﬁne control of pole-zero position is desired, poles and zeroes of the circuit would be added as performance metrics and pole-zero simulation would have to be performed.

Desired pole-zero positioning can be achieved the same way as the other desired performance speciﬁcations are met, e.g. by ﬁltering and sorting for acceptable solution in Microsoft Excel. However, for the sake of simplicity, the compensation capacitor

CC and compensation resistor RC have been kept constant at 1 pF and 200 Ω for this topology. The divide-and-conquer approach is applied to reduce the simulation time.

A random set of design variables (Vgd = 0.9V, Vx = 0.5V, VoQ = 0.9V, Wd =

20 µm, Wn2 = 40 µm, Wp = 40 µm, Wg = 20 µm, Wp2 = 40 µm, with an input amplitude of 1 µV at Vin) have been selected, and the performance results using a traditional simulation approach (i.e. simulating both stages at the same time shown in Figure 5–6) and divide-and-conquer approach are shown in Table 5–3. Using the divide-and-conquer approach, each stage has been simulated on its own as shown in Figures 5–8 and 5–9 and the performance results have been stored for each stage. The overall gain is then obtained by multiplying the two DC gains from each stage, the overall bandwidth is obtained by taking the lower of the two bandwidths, the overall noise is obtained by multiplying the noise of the ﬁrst stage by the gain of the second stage, the overall distortion is obtained by taking the distortion from the second stage, and the overall power is obtained by adding the power consumption of both stages as shown in Figure 5–10.

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Figure 5–8: 1st stage simulation Figure 5–9: 2nd stage simulation setup. setup.

Figure 5–10: Combining data from both stages.

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Figure 5–11: Compensated 1st stage Figure 5–12: Compensated2nd stage simulation setup. simulation setup.

Figure 5–13: Combining compensated data from both stages.

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Performance Metrics Figure Methods Gain BW Noise Distortion Power (V/V) (Hz) (Vrms) (V) (W) Reference 5–6 Traditional 1.33e4 2.16e4 1.63e-1 3.20e-6 5.07e-4 5–8 Stage 1 1.25e2 1.55e7 3.67e-3 2.29e-9 2.49e-4 Uncompensated 5–9 Stage 2 1.16e2 9.4e5 1.6e-3 2.14e-10 2.6e-4 5–10 D&C 1.45e4 9.4e5 4.26e-1 2.14e-10 5.09e-4 5–11 Stage 1 1.25e2 2.09e4 1.53e-3 2.19e-9 2.49e-4 Compensated 5–12 Stage 2 1.16e2 9.4e5 1.60e-3 2.94e-6 2.6e-4 5–13 D&C 1.45e4 2.09e4 1.77e-1 2.94e-6 5.09e-4 Table 5–3: Performance comparison between divide and conquer approach and traditional simulation approach.

Comparing the results between the traditional simulation approach and cascaded results from the divide-and-conquer approach in Table 5–3, only the DC gain and the power consumption is correctly predicted by the Divide-and-Conquer (D&C) approach. This is because the bandwidth and noise are reduced signiﬁcantly due to

1 the Miller effect on the compensation capacitor CC . The distortion results is also inconsistent because the amplification of the signal amplitude by the first stage was not taken into account. A new set of data has been generated after the Miller effect on compensation capacitor is taken into account. A dummy load capacitor having a capacitance equivalent to the Miller effect capacitance on CC is placed at the output of the first stage as shown in Figure 5–11. Also, the input amplitude of the second stage has to be magnified by the gain of the first stage as shown in Figure 5–12. The overall gain is then obtained by multiplying the DC gains from each stage, the overall

1 For the two-stage op amp, the compensation capacitance CC is increased by the gain of the 2nd stage, hence, a signiﬁcant capacitive loading occurs at the output of the ﬁrst stage.

87 Chapter 5 bandwidth is obtained by taking the lower of the two bandwidths, the overall noise is obtained by multiplying the noise of the ﬁrst stage by the gain of the second stage, the overall distortion is obtained by taking the distortion from the second stage, and the overall power is obtained by adding the power consumption of both stages as shown in Figure 5–13. The lower three rows of Table 5–3 show the results of these procedures. Comparing these results with the traditional simulation approach, we see these results are almost identical, with less than 8% error. Results using several other randomly taken datasets support our assertion that the divide-and-conquer approach using compensation is very similar to the traditional simulation approach as shown in Table 5–4. The datasets used are :

(1) Vg = 0.7 V, Vmid = 0.6 V, VoQ = 0.7 V, Wn1 = 40 µm, Wn2 = 60 µm, Wp1 = 80

µm, Wp2 = 40 µm, Wp3 = 60 µm, Vin = 1 µ, RC =200 Ω, CC =1pF.

(2) Vg = 1.1 V, Vmid = 0.55 V, VoQ = 1.1 V, Wn1 = 40 µm, Wn2 = 60 µm, Wp1 =

80 µm, Wp2 = 60 µm, Wp3 = 80 µm, Vin = 1 µV, RC =200 Ω, CC =1pF.

(3) Vg = 1.0 V, Vmid = 0.45 V, VoQ = 0.8 V, Wn1 = 30 µm, Wn2 = 50 µm, Wp1 =

60 µm, Wp2 = 40 µm, Wp3 = 60 µm, Vin = 1 µV, RC =200 Ω, CC =1pF. Constructing a table for the trade-offs in this case is straight forward. It comes down to combining two tables together. For example, the performance behaviors of the first stage of the two-stage amplifier shown in Table 5–5 is generated by sweeping all of the design variables of the first stage, and the performance behaviors of the second stage of the two-stage amplifier shown in Table 5–6 is generated by sweeping all of the design variables in the second stage. Tables 5–5 and 5–6 are combined by taking the union of each row containing the same control variable and augmenting

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Performance Metrics Example Figures Methods Gain BW Noise Distortion Power (V/V) (Hz) (Vrms) (V) (W) 5–6 Traditional 7.85e3 1.67e5 8.41e-2 4.59-6 3.92e-3 5–11 Compensated 8.89e1 1.83e5 9.52e-4 9.41e-10 2.239e-3 Stage 1 (1) 5–12 Compensated 1.10e2 7.90e5 9.06e-4 4.77e-6 1.69e-3 Stage 2 5–13 Compensated 9.80e3 1.83e5 1.05e-1 4.77e-6 3.92e-3 D&C 5–6 Traditional 1.03e4 9.19e4 9.78e-2 1.25e-5 2.04e-3 5–11 Compensated 1.12e2 9.96e4 1.06e-3 2.02e-9 1.14e-3 Stage 1 (2) 5–12 Compensated 1.13e2 8.12e5 1.04e-3 1.21e-5 8.96e-4 Stage 2 5–13 (2) Compensated 1.26e4 9.96e4 1.19e-1 1.21e-5 2.04e-3 D&C 5–6 (3) Traditional 1.30e4 1.57e4 1.26e-1 2.82e-6 2.59e-4 5–11 Compensated 1.25e2 1.69e4 1.31e-3 2.57e-9 1.39e-4 Stage 1 (3) 5–12 Compensated 1.16e2 7.98e5 1.40e-3 3.17e-6 1.21e-4 Stage 2 5–13 (3) Compensated 1.45e4 1.69e4 1.52e-1 3.17e-6 2.60e-4 D&C Table 5–4: Performance comparison between compensated divide and conquer approach and traditional simulation approach.

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Performance Metrics Control Variables Gain BW Noise Distortion Power Vgd − − ↑ ↑ − Vx ↓ ↑ ↓ ↓↑ ↑ Wg ↑ ↑ ↓ ↑ − Wd ↓ ↑ ↓ ↓ ↑ Wp − − ↓ ↓ − Table 5–5: Trade-oﬀs for the 1st stage of the 2-stage operational ampliﬁer using divide and conquer method.

Performance Metrics Control Variables Gain BW Noise Distortion Power Vx ↓ ↑ ↓ ↑↓ ↑ VoQ ↑↓ ↓↑ ↑↓ ↓↑ ↑ Wn2 ↑ ↑ ↓ ↑ ↑ Wp2 ↓ ↓ ↓ − − Table 5–6: Trade-oﬀs for the 2nd stage of the 2-stage operational ampliﬁer using divide and conquer method.

the table with unique control variables, resulting in Table 5–7. Vx is the only control variable appearing in both tables, the rest of the table can be merged without any problem. Gain, bandwidth, noise and power behaviour for Vx is the same for both stages, but distortion points to the opposite directions. Since we know that distortion is dominated by the second stage, distortion behavior of the second stage is considered for the combined two-stage operational ampliﬁer as shown in Table 5–7.

5.4 Folded Cascode Op Amp Conﬁguration

A folded cascode amplifier with ideal current sources is shown in Figure 5–14 and Figure 5–15 shows a folded cascode amplifier using self-biased current sources in master-slave arrangement. Without reducing any control variables, this amplifier topology would have 11 control variables, which would take years of simulation time

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Performance Metrics Control Variables Gain BW Noise Distortion Power Vgd − − ↑ ↑ − Vx ↓ ↑ ↓ ↑↓ ↑ VoQ ↑↓ ↓↑ ↑↓ ↓↑ ↑ Wg ↑ ↑ ↓ ↑ − Wd ↓ ↑ ↓ ↓ ↑ Wp − − ↓ ↓ − Wn2 ↑ ↑ ↓ ↑ ↑ Wp2 ↓ ↓ ↓ − − Table 5–7: Trade-oﬀs for the 2-stage operational ampliﬁer using divide and conquer method.

Figure 5–14: Folded cascode ampliﬁer with ideal current sources.

91 Chapter 5 iue51:Fle acd mlfiri atrsaeconfigura master-slave in amplifier cascode Folded 5–15: Figure tion.

92 Chapter 5 to explore the entire performance space. In this case, we will make use of the control variable reduction method.

In Chapter 2, we established through Equation 2.6 that if Vgn = Vgp and Vtn =

Vtp, the distortion is at minimum when VoQ is at 0.9 V. We also want to keep VoQ at VDD/2 for a maximum output swing. Since minimum distortion and maximum output swing is generally desired, there is no need to sweep VoQ, hence it will be kept at 0.9 V. If the op amp is to operated in feedback conﬁguration, the input DC voltages need to be at the same level as the ouput DC voltage, therefore, Vgd will be kept at 0.9 V as well. In addition, Vbot biases the cascode transistor, therefore, it will be kept at 0.45 V, half way from VoQ to VSS. The width variables (2 × Wd,

2 × Wg, Wn1 for the ﬁrst stage, Wp2, Wp, Wn2, Wn3 for the second stage) can be reduced to one per each stage (W1 and W2) by making the current density equal for all transistors in the stage. Subsequently, the total number of control vairables becomes four: 2 voltage variables (Vx and Vp) and 2 device widths (W1 and W2 for each stage). A summary of all the design variables is listed in Table 5–8.

Sweeping through the reduced control variables set can be done in a shorter time, and the results are organized in Table 5–9. To close oﬀ this section, performance results of a folded cascode ampliﬁer in

CMOSP18 technology is included in Table 5–2 for a randomly chosen set of control variables. This result gives the reader an idea on the performance of a folded cascode ampliﬁer designed with VDD = 1.8 V in CMOSP18 technology.

1 Depends on the power of the stage 1 and 2. Decreases the power of 1st stage, increases the power of the 2nd stage.

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Initial Control Variables New Control Variable Reason Vx Vx Vp Vp 2 × Wd (Wda + Wdb) 2 × Wg (Wga + Wgb) W1 One width variable per stage Wn1 Wp Wp2 Wn2 W2 One width variable per stage Wn3 VoQ 0.9 V for minimum distortion and maximum output swing Vgd 0.9 V need to be same as VoQ for feedback conﬁguration Vbot 0.45 V half way from VoQ and VSS Table 5–8: Control variable reduction method.

Performance Metrics Control Variables Gain BW Noise Distortion Power 1 Vx ↓ ↑ ↓ ↓↑ Vp ↑ ↓ ↓ ↑ ↓ W1 ↑ ↓ ↓ ↑ ↑ W2 ↓ ↑ ↓ ↓ − Table 5–9: Trade-oﬀs for the folded cascode ampliﬁer using control variable reduction method.

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Figure 5–16: Fully-diﬀerential ampliﬁer.

5.5 Fully-Diﬀerential Design

Fully-differential amplifiers generally refer to amplifiers with differential inputs and differential outputs as shown in Figure 5–16. This topology has the added benefits of canceling common mode signals, canceling of even-order harmonics and an increased output signal swing. On the other hand, the common-mode output voltages move to either the high or low end if they are left uncontrolled. Therefore, a fully- differential amplifier topology requires a common-mode feedback circuitry to stabilize the output nodes. The design space exploration of fully-differential amplifiers in this section was performed without a common-mode feedback circuit because the servo-loop current sources and master-slave configuration bias the DC node voltages. The final IC realization would require a common-mode feedback circuit for stable operation. Figure 5–17 shows a fully-differential implementation of a two-stage op amp.

The diode connected transistors Mda and Mdb in the single-ended two-stage op amp are now acting as the self-biased current source, while the rest of the circuit stays the same. This topology requires 1 additional servo-loop feedback biasing op amp to bias the previously active-loaded bottom transistors Mda and Mdb, but does not require an additional control variable because the the top and the bottom transistors of the

95 Chapter 5 iue51:Flydffrniltosaeo m nmaster-sla in amp op two-stage Fully-differential 5–17: Figure econfiguration. ve

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Performance Metrics Control Variables Gain BW Noise Distortion Power Vgd ↑ ↓ ↑ ↑ ↓ Vx ↑ ↓ ↑ ↑↓ − Wg ↑ ↑ ↓ ↑ ↑ Wd ↓ ↑ ↓ ↓ ↑ Wp ↓ ↑ ↓ ↓ ↑ Table 5–10: Trade-offs for the 1st stage of the fully-differential two-stage operational amplifier using divide and conquer method.

1st stage will adjust themselves to set the biasing voltage Vx as shown in Figure 5–17. The performance space can be generated using the divide-and-conquer approach.

Using the divide-and-conquer approach, fully-diﬀerential two-stage op amp was broken into 2 stages. The performance of the ﬁrst stage was investigated by sweeping through the control variables. These results are summarized in Table 5–10.

Unlike the single-ended counterpart, Vgd has a major effect on gain, bandwidth and power. This is due to the removal of the diode connection associated with transistors Mda and Mdb. The Vx acts in the opposite way than its single ended counterparts in terms of gain and bandwidth. In fact, the removal of the diode connection completely changes the behavior of the performance measures against the same control variables. However, the width Wg and Wd have the same trade-offs as its single-ended counterpart; Wp now also has an influence on the gain, bandwidth and power, unlike the single-ended case. The second stage generates the same table as in the single-ended case shown in

Table 5–6. The final table is obtained by merging the two tables together. Table 5–11 contains the control variables from both the first and second stage of the differential two-stage op amp. Again, Vx is the only control variable appearing in both Tables 5–

10 and 5–6. Increasing Vx increases the gain of the ﬁrst stage, but decreases the gain

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Performance Metrics Control Variables Gain BW Noise Distortion Power Vgd ↑ ↓ ↑ ↑ ↓ 1 2 Vx ↑ ↑↓ ↑ VoQ ↑↓ ↓↑ ↑↓ ↓↑ ↑ Wg ↑ ↑ ↓ ↑ ↑ Wd ↓ ↑ ↓ ↓ ↑ Wp ↓ ↑ ↓ ↓ ↑ Wn2 ↑ ↑ ↓ ↑ ↑ Wp2 ↓ ↓ ↓ − − Table 5–11: Trade-offs of the fully-differential two-stage operational amplifier using divide and conquer method. of the second stage. It also decreases the bandwidth of the first stage, while increasing the bandwidth of the second stage. Noise behavior is dominated by the first stage, therefore, it will increase, while distortion behavior is dominated by the second stage.

Power increases uniformly with increasing Vx as shown in Table 5–11. Fully-differential two-stage op amp design proved that the design by degrees of freedom strategy works for fully-differential amplifiers as well. It is easily extended to any other fully-differential topology by using any of the three design heuristics described earlier. For example, a fully-differential folded cascode using servo-loop feedback biasing in master-slave configuration is shown in Figure 5–18. The control variables are identical to its single-ended counterpart of Section 5.4 and by using any of the three design methods, the performance space can be obtained and can be organized into a library for future design specifications. For instance, we made

1 Increases the gain of the ﬁrst stage, decreases the gain of the second stage 2 Decreases the bandwidth of the ﬁrst stage, increases the bandwidth of the second stage

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Performance Metrics Control Variables Gain BW Noise Distortion Power 1 Vx ↑ ↑ ↓ ↑ Vp ↑ ↓ ↓ ↑ ↓ W1 − − ↓ ↓ ↑ W2 − ↑ ↓ ↓ − Table 5–12: Trade-offs for the fully-differential folded cascode amplifier using control variable reduction method. use of the control variable reduction method and the performance dependencies are listed in Table 5–12 using the same variable equivalences listed in Table 5–8. To close off this section, performance results of a differential folded cascode amplifier in CMOSP18 technology is included in Table 5–2 for a randomly chosen set of control variables. This result gives the reader an idea on the performance of a differential folded cascode amplifier designed with VDD = 1.8 V in CMOSP18 technology.

5.6 Comparison of the three methods

Using the method of design by degrees of freedom, the whole performance space could be explored. The excessive simulation time using this method for a multi-stage amplifier design has been addressed through the use of partial space exploration approach, divide and conquer approach and control variable reduction approach. The cascaded amplifier in Section 5.2 has 10 different control variables. Using the traditional parametric sweep approach with 10 steps for each control variable, the performance space exploration will take 1010 separate SPICE analysis. On average,

1 Depends on the power of the stage 1 and 2. Decreases the power of 1st stage, increases the power of the 2nd stage.

99 Chapter 5 iue51:Flydffrnilfle acd mlfiri m in amplifier cascode folded Fully-differential 5–18: Figure se-lv configuration. aster-slave

100 Chapter 5 each SPICE simulation takes 0.3s, therefore, the whole space exploration would then take 1010 × 0.3s = 34722 days! However, using the partial space exploration method, only 10×10 separate SPICE analysis is required, thus, simulation would only take 30 seconds. This method only spans the space where the results are likely to be found, signiﬁcantly reducing the simulation time with the inputs from the user. Likewise, the two-stage op amp in Section 5.3 has 8 control variables. Using the traditional parametric sweep approach with 10 steps for each control variable, the performance space exploration will take 108 separate SPICE analysis. On average, each SPICE simulation takes 0.3s, therefore, the whole space exploration would then take 108 × 0.3s = 347 days for this topology. However, through the use of divide and conquer approach, only 105 + 104 separate SPICE analysis is required. The simulation time in this case would be 9.16 hours. Finally, the folded cascode ampliﬁer in Section 5.4 has 8 control variables. Using the traditional parametric sweep approach with 10 steps for each control variable, the performance space exploration will take 108 separate SPICE analysis. On average, each SPICE simulation takes 0.3s, therefore, the whole space exploration would then take 108 × 0.3s = 347 days for this topology. Control variable reduction method reduces the number of control variables to 4. The simulation time is then 104 × 0.3s

= 50 minutes. The three methods have their own advantages and weaknesses. When given a fairly easy speciﬁcations, the partial space exploration is the best method since it is the fastest method. If the designer has a lot of intuition and insight on the topology, control variable reduction method is best used to span the performance space without losing the space where the results are likely to be found. Finally,

101 Chapter 5 the divide and conquer approach is applicable to all multi-stage topologies, but this method takes the longest time to search the performance space.

5.7 Summary

In this chapter, design strategies for multi-stage amplifiers have been reviewed. Due to the increased number of control variables involved in the design process, three methods have been proposed to reduce the simulation time: partial space exploration, divide and conquer, and control variable reduction methods. The partial space exploration method sweeps one variable at a time, reducing the number of simulation from resolution♯ of control variables to resolution × ♯ of control variables. The divide and conquer approach reduces the number of simulation from resolution♯ of control variables to resolution♯ of control variables in 1st stage + resolution♯ of control variables in 2nd stage by splitting the two stages. The control variable reduction method reduces the total number of control variables by using designer’s experience and intuition to arrive at a manageable number of control variables. These three methods have been applied to the design of a cascaded amplifier, a two-stage op amp and a folded cascode amplifier, respectively. The extention of these methods to a fully-differential topology was also discussed.

102 Chapter 6

Design Veriﬁcation

This chapter discusses the implementation of the ampliﬁer circuits shown previously using discrete electronics. The transistors used in this implementaion are

2N7000 for the n-channel MOSFET, and ZVP3306A for the p-channel MOSFET both made by Zetex Semiconductors. The 2N7000 transistors have Vth ranging from 0.8 to 3 volts and ZVP3306A transistors have Vth ranging from -1.5 to -3.5 volts [26] [27]. In addition to these transistors, operational ampliﬁers LF357 [28] from National Semiconductor and TL084 [29] from Texas Instruments were used to implement the self-biased current source in each design. The supply voltages used for the operational ampliﬁers are +15 V for VDD and -15 V for VSS. The equipment used in the DC voltage generation is : Hewlett Packard E3630A Triple Output DC Power Supply. The AC signal was generated by Agilent 33220A

20 MHz Function / Arbitrary Waveform Generator. The measurements are taken through Agilent Inﬁniium 54830D MSO 600 MHz 4 GSa/s scope. The ampliﬁer gain was captured by dividing the output peak-to-peak amplitude by the input peak-to-peak amplitude. Bandwidth information was measured by increasing the input frequency until the gain dropped by 3 dB. The power consumption

- 103 - Chapter 6

Figure 6–1: Self-biasing current source for CS ampliﬁer. was computed by measuring the amount of output current from the power supply and multiplying this quantity by the supply level. The waveform was captured at 1

MSa/s from Agilent 54830D, and the samples were processed in MATLAB to yield the noise and distortion values in dBW. The MATLAB code for computing noise and distortion is available in Appendix C.

6.1 Self-Biased Current Source

The self-biasing current sources of Figure 6–1 have been implemented for vali- dation. The transistors are set up as in Figure 6–2 in order to verify the DC voltage tracking behavior of the self-biased current sources using two different operational amplifiers (LF357 and TL084). Two different op amps are used to see whether the op amp make a difference in tracking the DC voltage. The test has been conducted for two different supply levels: 1.2 V and 4 V for VDD and 0 V for VSS.

Figures 6–3 and 6–4 show the output voltage in relation to changing VoQ, for diﬀerent supply levels of 1.2 V and 4.0 V. Setting VDD at 1.2 V VDD, the voltage

104 Chapter 6

Figure 6–2: Self-biased current source implementation with discrete components.

tracking works up to VoQ = 0.8 V. Above this value, the top transistor Mp cannot provide the current that the bottom transistor requires because the top transistor enters its triode mode.

Similarly, setting VDD at 4 V, experimental results in Figure 6–4 shows that the tracking works well until the top transistor cannot supply the current needed by the bottom transistor. This occurs when VoQ reaches 3.4 V. As shown in Figures 6–3 and 6–4, the op amps LF357 and TL084 show no difference when used in a self-biased current source configuration. This is consistent with the simulation results from Section 3.3 where a high-performance fully complementary folded cascode and a simple differential amplifiers showed little difference in tracking the voltages. The experimental results also prove that care needs to be exercised when sweeping the node voltages, such that the top transistor can always provide the required current.

105 Chapter 6

Figure 6–3: Vout vs VoQ using LF357 and TL084 VDD=1.2 V.

Figure 6–4: Vout vs VoQ using LF357 and TL084 VDD=4.0 V.

106 Chapter 6

Figure 6–5: CS ampliﬁer schematic.

6.2 Common-Source Ampliﬁer

Common-source amplifier of Figure 6–5 was implemented with the discrete components described above, as shown in Figure 6–6. The results from discrete implementation will be compared to the IC CMOSP18 technology simulation. Although the difference in technology will results in different performance numbers, the behaviors of these performance measures with respect to each of the control variable should be similar regardless of the technology as it depends on the physics of MOS devices.

Table 6–1 and 6–2 show experimental results obtained by sweeping Vg for VDD =

4.0 V and 1.2 V, respectively. With increasing Vg, Table 6–1 and 6–2 show decrease in gain, increase in bandwidth. The decrease in noise and distortion is more pronounced in Table 6–1. The increase in power with respect to Vg is clearly visible in both cases.

107 Chapter 6

Figure 6–6: Common Source ampliﬁer implementation with discrete components.

Vg Gain Bandwidth Noise Distortion Power (V) (V/V) (MHz) (dBW) (dBW) (mW) 2.6 99 0.03 -48.52 -20.11 120 2.65 74.3 0.065 -48.69 -24.78 160 2.7 40.9 0.12 -51.3 -38.5 200 2.8 21.7 0.35 -53.24 -55.03 240 2.85 17 0.48 -54.7 -63.01 280 2.9 14 0.8 -55.1 -67.94 320 2.95 12 1.1 -55.67 -70.47 360 Table 6–1: Performance measures for changing Vg for VoQ=0.6 N=1 P=1 VDD=4V.

Vg Gain Bandwidth Noise Distortion Power (V) (V/V) (MHz) (dBW) (dBW) (mW) 2.8 3.4 1.2 -52.25 -48.66 108 2.85 3.3 1.5 -52.18 -47.36 120 2.9 3.2 1.8 -52.2 -51.4 144 2.95 3 2 -52.14 -47.86 156 3.0 2.7 2.3 -52.1 -47.94 168 3.05 2.6 2.4 -52.04 -46.81 180 Table 6–2: Performance measures for changing Vg for VoQ=0.6 N=1 P=1 VDD=1.2V.

108 Chapter 6

VoQ Gain Bandwidth Noise Distortion Power (V) (V/V) (MHz) (dBW) (dBW) (mW) 0.2 1.2 2.4 -52.67 -44.75 108 0.25 1.6 2.3 -53.03 -41.89 120 0.3 2 2.2 -53.73 -39.84 132 0.35 2.2 2.1 -53.47 -39.75 144 0.4 2.5 2.1 -53.28 -39.29 156 0.45 2.6 2.1 -52.84 -39.98 156 0.5 2.7 2 -52.62 -41.34 168 0.55 2.7 2 -53.68 -44.73 168 0.6 2.75 2.2 -54.19 -47.93 168 0.65 2.8 2.2 -53.29 -48.12 168 0.7 2.75 2.4 -53.24 -48.15 168 0.75 2.7 2.4 -52.97 -51.15 168 Table 6–3: Performance measures for changing VoQ for Vg=2.97 N=1 P=1 VDD=1.2V.

These results are consistent with the simulation results listed in Table 4–1 for the

CS ampliﬁer.

Node voltage VoQ was swept with the supply voltage VDD set at 4.0 V and the experimental results are plotted against the simulation results in CMOSP18 technology in Figures 6–7, 6–8, 6–9, 6–10 and 6–11. We see a very good agreement between experimental and simulated results for gain, bandwidth, noise and distortion with respect to increasing VoQ. The increase in power consumption is more visible from the simulation results in Figure 6–11. This could be attributed to the lack of precision in current measurements from the power supply (using a 4 V supply, 55 mA to 65 mA would show up as 60 mA) as the experimental results using VDD =

1.2 V in Table 6–3 show a clear increase in power with respect to increasing VoQ.

109 Chapter 6

Figure 6–7: Experimental and simulated gain vs VoQ.

Figure 6–8: Experimental and simulated bandwidth vs VoQ.

110 Chapter 6

Figure 6–9: Experimental and simulated noise vs VoQ.

Figure 6–10: Experimental and simulated distortion vs VoQ.

111 Chapter 6

Figure 6–11: Experimental and simulated power vs VoQ.

Figure 6–12: Schematic of stacked N-channel transistors in common-source ampliﬁer.

112 Chapter 6

Figure 6–13: Stacked N-channel transistors in common-source ampliﬁer implementation. N Gain Bandwidth Noise Distortion Power (V/V) (MHz) (dBW) (dBW) (mW) 1 57 0.14 -52.08 -36.27 240 2 22 0.8 -55.43 -64.46 480 3 18 1.1 -56.83 -66.92 680 Table 6–4: Performance measures for changing N for Vg=2.8 VoQ=0.5 P=1 VDD=4V.

In order to mimic an increase in width of the transistors, the transistors were stacked in parallel as shown in Figures 6–12. This was implemented on the bread- board by stacking 2N7000 transistors in parallel as shown in Figure 6–13. However, due to the nature of discrete components, the stacked transistors could be very different from each other. As mentionned earlier, the datasheet of the transistors [26] and [27] indicate that Vth ranges from 0.8 to 3 volts for N-channel transistors and -1.5 to -3.5 volts for P-channel transistors. The experimental results in this case should be interpreted carefully.

113 Chapter 6

N Gain Bandwidth Noise Distortion Power (V/V) (MHz) (dBW) (dBW) (mW) 1 3.8 1.4 -53.96 -38.92 108 2 3.5 2 -55.56 -39.93 216 3 4 1.8 -55.12 -37.42 228 Table 6–5: Performance measures for changing N for Vg=2.8 VoQ=0.5 P=1 VDD=1.2V.

P Gain Bandwidth Noise Distortion Power (V/V) (MHz) (dBW) (dBW) (mW) 1 57 0.14 -52.08 -36.27 240 2 130 0.055 -40.91 -19.26 240 3 52 0.11 -51.13 -40.53 240 Table 6–6: Performance measures for changing P for Vg=2.8 VoQ=0.7 N=1 VDD=4V.

Tables 6–4 and 6–5 show the changing performance results with respect to stacking N-channel transistors Mn in parallel for VDD = 4.0 V and 1.2 V, respectively. Since stacking the N-channel transistor would require a higher current through the top transistor Mp, only up to three N-channel transistors were stacked such that the top transistor Mp does not burn out. The experimental results in Table 6–5 show an increase in gain and bandwidth, decrease in noise, increase in distortion and power consumption when the width of Mn effectively increased. These results are consistent with the simulation results shown in Table 4–1. The results in Table 6–4 shows a drop off in gain as more N-channel transistors are stacked. This might be because the threshold voltage of the stacked transistor was quite different from each other. The other performance behaviours from Table 6–4 are consistent with the simulated results in Table 4–1. Likewise, Tables 6–6 and 6–7 show experimental results when the top transistor

Mp in Figure 6–6 are stacked in parallel for VDD = 4.0 V and 1.2 V, respectively.

114 Chapter 6

P Gain Bandwidth Noise Distortion Power (V/V) (MHz) (dBW) (dBW) (mW) 1 2.8 2.2 -56.08 -61.26 156 2 2.9 2 -56.35 -63.19 156 3 3.2 1.8 -54.37 -60.03 156 Table 6–7: Performance measures for changing P for Vg=2.8 VoQ=0.7 N=1 VDD=1.2V.

The decrease in bandwidth and power consumption are in line with the simulation results in Table 4–1. However, gain, noise and distortion results from experiment were inconclusive.

6.3 Two-Stage Ampliﬁer

A Two-Stage ampliﬁer of Figure 6–14 was implemented with the discrete components as shown in Figure 6–15. The input diﬀerential voltage was generated by using two Agilent 33220A Function / Arbitrary Waveform Generators with 180 degrees of phase shift from each other, as shown in Figure 6–16. Since the Agilent 33220A has a minimum input amplitude of 10 mV, a gain of 100 V/V is the realistic maximum gain that can be measured. If the gain is higher than that, most of the output voltage will be clipped and distorted. At the same time, the drain voltage of the transistors

Md needs to be at around 2.8 V to overcome the Vth of the second stage. Hence, two diﬀerent supply voltage levels are used in this design. The VDD supply voltage of the ﬁrst stage has been set to 7 V, whereas, the second stage has 3 V VDD supply voltage levels with VSS tied to ground in both cases. The compensation capacitor

CC of 47 pF and the compensation resistor RC of 1 kΩ were used in this setup. Figures 6–17, 6–18, 6–19, 6–20 and 6–21 show a comparison of performance behaviors between experimental results and IC simulation in CMOSP18 with respect

115 Chapter 6 iue61:2Saeo-m nmse-lv conﬁguration. master-slave in op-amp 2-Stage 6–14: Figure

116 Chapter 6

Figure 6–15: Two-Stage ampliﬁer implementation with discrete components.

Figure 6–16: Diﬀerential signal generation setup.

117 Chapter 6

Figure 6–17: Experimental and simulated gain vs VoQ.

to increasing VoQ. These ﬁgures show that the behaviors of the performance results are in agreement for all ﬁve performance measures.

Table 6–8 shows the performance measures in relation to increasing Vgd. With respect to increasing Vgd, simulation results for two-stage op amp show a slight increase gain and a slight decrease in bandwidth, small enough to be ignored in the summarized results in Table 5–7. However, experimental results show that gain increased and bandwidth decreased signiﬁcantly. This might be because we were limited to such a small gain for the experimental results, whereas, the gain in the simulation was close to 10000 V/V. Noise, distortion and power consumption results show consistency with simulated results as noise and distortion increased, while power consumption stayed constant with respect to increasing Vgd. Figures 6–22, 6–23, 6–24, 6–25 and 6–26 show a comparison of performance behaviors between experimental results and IC simulation in CMOSP18 with respect

118 Chapter 6

Figure 6–18: Experimental and simulated bandwidth vs VoQ.

Figure 6–19: Experimental and simulated noise vs VoQ.

119 Chapter 6

Figure 6–20: Experimental and simulated distortion vs VoQ.

Figure 6–21: Experimental and simulated power vs VoQ.

120 Chapter 6

Vgd Gain Bandwidth Noise Distortion Power (V) (V/V) (MHz) (dBW) (dBW) (mW) 0 5.2 5 -49.78 -54.88 700 0.2 6.8 4.6 -50.05 -64.39 700 0.4 8 4.2 -49.53 -63.52 700 0.6 9.2 4.1 -48.56 -55.55 700 0.8 11.2 3.8 -48.86 -52.17 700 1.0 12 3.6 -48.58 -51.22 700 1.2 14.4 3.4 -45.08 -48.15 700 1.4 16 3.2 -44.83 -45.93 700 Table 6–8: Performance measures for changing Vgd for VoQ=1.5 Vmid=2.825 Md=1 Mg=1 Mp=1 Mp2=1 Mn2=1.

Md Gain Bandwidth Noise Distortion Power (V/V) (MHz) (dBW) (dBW) (mW) 1 14 3.5 -46.47 -62.73 700 2 48 0.4 -40.38 -32.33 1050 3 76 0.15 -40.07 -31.82 1290 Table 6–9: Performance measures for changing Md for Vgd=1 VoQ=1.5 Vmid=2.825 Mg=1 Mp=1 Mp2=1 Mn2=1.

to increasing VoQ. In this case, both experimental and simulation in CMOSP18 technology results show consistency with each other, with the exception of noise.

Table 6–9 shows the performance measures in relation to stacking transistor Md. Simulation predicts that gain, noise, distortion will go down, whereas bandwidth and power consumption will go up. The experimental data shows a huge boost in gain, and a decrease in bandwidth, while increased noise, bandwidth, and power consump- tions are observed. The diﬀerence in simulation and experimental results could be attributed to the wide diﬀerence of Vth in each discrete transistor, as mentionned in the previous section.

Table 6–10 shows the performance measures in relation to stacking transistor

Mg. In this case, the increase in bandwidth, decrease in noise and constant power

121 Chapter 6

Figure 6–22: Experimental and simulated gain vs Vx.

Figure 6–23: Experimental and simulated bandwidth vs Vx.

122 Chapter 6

Figure 6–24: Experimental and simulated noise vs Vx.

Figure 6–25: Experimental and simulated distortion vs Vx.

123 Chapter 6

Figure 6–26: Experimental and simulated power vs Vx.

Mg Gain Bandwidth Noise Distortion Power (V/V) (MHz) (dBW) (dBW) (mW) 1 14 3.5 -46.47 -62.73 700 2 8.8 4.2 -52.23 -65.5 700 3 8 4.5 -50.62 -67.76 700 Table 6–10: Performance measures for changing Mg for Vgd=1 VoQ=1.5 Vmid=2.825 Md=1 Mp=1 Mp2=1 Mn2=1. consumption are in agreement with the simulated results. However, gain and distortion should’ve increased according to the simulation whereas, the experimental data show a decline in both.

Table 6–11 shows the performance measures in relation to stacking transistor

Mp. The movements in performance measures are consistent with the simulation, as gain, bandwidth did not change, while both noise and distortion went down. Power consumption also stayed constant as predicted.

124 Chapter 6

Mp Gain Bandwidth Noise Distortion Power (V/V) (MHz) (dBW) (dBW) (mW) 1 14 3.5 -46.47 -62.73 700 2 12 3.8 -46.60 -71.35 700 3 12 3.8 -48.39 -69.91 700 Table 6–11: Performance measures for changing Mp for Vgd=1 VoQ=1.5 Vmid=2.825 Mg=1 Md=1 Mp2=1 Mn2=1.

Mn2 Gain Bandwidth Noise Distortion Power (V/V) (MHz) (dBW) (dBW) (mW) 1 14 3.5 -46.47 -62.73 700 2 8.8 4.3 -48.31 -72.21 910 3 7.6 4.8 -40.23 -70.19 1120 Table 6–12: Performance measures for changing Mn2 for Vgd=1 VoQ=1.5 Vmid=2.825 Mg=1 Mp=1 Mp2=1 Md=1.

Table 6–12 shows the performance measures in relation to stacking transistor

Mn2. In this case, gain moved in the opposite direction from the simulated behaviour, but bandwidth increased as expected. Noise and distortion give an inconclusive data as they decreased with 2 Mn2 but then increased with 3 Mn2 transistors. Power consumption is in line with simulation as it increased with more transistors in parallel.

Finally, Table 6–13 shows the performance measures in relation to stacking transistor Mp2. In simulation, gain, bandwidth, and noise decrease is seen while distortion and power consumption remained constant. The experimental data show that there is a huge boost in gain, which contradicts the simulation. Noise and distortion behaviour from the experimental results are also contradicting the simulated behaviour.

125 Chapter 6

Mp2 Gain Bandwidth Noise Distortion Power (V/V) (MHz) (dBW) (dBW) (mW) 1 14 3.5 -46.47 -62.73 700 2 48 0.8 -46.1 -60.49 700 3 65 0.22 -43.67 -54.83 700 Table 6–13: Performance measures for changing Mp2 for Vgd=1 VoQ=1.5 Vmid=2.825 Mg=1 Mp=1 Md=1 Mn2=1.

6.4 Summary

In this chapter, circuits shown in previous chapters were implemented using discrete components. Self-biased current source was tested using two different supply voltages, and the DC voltage tracking operation was validated using the operational amplifiers LF357 and TL084, and the transistors 2N7000 and ZVP3630A. A common-source amplifier and a two-stage amplifier were built using the above operational amplifiers and discrete transistors as self-biased current source in master-slave configuration. The voltage sweep show consistency between the experimental results and the simulation results from CMOSP18 IC technology. However, stacking the transistors in order to mimic the increase in width sometimes gave random results which were not useful to validate the effect of increasing transistor width on performance measures. We believe that the difference in simulated results and experimental results in this case came from the fact that each discrete transistor has a different

Vth, ranging from 0.8 to 3 volts for 2N7000 and -1.5 to -3.5 volts for ZVP3630A transistors.

126 Chapter 7

Conclusion

The evolution of CMOS technology has created a need for a systematic design methodologies in IC design. Chapter 2 presented the background on analog IC design, amplifiers and its performance metrics. We also explored different strategies used in today’s analog IC design world such as gm/ID method and Geometric Programming method, where it was concluded that the current methods are not optimized in the ever shrinking CMOS technology. A new design strategy was outlined and explored in Chapter 3. Namely, the choice of independent control variables, self-biasing current source, master-slave configuration techniques have been explored to allow creation of the entire performance space of an amplifier. The proposed design strategy was first applied to basic amplifiers taking advantage of independent control variables via self-biasing current source in master- slave configuration and the results for four single-stage amplifiers: Common-Source, Common-Gate, Common-Drain, and Differential amplifiers were described Chap- ter 4. This chapter also contains information on filtering the existing data to design amplifiers that meet new specifications.

- 127 - Chapter 7

The number of simulation explosion problem for multi-stage amplifiers was discussed in Chapter 5, and three solutions have been proposed: Partial Space Ex- ploration, Divide and Conquer and Control Variable Reduction methods. These methods have been used to design the folded cascode, cascaded and 2-stage op-amp as examples. Extension of the design strategy to fully differential amplifiers was also outlined. These methods were investigated through extensive simulations in

CMOSP18 technology. Design verification was demonstrated in Chapter 6 using a discrete implementation of a common-source amplifier and a two-stage op-amp. Simulation and experimental results are shown here that verify the validity of proposed design strategy. In this thesis, a fast, economical and systematic way to design any amplifier topology is proposed. This work can consider any performance measure. In order to expand and enhance performance space exploration method, future work needs to be carried out to see if this method is applicable to other analog building blocks, such as, Analog-to-digital converters, digital-to-analog converters, phase-locked loops, filters, et cetera.

128 Appendix A

OCEAN code : Control Variable Sweep

; ; This ocean script performs a parametric analysis on a circuit but, instead of saving all the data until the end, ; it saves it on the fly in an excel compatible file. This makes it a) use less disc since it deletes results it ; no longer uses and b) be more recoverable from crashes, since at any point in time the Excel file is still ; usable ; ; To use it for your own circuits, replace the parameters at the top with the correct paths and analyses for your ; design, and change the paramList variable to reflect the parameters you wish to sweep. ; ; simulator( ’spectre )

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;; REPLACE THE FOLLOWING WITH YOUR OWN PARAMETERS ;;;;;;;;; ;;;;;;;;; You can generate these parameters from the Analog environment ;;;;;;;;; ;;;;;;;;; by pressing "Save Script" when it’s set up the way you want and ;;;;;;;;; ;;;;;;;;; copying the first few lines. ;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ocnWaveformTool( ’wavescan ) simulator( ’spectre ) design( "/home/eyoo/simulation/SingleTRn/spectre/schematic/netlist/netlist") resultsDir( "/home/eyoo/simulation/SingleTRn/spectre/schematic" ) modelFile( ’("/CMC/kits/cmosp18.5.2/models/spectre/cor_std_mos.scs" "tt") ) analysis(’ac ?start "1" ?stop "1G" ) analysis(’tran ?stop "10m" ) analysis(’noise ?start "1" ?stop "1G" ?p "/Vout" ?n "/VSS" ?oprobe "" ?iprobe "/V4" ) analysis(’dc ?saveOppoint t ) desVar( "Wp3" 10u ) desVar( "Wn3" 10u ) desVar( "VoQ" 0.9 ) desVar( "Vg" 0.5 ) desVar( "L" 400n )

- 129 - desVar( "freqz" 1k ) desVar( "amp" 1u ) temp( 27 )

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;; END OF STUFF TO REPLACE ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;; CUSTOMIZATION ;;;;;;;;;;;; ;;;;;;;;;; The following can optionally be modified in order to ;;;;;;;;;;;; ;;;;;;;;;; customize the behaviour of the script, for instance ;;;;;;;;;;;; ;;;;;;;;;; what variables to sweep and what to do with the ;;;;;;;;;;;; ;;;;;;;;;; results. ;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; This is the file it will write the useful results to. You can change it to ; whatever you want. of = outfile( "./SingleTRVg.csv" "w" )

; These lists define the values to sweep the variables ; across. If you want to change the parametric sweep, change this. paramList = ’( ;("Vg" 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4) ;("VoQ" 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5) ;("Wn3" 5e-7 1e-6 5e-6 1e-5 5e-5 1e-4 2e-4) ("amp" 1e-6 5e-6 1e-5 5e-5 1e-4 5e-4 1e-3 5e-3 1e-2) ;("L" 5e-7 1e-6 5e-6 1e-5 5e-5 1e-4 2e-4) ) resultTypes = "Gain,Bandwidth,Noise,DC,S,H2,H3,H4,IDC"

; This governs what will happen at each data point in the simulation. Change it to ; do whatever you want, but I recommend retaining the "run()" in the first line. ; also you’ll want to make sure that the stuff you print out is in the same order ; as the resultTypes string above. procedure( runSim( ) printf("Running Sim\nPoints Remaining: %d\n",numPoints) numPoints = numPoints-1 run()

;valPrint(of VDC("/V_1")) ; V_1 ;valPrint(of VDC("/V_2")) ; V_2 ;valPrint(of VDC("/V_3")) ; V_3 ;valPrint(of VDC("/Vmid")) ; V_4 ;valPrint(of VDC("/Vout")) ; V_5 valPrint(of ymax(mag(VF("/Vout")))) ; GAIN valPrint(of bandwidth(VF("/Vout") 3 "low")) ; BW ;valPrint(of ymax(mag(VF("/Vmid")))) ; GAIN ;valPrint(of bandwidth(VF("/Vmid") 3 "low")) ; BW valPrint(of rmsNoise(1 1e+9)) ; NOISE let( (DFT_data) DFT_data = dft(VT("/Vout") 4m 9m 1024 "Rectangular" 1 dftCoherentGain("Rectangular",1)) foreach(var list(0 1000 2000 3000 4000) valPrint(of mag(value( DFT_data var ))) ) ) valPrint(of IDC("/V1/PLUS")) ; IDC

- 130 - fprintf(of "\n") drain(of) )

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;; END OF CUSTOMIZABLE OPTIONS ;;;;;;;; ;;;;;;;;;;;;;;;;; I wouldn’t recommend modifying anything below here ;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; numPoints = length(cdar(paramList)) foreach(E cdr(paramList) numPoints = numPoints*length(cdr( E )) ) printf("This sweep will cover %d points", numPoints) foreach(E paramList fprintf(of "%s," car(E)) ) fprintf(of "%s\n" resultTypes) drain(of)

; Prints out the given Value to the sink, followed by a comma. ; If the value is nil it prints out just a comma. procedure( valPrint(Sink Value) if( Value then fprintf(Sink "%e," Value) else fprintf(Sink ",") ) ) procedure( doSweep(L Values) if( L then foreach( Value cdar(L) desVar( caar(L) Value) doSweep(cdr(L) append(Values list(Value))) ) else foreach(V Values fprintf(of "%e," V) ) runSim( ) ) ) doSweep(paramList nil)

- 131 - Appendix B

MATLAB code : Partial Space Exploration

% % %*************************** % % % Load Ocean, Sweep Voltages % % %***************************

!exec tcsh !source /CMC/scripts/cadence2007a !mv .oceanrc initialocearnrc !mv step1oceanrc .oceanrc !ocean

% % % Read the data, Plot the perf vs Sweeped Voltages

Data1 = csvread(’dat1.csv’,1,0); Data2 = csvread(’dat2.csv’,1,0); Data3 = csvread(’dat3.csv’,1,0);

% plot data1,data2,data3

% Data1 Plot figure(); subplot(2,1,1); plot (Data1(:,1),db(Data1(:,5))); title (’Vin vs Gain’); xlabel (’Vin (V)’) ylabel (’Gain (dB)’) grid on; subplot(2,1,2); plot (Data1(:,1),(Data1(:,6))); title (’Vin vs 3dB-Frequency’); xlabel (’Vin (V)’) ylabel (’Frequency (Hz)’) grid on;

% Data2 Plot figure(); subplot(2,1,1);

- 132 - plot (Data2(:,1),db(Data2(:,5))); title (’Vmid vs Gain’); xlabel (’Vmid (V)’) ylabel (’Gain (dB)’) grid on; subplot(2,1,2); plot (Data2(:,1),(Data2(:,6))); title (’Vmid vs 3dB-Frequency’); xlabel (’Vmid (V)’) ylabel (’Frequency (Hz)’) grid on;

% Data2 Plot figure(); subplot(2,1,1); plot (Data3(:,1),db(Data3(:,5))); title (’Vout vs Gain’); xlabel (’Vout (V)’) ylabel (’Gain (dB)’) grid on; subplot(2,1,2); plot (Data3(:,1),(Data3(:,6))); title (’Vout vs 3dB-Frequency’); xlabel (’Vout (V)’) ylabel (’Frequency (Hz)’) grid on;

% % % Ask the user for inputs (voltages) then generate a script for that

Vin=input(’Give the new input for DC voltage of Vin: ’); Vout=input(’Give the new input for DC voltage of Vout: ’); Vmid=input(’Give the new input for DC voltage of Vmid: ’);

% Generate Script using the above values CSGenWn2(Vin,Vout,Vmid); CSGenWp2(Vin,Vout,Vmid);

% % % Load Ocean, Sweep Single TR Sizes

!mv .oceanrc step1oceanrc !mv step2oceanrc .oceanrc !ocean

% % % Read the data, Plot the perf vs Sweeped Voltages

Data4 = csvread(’dat4.csv’,1,0); Data5 = csvread(’dat5.csv’,1,0);

% plot data4,data5 % Data4 Plot figure(); subplot(2,1,1); plot (Data4(:,4),db(Data4(:,5))); title (’Wn2 vs Gain’); xlabel (’Wn2 (m)’) ylabel (’Gain (dB)’) grid on; subplot(2,1,2); plot (Data4(:,4),(Data4(:,6))); title (’Wn2 vs 3dB-Frequency’);

- 133 - xlabel (’Wn2 (m)’) ylabel (’Frequency (Hz)’) grid on;

% Data5 Plot figure(); subplot(2,1,1); plot (Data5(:,4),db(Data5(:,5))); title (’Wp2 vs Gain’); xlabel (’Wp2 (m)’) ylabel (’Gain (dB)’) grid on; subplot(2,1,2); plot (Data5(:,4),(Data5(:,6))); title (’Wp2 vs 3dB-Frequency’); xlabel (’Wp2 (m)’) ylabel (’Frequency (Hz)’) grid on;

% % % Ask the user for inputs (sizes)

Wn2=input(’Give the new input for the width of Wn2: ’); Wp2=input(’Give the new input for the width of Wp2: ’);

% % % Load Ocean, Sweep Differential TR CSGenWn1(Vin,Vout,Vmid,Wn2,Wp2); CSGenWp1(Vin,Vout,Vmid,Wn2,Wp2); CSGenWp3(Vin,Vout,Vmid,Wn2,Wp2);

!mv .oceanrc step2oceanrc !mv step3oceanrc .oceanrc !ocean

% % % Read Data

Data6 = csvread(’dat6.csv’,1,0); Data7 = csvread(’dat7.csv’,1,0); Data8 = csvread(’dat8.csv’,1,0);

% % % Plot

% Data6 Plot figure(); subplot(2,1,1); plot (Data6(:,4),db(Data6(:,5))); title (’Wn1 vs Gain’); xlabel (’Wn1 (m)’) ylabel (’Gain (dB)’) grid on; subplot(2,1,2); plot (Data6(:,4),(Data6(:,6))); title (’Wn1 vs 3dB-Frequency’); xlabel (’Wn1 (m)’) ylabel (’Frequency (Hz)’) grid on; % Data7 Plot figure(); subplot(2,1,1); plot (Data7(:,4),db(Data7(:,5))); title (’Wp1 vs Gain’);

- 134 - xlabel (’Wp1 (m)’) ylabel (’Gain (dB)’) grid on; subplot(2,1,2); plot (Data7(:,4),(Data7(:,6))); title (’Wp1 vs 3dB-Frequency’); xlabel (’Wp1 (m)’) ylabel (’Frequency (Hz)’) grid on; % Data8 Plot figure(); subplot(2,1,1); plot (Data8(:,4),db(Data8(:,5))); title (’Wp3 vs Gain’); xlabel (’Wp3 (m)’) ylabel (’Gain (dB)’) grid on; subplot(2,1,2); plot (Data8(:,4),(Data8(:,6))); title (’Wp3 vs 3dB-Frequency’); xlabel (’Wp3 (m)’) ylabel (’Frequency (Hz)’) grid on;

% New inputs Wn1=input(’Give the new input for the width of Wn1: ’); Wp1=input(’Give the new input for the width of Wp1: ’); Wp3=input(’Give the new input for the width of Wp3: ’);

% Generate new script <><> TODO CSGenRc(Vin,Vout,Vmid,Wn2,Wp2,Wn1,Wp1,Wp3); CSGenCc(Vin,Vout,Vmid,Wn2,Wp2,Wn1,Wp1,Wp3);

% Run Ocean using new script !mv .oceanrc step3oceanrc !mv step4oceanrc .oceanrc !ocean

% Take Data

Data9 = csvread(’dat9.csv’,1,0); Data10 = csvread(’dat10.csv’,1,0);

% Plot

% Data9 Plot figure(); subplot(2,1,1); plot (Data9(:,4),db(Data9(:,5))); title (’Rc vs Gain’); xlabel (’Rc (Ohm)’) ylabel (’Gain (dB)’) grid on; subplot(2,1,2); plot (Data9(:,4),(Data9(:,6))); title (’Rc vs 3dB-Frequency’); xlabel (’Rc (Ohm)’) ylabel (’Frequency (Hz)’) grid on;

- 135 - % Data10 Plot figure(); subplot(2,1,1); plot (Data10(:,4),db(Data10(:,5))); title (’Cc vs Gain’); xlabel (’Cc (F)’) ylabel (’Gain (dB)’) grid on; subplot(2,1,2); plot (Data10(:,4),(Data10(:,6))); title (’Cc vs 3dB-Frequency’); xlabel (’Cc (F)’) ylabel (’Frequency (Hz)’) grid on;

Rc=input(’Give the new input for the Compensation Resistor Rc (Ohm): ’); Cc=input(’Give the new input for the Compensation Capacitor Cc (F): ’);

% Generate new script <><> TODO CSGenF(Vin,Vout,Vmid,Wn2,Wp2,Wn1,Wp1,Wp3,Rc,Cc);

!mv .oceanrc step4oceanrc !mv step5oceanrc .oceanrc !ocean

Data11 = csvread(’dat11.csv’,1,0); fprintf (’Gain...Bw...etcetc’); fprintf = (’satisfied? yes or no’); % loop if no % out if yes

!mv .oceanrc step5oceanrc !mv initialoceanrc .oceanrc

- 136 - function CSGen1(V1,V2,V3,V4) fid=fopen(’Gen1.ocn’,’w’); fprintf(fid,’simulator( ’’spectre )\n’); fprintf(fid,’ocnWaveformTool( ’’wavescan )\n’); fprintf(fid,’simulator( ’’spectre )\n’); fprintf(fid,’design( "/home/eyoo/simulation/FoldedCascode_T/spectre/schematic/netlist/netlist")\n’); fprintf(fid,’resultsDir( "/home/eyoo/simulation/FoldedCascode_T/spectre/schematic" )\n’); fprintf(fid,’modelFile( \n’); fprintf(fid,’ ’’("/CMC/kits/cmosp18.5.2/models/spectre/cor_std_mos.scs" "tt")\n’); fprintf(fid,’)\n’); %analysis fprintf(fid,’analysis(’’ac ?start "1" ?stop "1G" )\n’); fprintf(fid,’analysis(’’tran ?stop "10m" )\n’); fprintf(fid,’analysis(’’noise ?start "1" ?stop "1G" ?p "/Vout"\n’); fprintf(fid,’ ?n "/VSS" ?oprobe "" ?iprobe "/V4" )\n’); fprintf(fid,’analysis(’’dc ?saveOppoint t )\n’); %design variables fprintf(fid,’desVar( "freqz" 1k )\n’); fprintf(fid,’desVar( "amp" 25u )\n’); fprintf(fid,’desVar( "Vx" 1 )\n’); fprintf(fid,’desVar( "Vp3" 0.4 )\n’); fprintf(fid,’desVar( "VoQ" 0.6 )\n’); fprintf(fid,’desVar( "Gn1_m" 0.8 )\n’); fprintf(fid,’desVar( "Wp3" 10u )\n’); fprintf(fid,’desVar( "Wp2" 10u )\n’); fprintf(fid,’desVar( "Wp1" 10u )\n’); fprintf(fid,’desVar( "Wn3" 10u )\n’); fprintf(fid,’desVar( "Wn2" 10u )\n’); fprintf(fid,’desVar( "Wn1" 10u )\n’); fprintf(fid,’desVar( "L" 500n )\n’); fprintf(fid,’desVar( "Lp3" 500n )\n’); fprintf(fid,’desVar( "Lp2" 500n )\n’); fprintf(fid,’desVar( "Lp1" 500n )\n’); fprintf(fid,’desVar( "Ln3" 500n )\n’); fprintf(fid,’desVar( "Ln2" 500n )\n’); fprintf(fid,’desVar( "Ln1" 500n )\n’); fprintf(fid,’temp( 27 ) \n’); fprintf(fid,’run()\n’); %Output File Name fprintf(fid,’of = outfile( "./aVp3Sweep2.csv" "w" )\n’); %Sweep list fprintf(fid,’paramList = ’’( ("Vx" 1.2)\n’); fprintf(fid,’("Vp3" 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.625 0.65 0.675 0.7 0.725 0.75 0.775 0.8 0.825 0.85 0.875 0.9 0.925 fprintf(fid,’ ("VoQ" 0.9)\n’); fprintf(fid,’ ("Gn1_m" 0.8)\n’); fprintf(fid,’ )\n’); %Results Type fprintf(fid,’resultTypes = "OvGain,OvBW,S1Gain,S1Bw,Noise,DC,S,H2,H3,H4,IDC"\n’); %Sweep process fprintf(fid,’procedure( runSim( )\n’); fprintf(fid,’ printf("Running Sim\nPoints Remaining: %%d\\n",numPoints)\n’); fprintf(fid,’ numPoints = numPoints-1\n’); fprintf(fid,’ run()\n’); %Results handler fprintf(fid,’ valPrint(of ymax(mag(VF("/Vout")))) ; GAIN\n’); fprintf(fid,’ valPrint(of bandwidth(VF("/Vout") 3 "low")) ; BW\n’); fprintf(fid,’ valPrint(of ymax(mag(VF("/Vc")))) ; GAIN\n’); fprintf(fid,’ valPrint(of bandwidth(VF("/Vc") 3 "low")) ; BW\n’);

- 137 - fprintf(fid,’ valPrint(of rmsNoise(1 1e+9)) ; NOISE\n’); fprintf(fid,’ let( (DFT_data)\n’); fprintf(fid,’DFT_data = dft(VT("/Vout") 4m 9m 1024 "Rectangular" 1 dftCoherentGain("Rectangular",1))\n’); fprintf(fid,’foreach(var list(0 1000 2000 3000 4000)\n’); fprintf(fid,’valPrint(of mag(value( DFT_data var )))\n’); fprintf(fid,’)\n’); fprintf(fid,’ )\n’); fprintf(fid,’ valPrint(of IDC("/V1/PLUS")) ; IDC \n’); fprintf(fid,’ fprintf(of "\\n")\n’); fprintf(fid,’ drain(of)\n’); fprintf(fid,’)\n’); %End of Customizable options fprintf(fid,’numPoints = length(cdar(paramList))\n’); fprintf(fid,’foreach(E cdr(paramList)\n’); fprintf(fid,’ numPoints = numPoints*length(cdr( E ))\n’); fprintf(fid,’)\n’); fprintf(fid,’printf("This sweep will cover %%d points", numPoints)\n’); fprintf(fid,’foreach(E paramList\n’); fprintf(fid,’ fprintf(of "%%s," car(E))\n’); fprintf(fid,’)\n’); fprintf(fid,’fprintf(of "%%s\\n" resultTypes)\n’); fprintf(fid,’drain(of)\n’); fprintf(fid,’procedure( valPrint(Sink Value)\n’); fprintf(fid,’ if( Value\n’); fprintf(fid,’ then fprintf(Sink "%%e," Value)\n’); fprintf(fid,’ else fprintf(Sink ",")\n’); fprintf(fid,’ )\n’); fprintf(fid,’)\n’); fprintf(fid,’procedure( doSweep(L Values)\n’); fprintf(fid,’ if( L\n’); fprintf(fid,’ then\n’); fprintf(fid,’ foreach( Value cdar(L)\n’); fprintf(fid,’ desVar( caar(L) Value)\n’); fprintf(fid,’ doSweep(cdr(L) append(Values list(Value)))\n’); fprintf(fid,’ )\n’); fprintf(fid,’ else\n’); fprintf(fid,’ foreach(V Values\n’); fprintf(fid,’ fprintf(of "%%e," V)\n’); fprintf(fid,’ )\n’); fprintf(fid,’ runSim( )\n’); fprintf(fid,’ )\n’); fprintf(fid,’)\n’); fprintf(fid,’doSweep(paramList nil)\n’); fprintf(fid,’\n’); fclose(fid);

- 138 - Appendix C

MATLAB code : Processing Waveform

clear all; load vg28voq310.csv; N=length(vg28voq310); Y=abs(fft(vg28voq310,N)); Power=Y.^2*2/(N*(N-1)); PSD=10*log10(Power); % plot(PSD);

Noise=0; Dist=0; for k=20:1:400 Noise = Noise+Power(k,2); end

for k=1:1:5 Dist=Dist+Power(3+2*k,2); end

NoisedB = 10*log10(Noise) DistdB = 10*log10(Dist) SignaldB = 10*log10(Power(3,2))

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