Corrected: Author correction
ARTICLE
https://doi.org/10.1038/s41467-019-13797-9 OPEN Is negative capacitance FET a steep-slope logic switch?
Wei Cao 1 & Kaustav Banerjee 1*
The negative-capacitance field-effect transistor(NC-FET) has attracted tremendous research efforts. However, the lack of a clear physical picture and design rule for this device has led to numerous invalid fabrications. In this work, we address this issue based on an unexpectedly
1234567890():,; concise and insightful analytical formulation of the minimum hysteresis-free subthreshold swing (SS), together with several important conclusions. Firstly, well-designed MOSFETs that have low trap density, low doping in the channel, and excellent electrostatic integrity, receive very limited benefit from NC in terms of achieving subthermionic SS. Secondly, quantum- capacitance is the limiting factor for NC-FETs to achieve hysteresis-free subthermionic SS, and FETs that can operate in the quantum-capacitance limit are desired platforms for NC-FET construction. Finally, a practical role of NC in FETs is to save the subthreshold and overdrive voltage losses. Our analysis and findings are intended to steer the NC-FET research in the right direction.
1 Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106, USA. *email: [email protected]
NATURE COMMUNICATIONS | (2020)11:196 | https://doi.org/10.1038/s41467-019-13797-9 | www.nature.com/naturecommunications 1 ARTICLE NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-019-13797-9
lthough the global semiconductor industry has reached a Previous attempts at understanding the workings of NC-FETs staggering ~$500 billion, to further continue such a either assumed the total FET gate capacitance to be a constant7,18, Afl ourishing growth, low-voltage or steep-slope logic tran- i.e., the bias-dependent channel capacitance was ignored, or were sistor is crucial for simultaneous reduction of power consumption focused on performing intensive numerical simulations21–25 or along with dimensional scalability of the metal oxide semi- complex analytical modeling26,27 of a specific NC-FET such as conductor field-effect transistors (MOSFETs)1,2. However, low- NC-FinFET and NC-2DFET etc., in which the generic device ering of the supply voltage, has failed to keep pace with the physics, design rule and major challenges of NC-FETs get feature-size scaling because the thermionic emission based obscured. In this work, we analytically formulate the slope of the transport mechanism of MOSFETs limits the steepness of their transfer characteristics of a generic NC-FET structure, from transfer characteristics in the subthreshold regime, i.e., SS,tobe which a physics-rich but concise picture is innovatively extracted ≥ 60 mV per decade at room temperature3, thereby constraining for “visualizing” the intriguing device physics and design space of the energy/power efficiency. To overcome this limitation, many NC-FETs. This picture can not only serve as a convenient design steep-slope (SS < 60 mV per decade) device concepts have been platform for NC-FET experimentalists, but also allow us to find a proposed, such as tunnel FETs4,5, impact ionization MOSFETs6, novel functionality of NC in modern MOSFET applications. NC-FETs7 etc., (Supplementary Note 1). Among these devices, More specifically, using fundamental FET and NC theory, we NC-FETs have been attracting most interest in recent years7–28, uncover the intriguing interplay between hysteresis and sub- thanks to their simple structure that involves minimal penalty in thermionic (or < 60 mV per decade) SS in NC-FETs in a very added (w.r.t. MOSFETs) manufacturing complexity. The NC simple and generic manner, and arrive at several important layer can be implemented with single-domain (best case) ferro- conclusions that are contrary to many contemporary under- electric (FE) materials, which are featured by their “double-well” standings on NC-FETs. Our analysis reveals that well-designed energy landscape versus polarization29 (see Supplementary scaled MOSFETs that have low trap density and low doping in Note 2 and Supplementary Fig. 2a). The anomalous polarization the channel, and excellent electrostatic integrity by employing response of FE material systems in the metastable state to external state-of-the-art FET structures, such as SOI-FET, FinFET, NW- electric field, results in an effective NC (see Supplementary FET, CNT-FET, and 2D material based FETs etc., which have Fig. 2b). It has been suggested7 that connecting an FE layer in negligible parasitic capacitance compared to the gate capacitance, series with a normal dielectric (DE) capacitor with a proper receive very limited benefit from NC in terms of achieving small capacitance matching between FE and DE can stabilize (see SS (< 60 mV per decade). Secondly, we derive an unexpectedly Supplementary Fig. 2c) the metastable NC state of the FE layer, concise and insightful formula for the minimum SS for hysteresis- which has been experimentally verified recently19,20. It was also free operation, which allows us to uncover that the quantum predicted that NC-FETs may be plagued by hysteresis, if the capacitance is the limiting factor for NC-FETs to achieve capacitance matching process is inappropriately performed, hysteresis-free subthermionic SS, and thus, only FETs that can which should be avoided in logic applications. Driven by the operate in the quantum-capacitance limit are desired platforms enthusiasm toward this novel “steep-slope” device, experi- for NC-FET construction. Thirdly, our analysis unveils a hitherto mentalists have been indiscriminately trying to incorporate FE concealed knowledge that compared to the target of achieving materials in the gate of various “X-FETs”, where X can be SOI, subthermionic SS, a more practical role of NC in FETs could be to Fin, nanowire (NW), 2D (such as MoS2, WSe2 etc.), or 1D (such save the subthreshold voltage loss caused by short-channel effects, as carbon nanotube (CNT), graphene nanoribbon (GNR) etc.), and the overdrive voltage loss caused by the large quantum generating numerous “NC-FETs” in the past several years8–15. capacitance, provided the polarization response of ferroelectric However, none of them exhibit SSs that are noticeably smaller materials can be enhanced to allow the NC to function effectively than 60 mV per decade and simultaneously free of hysteresis at high frequencies (GHz range). during both AC and DC operations (see Supplementary Table 1). Such a deviation from expectation stems from a lack of clear understanding of NC-FETs for many device experimentalists. In Results this sense, comprehending what NC-FETs really are, how to Capacitor network in a generic NC-FET. The switching of FETs design NC-FETs, and what can be expected from NC-FETs, can is realized by electrostatic (or capacitive) modulation of the play a decisive role in identifying a genuinely low-voltage switch potential of the channel through which current is conducted. that can revolutionize next-generation electronics including Figure 1a depicts all relevant capacitors in a generic NC-FET computing, sensing, and communication. structure. The discussion throughout this work is based on n-type
G E a bcF Vg
C V
frin,d-g NC CNC CNC NC S frin,s-g C D VMOS V
C OX Oxide C ox Spacer ox Spacer Ch Cfrin,s/d-g CQ Channel
Source Drain Voltage Sub C divider div Ctrap C d,geo Cs,geo Cdep
Substrate Small signal model Band diagram
Fig. 1 Capacitors in a generic NC-FET structure and its small-signal model. a Capacitors potentially involved in determining the channel potential of a generic NC-FET. CQ, Cdep, Cs/d,geo, and Ctrap are the quantum-, depletion-, s/d geometrical, and trap induced, capacitors, respectively. CNC and COX represent the capacitance of the NC and oxide layers, respectively. b Simplified small-signal model for NC-FETs. Note that in the small-signal model, the change in the values of the capacitances near the vicinity of a given DC bias point is negligible. Cdiv is the voltage divider capacitance that includes CQ, Cdep, Cs/d,geo, and Ctrap. The effect of fringing capacitance, Cfrin,s/d-g, is screened by power rails, and hence is irrelevant to channel potential control. c The conduction band diagram of NC-FETs under a positive gate bias. Note that due to negative CNC, VNC is negative.
2 NATURE COMMUNICATIONS | (2020)11:196 | https://doi.org/10.1038/s41467-019-13797-9 | www.nature.com/naturecommunications NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-019-13797-9 ARTICLE
fi device, if not speci ed otherwise. CNC and COX are the capaci- in Fig. 2b. m is called the body factor that captures the gate fi tances of the NC layer and gate oxide, respectively. CQ, Ctrap, Cdep, ef ciency of the FET under the NC layer, and AV is the voltage and Cs/d,geo represent quantum, interface trap induced, depletion, gain introduced by the NC layer, and source/drain geometrical capacitances, respectively, and can jj dVMOS CNC be grouped as gate voltage divider capacitance Cdiv, ¼ ¼ ð Þ AV jjÀ 4 ¼ þ þ þ þ ð Þ dVg CNC CMOS; NATURE COMMUNICATIONS | (2020)11:196 | https://doi.org/10.1038/s41467-019-13797-9 | www.nature.com/naturecommunications 3 ARTICLE NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-019-13797-9 = a b = = = = = Electrostatics Transport limited S: S Electrostatics TP STP c d Design space CQ narrows NC design Fin, NW, CNT, 2D... space, and constrains SSmin Ridiculously thick NC needed e log(Id) C Q Q e (S<0) (SS>60) V g (SS>60) dominated region Av dominates (SS<0) dominated region Hysteresis region m m Hysteresis region /dec mV 60 Vg Fig. 2 Impact of electrostatics and quantum capacitance on NC-FET design space. a Formulating Id-Vg slope or swing (S) by decoupling the electrostatics and transport contributions. STP is the transport limited S. b S is reduced to subthreshold S (SS) in the subthreshold regime. STP is reduced to 60 mV per decade. Body factor m (>1) and voltage gain AV (>1) compete with each other in determining SS. c Visualizing the SS formula and its physics. In the shaded region on the LHS, m dominates, thus SS > 60 mV per decade. In the shaded region on the RHS, SS < 0, represents the appearance of hysteresis. The design space here is between the two shaded regions where AV dominates and 0 < SS < 60. The dashed line illustrates the ultra-small negative slope of SS/60 line (which implies that SS/60 can be noticeably below 1 only for 1/|CNC| ≫ 1/Cox) for Fin-, nanowire (NW)-, carbon nanotube (CNT)- and 2D- FETs, indicating very small |CNC|, or equivalently very thick NC layer in these devices is required to obtain NC benefit. d A picture that captures all essential quasi-static device physics of NC-FETs. Note that in the near and above-threshold region, the SS/60 line transforms to the S/STP line, which rotates clockwise due to the rapidly increasing quantum-capacitance CQ with gate bias till a nearly vertical position is reached when the device is fully turned on. Since S in the entire range of Id–Vg curve should be guaranteed to be positive, in order to prevent hysteresis in both sub- and super- threshold regimes, the lower bound of 1/| CNC| is extended to 1/CMOS,>Vth, leading to a narrow NC design space and a minimum hysteresis-free SS ( = CQ/(CQ + Cdiv, S/STP line w.r.t. the SS/60 line, as illustrated in Fig. 2d. In order to be within the “m dominated region” (shaded region on the LHS – guarantee hysteresis-free I-V characteristics, or positive S, not of Fig. 2d), S in the entire range of Id Vg curve is guaranteed to be only in the subthreshold regime, but also near- and above- positive, i.e., Id–Vg curve is free of hysteresis. On the other hand, ≈ “ threshold regimes, the lower bound of the forbidden hysteresis in the absence of an oxide layer (i.e., 1/COX 0), the m domi- region (shaded region on the RHS of Fig. 2d) of 1/|CNC| gets ex- nated region” disappears, leaving negligible 1/|CNC| design space = + = ≈ tended from 1/CMOS, 4 NATURE COMMUNICATIONS | (2020)11:196 | https://doi.org/10.1038/s41467-019-13797-9 | www.nature.com/naturecommunications NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-019-13797-9 ARTICLE a bc Δ TG TNC = TNC (@SSmin)–TNC(@SS60) 60 102 30 nm HZO 4 nm HfO2 55 12 SDGermanane 5 nm HfO2 50 10 In As 100 Ga0.47 0.53 BG (Grounded) G Technologically 8 m) 45 μ 26 nm HZO challenging Si NC: HfZrOx A/ (nm) (mV/dec) –2 5 nm HfO2 6 μ ( 10 40 NC d 2.5 nm Chan. min I Ga0.47In0.53As T S (undoped) D Δ 4 SS 35 MoS2 Si p-doped substrate –4 SS = 49 2 SS = 39 MoS 2 10 SS = 46 30 0 Si 25 5 Ga0.47In0.53As 0 456 4 4 –6 1 2 3 2 3 10 EOT 1 2 EOT of C (nm) of C 0 0 (nm) –0.8 –0.6 –0.4 –0.2 0 0.2 div, Fig. 3 Impact of density-of-states on SSmin and NC design space. a SSmin at room temperature and b NC thickness design space (ΔTNC) for Si, 19 −3 17 −3 Ga0.47In0.53As, and monolayer MoS2. The effective DOS (conduction band) of Si and Ga0.47In0.53As are ~2.8 × 10 cm and ~2.1 × 10 cm , respectively. 14 −1 −2 The DOS of single-layer MoS2 is ~2.4 × 10 eV ·cm . The low-DOS Ga0.47In0.53As exhibits significant advantages. Cdiv, could help. In order to illustrate this, SSmin is evaluated for Si (as illustrated in the inset on the LHS of Fig. 3c. By optimizing the reference), Ga0.47In0.53As, and monolayer MoS2, as shown in oxide and NC thicknesses, SS of Germanane based NC-FETs can Fig. 3a, versus Cdiv, NATURE COMMUNICATIONS | (2020)11:196 | https://doi.org/10.1038/s41467-019-13797-9 | www.nature.com/naturecommunications 5 ARTICLE NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-019-13797-9 a c In short-channel FETs: Ion = = + 10 2 8 = 10 11 10 9 = 10 = 10 = + > = 10 Needed overdrive b voltage is reduced ! m) μ A/ = − − Two practical roles of negative μ TG log(Id) ( 1 capacitance for FETs d 10 43.1 nm HZO Δ I Voverdrive 2 nm SiO2 Ion SD5 nm Si In near and above-Vth regimes: 2 Save 300 nm SiO2 Save overdrive subthreshold voltage loss BG (grounded) = + voltage loss Δ 0 Δ ( Voverdrive) 10 ( Vsub-Vth) –0.2 0 0.2 0.4 1 Vg (V ) = − − d 300 250 Ioff /dec) 200 ΔV Vth Vg NC non-linearity induced sub-Vth V |CNC| mismatch to COX (m 150 S 60 60 100 = Transport limited S 0 0 50 TP 101 102 μ μ Id ( A/ m) Fig. 4 Role for NC in MOSFETs as a voltage-loss saver. a With a simple |CNC| = COX matching, SS can be restored to 60 mV per decade in short-channel MOSFETs, and S in near- and above- threshold regimes can be reduced to the transport limit (STP). Here Ctrap and Cdep are neglected, since they have been greatly suppressed in state-of-the-art MOSFETs. Thereby, b NC layer can help suppress the short-channel effect induced subthreshold voltage loss (ΔVsub- Vth), and inversion charge screening induced overdrive voltage loss (ΔVoverdrive). It is difficult for NC to help obtain hysteresis-free steep-slope turn-on characteristics. c Simulated Id–Vg and d S versus Id curve of a Si SOI NC-FET in which |CNC| is matched to COX. Lower NC non-linearity (quantified by the factor of β) is desired, in terms of restoring S back to STP. being NC-FETs, since those observations are not consistent with In fact, in terms of saving switching energy, NC-FET does not or supported by the fundamental physics-based predictions of the have to be designed as a steep-slope device. As indicated in Fig. 2d, subthreshold behavior of NC-FETs in this work and other rele- the S/STP line rotates with bias about a constant (bias and NC 37–40 vant work in the literature. In fact, more and more studies material independent) point (1/COX,1),whichprovidesan have indicated that the steep SSs observed in many of those important implication for a new role NC can play. To make it fabricated “NC-FETs” can be attributed to the transient effects clearer, SS formula for short-channel MOSFETs and NC-FETs, and (not captured in this work because of the ideal steady-state model S formula in the near and above-threshold regimes for MOSFETs employed, aimed at uncovering the essential physics and evalu- and NC-FETs of any scale, are reorganized in Fig. 4a. In the short- ating the upper-limit of NC-FET performance) during the mea- channel MOSFETs, Cdiv is mainly attributed to short-channel effect fi = = + surement and/or ferroelectric polarization dynamics, instead of (SCE), speci cally, Cdiv CSCE Cs,geo Cd,geo. CSCE prevents gate the negative capacitance effect through capacitance matching, voltage in subthreshold regime to drop entirely in the channel, i.e., it which provide further support to the analysis and the insightful causes a subthreshold gate voltage loss on the gate oxide, which is fl = + conclusions of this work, albeit from a different perspective. Here, re ected by a poor SS, SSMOSFET 60(1 CSCE/COX)>60 (see based on the SS physics of NC-FETs developed above, we also detailed derivations in Supplementary Note 3). On the other hand, provide our insight/suggestion to those who are trying to inter- in near and above-threshold regimes of MOSFETs, large CQ,or “ ” – pret the observed steep SSs in various reported NC-FETs from electron charge screening effect, forces Vg Vth, which is usually transient effect point of view. Essentially, to achieve sub- referred to as the overdrive voltage, to drop on the gate oxide, thermionic SS, the polarization dynamics should allow FE layer in instead of in the channel, leading to a poor gate efficiency, or = + ≫ the subthreshold regime to be greatly depolarized and allow equivalently a large S, SMOSFET STP·(1 CQ/COX) STP (see the weak residual polarization to be self-sustained (i.e., D ≈ detailed derivations in Supplementary Note 3). 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Van der Waals negative capacitance transistors. Nat. Comm. 10,1–8 (2019). 14. McGuire, F. et al. Sustained sub-60 mV/decade switching via the negative Acknowledgements capacitance effect in MoS2 transistors. Nano Lett. 17, 4801–4806 (2017). The research outlined in this article from the Nanoelectronics Research Lab at UCSB was fi 15. Si, M. et al. Steep-slope WSe2 negative capacitance eld-effect transistor. Nano supported by the ARO (grant W911NF1810366), JST CREST program (grant SB180064), Lett. 18, 3682–3687 (2018). and Intel Corporation. NATURE COMMUNICATIONS | (2020)11:196 | https://doi.org/10.1038/s41467-019-13797-9 | www.nature.com/naturecommunications 7 ARTICLE NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-019-13797-9 Author contributions Publisher’s note Springer Nature remains neutral with regard to jurisdictional claims in W.C. and K.B. wrote the manuscript. published maps and institutional affiliations. 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