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Design, Implementation, Modeling, and Optimization of Next Generation Low-Voltage Power Mosfets

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Design, Implementation, Modeling, and Optimization of Next Generation Low-Voltage Power Mosfets Design, Implementation, Modeling, and Optimization of Next Generation Low-Voltage Power MOSFETs by Abraham Yoo A thesis submitted in conformity with the requirements for the degree of Doctor of Philosophy Department of Materials Science and Engineering University of Toronto © Copyright by Abraham Yoo 2010 Design, Implementation, Modeling, and Optimization of Next Generation Low-Voltage Power MOSFETs Abraham Yoo Doctor of Philosophy Department of Materials Science and Engineering University of Toronto 2010 Abstract In this thesis, next generation low-voltage integrated power semiconductor devices are proposed and analyzed in terms of device structure and layout optimization techniques. Both approaches strive to minimize the power consumption of the output stage in DC-DC converters. In the first part of this thesis, we present a low-voltage CMOS power transistor layout technique, implemented in a 0.25µm, 5 metal layer standard CMOS process. The hybrid waffle (HW) layout was designed to provide an effective trade-off between the width of diagonal source/drain metal and the active device area, allowing more effective optimization between switching and conduction losses. In comparison with conventional layout schemes, the HW layout exhibited a 30% reduction in overall on-resistance with 3.6 times smaller total gate charge for CMOS devices with a current rating of 1A. Integrated DC-DC buck converters using HW output stages were found to have higher efficiencies at switching frequencies beyond multi-MHz. ii In the second part of the thesis, we present a CMOS-compatible lateral superjunction FINFET (SJ-FINFET) on a SOI platform. One drawback associated with low-voltage SJ devices is that the on-resistance is not only strongly dependent on the drift doping concentration but also on the channel resistance as well. To resolve the issue, a SJ- FINFET structure consisting of a 3D trench gate and SJ drift region was developed to minimize both channel and drift resistances. Several prototype devices were fabricated in a 0.5µm CMOS compatible process with nine masking layers. In comparison with conventional SJ-LDMOSFETs, the fabricated SJ-FINFETs demonstrated approximately 30% improvement in Ron,sp. This is a positive indication that the SJ-FINFET can become a competitive power device for sub-100V rating applications. iii Acknowledgements First of all, I would like to thank Prof. Wai Tung Ng for his supervision, encouragement, and invaluable counsel throughout my Ph.D. program. Without whose presence my development as both a student and an individual would not have progressed as rapidly. I wish to further acknowledge Prof. Johnny Sin (Hong Kong University of Science and Technology) and Yasuhiko Onishi (Visiting Scientist from Fuji Electric Corp.) who have contributed to my knowledge in the field, which better enabled me to carry out and finish my research project on time. I would like to express appreciation to all the members in the Smart Power Integration & Semiconductor Devices Research Group for their fruitful discussions over the course of this research, particularly M. Chang, O. Trescases, H. Wang, E. Xu, G. Wei, and Q. Fung. I would also like to express my appreciation to all the staff in Nanoelectronic Fabrication Facility (NFF) at HKUST who provided me with various IC fabrication support. Financial support from the University of Toronto Open Fellowship, the Natural Sciences and Engineering Research Council of Canada, and the Auto21 Network of Centres of Excellence of Canada are gratefully acknowledged. Lastly, I would like to extend my appreciation to my wife, Mia Yoo for her patience, consideration and support during the past four years. She has been wonderful and a true partner. Also, special thanks to my mother and parents-in-law for their constant support and encouragement throughout the studies. iv Table of Contents Table of Contents .............................................................................................................. v List of Tables .................................................................................................................. viii List of Figures ................................................................................................................... ix List of Glossary .............................................................................................................. xiv List of Symbols ............................................................................................................... xvi Chapter 1 Introduction ..................................................................................................... 1 1.1 Technology and Market Trends in Power Semiconductors ...................................... 1 1.2 Advantages of Power MOSFET Devices ................................................................. 3 1.3 Application Fields for Current and Future Power MOSFETs .................................. 4 1.4 Thesis Objectives and Organization ......................................................................... 6 Chapter 2 Power MOSFETs – a Brief Overview ........................................................... 7 2.1 Fundamentals of MOS Device .................................................................................. 7 2.2 Types of Power MOSFETs ..................................................................................... 11 2.2.1 Traditional Vertical Power MOSFETs ............................................................ 12 2.2.2 Traditional Lateral Power MOSFETs .............................................................. 14 2.3 CMOS-based Power MOSFETs ............................................................................. 18 2.3.1 Monolithic Integration: Standard CMOS Process ........................................... 18 2.3.2 CMOS Layout Techniques for Power Integrated Circuits ............................... 20 2.4 Super-Junction (SJ) Power MOSFETs ................................................................... 25 2.4.1 Device Concept and Characteristics ................................................................ 25 2.4.2 Current Status and Challenges of SJ Power MOSFETs .................................. 27 Chapter 3 Analytical Layout Modeling of Power MOSFET ...................................... 30 3.1 Analysis of Basic MOS Finger Structure................................................................ 30 3.2 Modeling of Conventional Multi-Finger (MF) Layout ........................................... 33 v 3.3 Modeling of Regular Waffle (RW) Layout ............................................................ 36 3.4 Proposed Hybrid Waffle (HW) Layout ................................................................... 38 3.4.1 Lfinger-Optimization of HW Layout Structure .................................................. 40 3.4.2 Performance Evaluation via FOM ................................................................... 42 3.4.3 Simulated Characteristics of Different Layout Structures ............................... 48 3.5 Summary ................................................................................................................. 53 Chapter 4 High Speed CMOS Output Stage for Integrated DC-DC Converter ...... 54 4.1 Output Stage Design based on 5V Hybrid Waffle Layout ..................................... 55 4.1.1 Design of Low-Side Switch: N-channel MOSFETs ........................................ 56 4.1.2 Design of High-Side Switch: P-channel MOSFETs ........................................ 59 4.1.3 Power Connection Routings ............................................................................ 61 4.1.4 ESD Protection, Power Clamp, and Guard Rings ............................................ 62 4.2 IC Fabrication and Packaging ................................................................................. 66 4.3 Test PCB Design ..................................................................................................... 68 4.4 Experimental Results and Discussion ..................................................................... 70 4.4.1 On-Resistance Measurements .......................................................................... 70 4.4.2 Gate-drive Loss Measurements ........................................................................ 75 4.4.3 Efficiency Measurements ................................................................................. 77 4.5 Summary ................................................................................................................. 79 Chapter 5 Device Structure and Analysis of the SJ-FINFET on SOI ........................ 80 5.1 Device Structure and Operating Concept ............................................................... 81 5.2 Process Simulations ................................................................................................ 87 5.2.1 Simulation of P-body Formation ..................................................................... 87 5.2.2 Simulation of SJ-drift Formation ..................................................................... 89 5.2.3 Simulation of N+ Source/Drain Contact Formation ........................................ 91 5.3 Device Simulations ................................................................................................. 92 5.3.1 Mesh Structure and Grid Refinement .............................................................. 92 5.3.2 Off-State Simulations ......................................................................................
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