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Effect of Transition from PD to FD Operation on the Depletion Isolation Effect in Vertical Mosfets

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Effect of Transition from PD to FD Operation on the Depletion Isolation Effect in Vertical Mosfets 1 Effect of transition from PD to FD operation on the depletion isolation effect in vertical MOSFETs M. M. A. Hakim*, C. H. de Groot*, E. Gili*, T. Uchino*, S. Hall** and Peter Ashburn* Email:[email protected] *Microelectronics Group, University of Southampton, Highfield, Southampton, SO17 1BJ, UK **Dept. of EEE, University of Liverpool, Brownlow Hill, Liverpool L69 3GJ, UK Abstract-We study the effect of transition from However no work has been reported on FD VMOS partially depleted to fully depleted operation on the transistors or on the transition from PD to FD operation depletion isolation effect in vertical MOSFETs. The and the impact of substrate conduction during this impact of the body contact during this transition is transition. In this article a comprehensive investigation of exemplified. It is found that for pillar thickness > 120 the transition from PD to FD operation on the depletion nm the body contact is effective and for pillar isolation is done during source on top mode of operation. thickness < 60 nm is ineffective. In VMOS devices with Subsequently the impact of the body contact on depletion pillar thicknesses of 60-120 nm, even though the isolation is reported at various pillar thickness to gain existence of depletion isolation is identified, substrate physical insight into the behavior of thin pillar body conduction is found to reduce floating body effects and contacted VMOS devices. improve the breakdown voltage. We show that the reduction of the pillar thickness results in the gradual ineffectiveness of the body contact. The impact of substrate conduction on the breakdown voltage and kink behavior is also gradually reduced. I. INTRODUCTION Aggressive scaling of CMOS devices has highlighted the requirement for fully depleted double or Fig. 1. Schematic cross-sectional view of a) planar SOI and b) surround gate MOSFETS for decananometer Si CMOS VMOS device operated in the depletion isolated mode. [1]. Excellent control of short channel effects, ideal subthreshold slope and increased drive current per unit II. MODELING PROCEDURE area have made these devices extremely promising for 100 nm channel length vertical ion-implanted high density, low voltage, and low power DRAM, double gate nMOSFETs with different pillar thickness SRAM, and ULSI applications. Technologically these (TSi) were simulated using the Silvaco Atlas device fully depleted double or surround gate MOSFETs can be simulator [9]. The gate oxide thickness was 2 nm and the realized using DG SOI [2], FINFETs [3] or vertical gate electrode chosen was a metal with a work function of 18 -3 MOSFETs (VMOS) [4]. 4.5 V. The body doping density was 10 cm and in the 19 -3 Though a major advantage of DG SOI and finfet source/drain region a lightly doped region of 10 cm 20 -3 technologies is the ease of device isolation, in most cases surrounded a heavily doped region of 10 cm . the body is left floating and hence these devices suffer A 2D coupled Poisson’s drift-diffusion solver from floating body effects. An extensive amount of work was used to investigate the device operation. The has been done on floating body effects in both partially dependence of carrier mobility on the parallel and depleted (PD) and fully depleted (FD) planar silicon on transverse fields was accounted for by using the Lombardi insulator (SOI) transistors [5-7]. VMOS devices have the CVT model [9]. The mobility parameters in the simulator advantage that it is easier to make a body contact and were calibrated against a bulk silicon transistor [9]. In hence, the floating body effect is less severe than in particular the mobility degradation due to surface planar SOI MOSFETs. But with the scaling of pillar roughness arising from dry etch of vertical pillar was thickness the floating body effect is also observed in accounted for by adjusting the surface roughness factor in VMOS devices during source on top mode of operation the model. It is found that satisfactory agreement between even if a body contact is provided [8]. This effect has simulated and experimental values [4] are obtained when been termed depletion isolation [8] and is caused by the surface roughness factor of CVT model is reduced to 13 13 penetration of the depletion region of the bottom drain δ(elec) = 2.91×10 and δ(holes) = 1.027×10 . Impact junction towards the center of the pillar and the eventual ionization (II) was modeled by the Selberherr law for the isolation of the pillar from the body contact as shown in generation rate and the optimized model parameters for fig. 1(b) and also compared with planar SOI MOSFETs submicron bulk silicon transistors were used [10]. (fig. 1(a)). Terauchi et al [8] found depletion isolation in PD VMOS transistors and showed how this effect III. RESULTS & DISCUSSIONS influenced the output and substrate current characteristics. Fig. 2 shows output characteristics of the 2 simulated VMOS transistor with and without a body For the thinnest pillar in fig. 2(c), the contact, for three different pillar thicknesses and for characteristics for VMOS devices with and without a source on top mode of operation. In the thick pillar body contact are very similar, indicating that the body VMOS device with a body contact (Fig. 2(a)), ideal contact is ineffective at this pillar thickness. The values of characteristics are obtained with no evidence of floating drain current are significantly higher than those for the body effects at high drain voltages. In contrast in the device in fig. 2(b), and the breakdown kink is less VMOS device without a body contact, a breakdown kink severe. can be seen at a drain voltage of around 4.4V, and the values of drain current are higher than equivalent values in the body contacted device at all drain voltages. T =200 nm Breakdown kink 2.0 Si with body contact without body contact 1.5 (a) m) µ V =2.5V 1.0 g V =2.5V V =2V g g (mA/ V =2V V =1.5V g d 0.5 g I V =1V V =1.5V g g V =1V g 0.0 T =60 nm 2.0 Si with body contact m) without body contact µ 1.5 V =2.5V (b) g V =2V Charging hump g 1.0 (mA/ d I 0.5 V =1.5V g V =1V 0.0 g T =10 nm 2.0 Si with body contact without body contact m) 1.5 µ V =2.5V (c) g V =2V 1.0 g (mA/ V =1.5V g d I V =1V 0.5 g 0.0 012345 V (V ) d Fig. 3. Schematic cross-sectional view of the body contacted VMOS device before and after depletion isolation. Dashed line Fig. 2. Output characteristics (IDS vs VD) of the simulated ion- implanted VMOS device with and without a body contact during represents depletion layer edge. a)200 nm, b) 60 nm and c) 10 source on top mode of operation at pillar thicknesses of a) 200 nm. nm, b) 60 nm and c) 10 nm. Fig. 3 shows the schematic cross-sectional view of the body contacted VMOS device at low and high drain For the intermediate pillar thickness in fig. 2(b), bias for the pillar thicknesses shown in fig. 2. In the thick the VMOS device without a body contact shows similar pillar VMOS device, shown in fig 3(a) (corresponding to characteristics to the equivalent device in fig. 2(a), fig 2(a)), no depletion isolation occurs within the range of although the breakdown kink is sharper and the values of drain biases shown in fig. 2. Therefore, no body charging drain current at a given drain voltage are slightly higher. occurs and the output characteristic of the body contacted In contrast, the body contacted device is considerably VMOS device does not exhibit any breakdown kink and different than the equivalent device in fig. 2(a). In charging hump. Fig. 3(b) shows the VMOS device with particular, the device shows a sharp breakdown kink at a intermediate pillar thickness (corresponding to fig. 2(b)), drain bias around 4.45V, higher values of drain current where the drain bias dependent depletion isolation is and the presence of a hump at a drain voltage of around clearly evident and hence, the output characteristics of the 1.2 V. When comparing characteristics of the devices body contacted VMOS device exhibited a breakdown with and without a body contact, it can be seen that the kink. The charging hump found at 1.2 V reflects the body difference in current between the VMOS device with and charging after depletion isolation. In the body contacted without the body contact is reduced and the breakdown VMOS device, charging starts after depletion isolation kink of the body contacted device occurs at a slightly (charging lag). Therefore, the total body charging is lower higher drain voltage. than for the device without a body contact and the device 3 exhibits slightly better breakdown behaviour at this pillar body contact, and a lower φSB means a lower amount of thickness even after depletion isolation. In the very thin free holes available for body charging [6]. Therefore, the pillar case of fig. 3(c) (corresponding to fig. 2(c)) the difference in the normalized breakdown current between depletion region isolates the pillar even at low drain bias. the device with and without a body contact is gradually Therefore, the output characteristics of the VMOS devices reduced with the scaling of the pillar thickness. with and without body contact are found to be similar and To further clarify the point, we have simulated no charging hump is visible (fig.
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