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Device-Level Predictive Modeling of Extreme Electromagnetic Interference

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Device-Level Predictive Modeling of Extreme Electromagnetic Interference University of New Mexico UNM Digital Repository Electrical and Computer Engineering ETDs Engineering ETDs Summer 7-15-2020 DEVICE-LEVEL PREDICTIVE MODELING OF EXTREME ELECTROMAGNETIC INTERFERENCE NISHCHAY H. SULE The University of New Mexico Follow this and additional works at: https://digitalrepository.unm.edu/ece_etds Part of the Electronic Devices and Semiconductor Manufacturing Commons, and the VLSI and Circuits, Embedded and Hardware Systems Commons Recommended Citation SULE, NISHCHAY H.. "DEVICE-LEVEL PREDICTIVE MODELING OF EXTREME ELECTROMAGNETIC INTERFERENCE." (2020). https://digitalrepository.unm.edu/ece_etds/492 This Dissertation is brought to you for free and open access by the Engineering ETDs at UNM Digital Repository. It has been accepted for inclusion in Electrical and Computer Engineering ETDs by an authorized administrator of UNM Digital Repository. For more information, please contact [email protected], [email protected], [email protected]. NISHCHAY H. SULE Candidate Electrical and Computer Engineering (ECE) Department This dissertation is approved, and it is acceptable in quality and form for publication: Approved by the Dissertation Committee: Dr. Payman Zarkesh-Ha , Chairperson Dr. Edl Schamiloglu Dr. Sameer Hemmady Dr. Daryl Beetner i DEVICE-LEVEL PREDICTIVE MODELING OF EXTREME ELECTROMAGNETIC INTERFERENCE by NISHCHAY HEMANT SULE B.S. in Electrical Engineering, The University of New Mexico, 2013 DISSERTATION Submitted in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy Engineering The University of New Mexico Albuquerque, New Mexico July 2020 ii DEDICATION This work is dedicated to my parents and extended family in India, and the US, whose support, motivation, and love help guide me and push me forward to be a better version of myself. Lastly, to my late maternal grandmother and late maternal uncle, your support and love, I dearly miss. प्रिय आई आप्रि बाबा, मी नेहमीच तुमचा आभारी आहे. (Dear mom and dad, I am forever grateful to you.) iii ACKNOWLEDGMENTS First and foremost, I would like to thank my academic advisor, Dr. Payman Zarkesh-Ha, for accepting me as his Ph.D. student and for believing that I can achieve this degree. His vast experience and knowledge, about a given subject matter, especially in microelectronics, really shines through his insightful and critical question(s) he would ask of me. I felt that when we sat down for a discussion with regards to my research, there was never a dull moment. I am thankful to my dissertation committee: Dr. Edl Schamiloglu, Dr. Sameer Hemmady, and Dr. Daryl Beetner. Sameer and Prof. Edl, your suggestions, and comments during the paper writing - helped me realize that there is still a lot for me to learn and improve upon, which is a great eye-opener for me. I would also like to thank Dr. Sanjay Krishna (formerly at UNM), who helped introduce Dr. Zarkesh-Ha to me, which in turn has led me to this opportunity. I would like to thank Dr. Tim Clark, from AFRL, who pointed me toward the AFRL- COE grant, back when I started working as an AFRL Scholar for his division. Furthermore, I would like to thank the United States Air Force Research Laboratory (AFRL) and Air Force Office of Scientific Research (AFOSR) for their support with AFOSR/AFRL COE Grant #FA9550-15-1-0171 and by DURIP Grant #FA9550-15-1-0379. I would also like to thank Zahra Abedi for collecting experimental data for me. To my officemates in ECE 318, it gives me great pleasure knowing and sharing personal events with you. Although we had our differences and worked our schedules, it was great to know and learn cultural similarities and differences from each of you. iv Lastly, I am thankful to my parents, who have always been supportive and cheered me from my corner. I am grateful to my parents for risking it all and coming to a new country in search of a better future for me. They have taught me the value of working hard. I love you - mom, and dad! v DEVICE-LEVEL PREDICTIVE MODELING OF EXTREME ELECTROMAGNETIC INTERFERENCE by Nishchay H. Sule B.S., Electrical Engineering, The University of New Mexico, 2013 Ph.D., Engineering, The University of New Mexico, 2020 ABSTRACT Radio Frequency (RF) interference is a prominent issue for modern electronic devices. As device size and supply power shrink to meet the on-going demand for compact and complex Integrated Circuits (ICs), their susceptibility to external noise coupling to the input or power supply increases significantly. One such type of noise that acts upon a system to be considered is Extreme Electromagnetic Interference (EEMI). Previous works done to understand and evaluate the impact of EEMI onto a system or sub-system have been conducted on a statistical or empirical analysis level, which has led to complex and convoluted analysis, that requires significant time and computational power. Furthermore, since Electromagnetic Interference/Compatibility (EMI/EMC), engineers have to deal with complex systems, they typically come up with an estimate to analyze such systems. vi The premise behind this research is to highlight the development of the refinements of such "rule-of-thumb" guidelines to help EMI/EMC engineers quickly estimate device or circuit level susceptibility for the injected EEMI signals. A novel analytical model is proposed in this research, which offers an alternative solution for the limits of malfunction for a Silicon-based (Si) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) under EEMI bias. These developed analytical predictive models help determine the maximum limits for large-signal gate-side (input) or drain-side (power supply) injection in terms of the device's ION/IOFF ratio prior to degradation or damage to the device. The ION/IOFF ratio is a function based on the MOSFETs' device parameters. These models have been developed for a single transistor, particularly n-type and p-type MOSFETs when the EEMI signal is superimposed onto the gate or drain terminals. Additionally, these predictive models have also been extended to determine the maximum tolerance for gate or drain injections as transistor technology scales down. Furthermore, these models have been compared and validated with prototype test chips across five different technology nodes. Lastly, the analytical models have been expanded to be used in several different assessments, such as high-frequency analysis, manufacturer, and transistor size- independent and sensitivity modeling. Such demonstrations show the fundamental nature and flexibility, which allows these models to be used based on the EMI/EMC engineers' needs. vii Table of Contents DEDICATION ................................................................................................................... iii ACKNOWLEDGMENTS ................................................................................................. iv ABSTRACT ....................................................................................................................... vi Table of Contents ............................................................................................................. viii Table of Figures ................................................................................................................. xi List of Tables ................................................................................................................... xiv Chapter 1: Introduction ................................................................................................... 1 1.1 Background ............................................................................................................... 1 1.2 Motivation ................................................................................................................. 2 1.3 Development of the Problem Statement ................................................................... 3 1.3.1 Transistor ........................................................................................................... 3 1.3.2 Impact of EEMI on MOSFET at Component or Device-level ........................ 12 1.4 Dissertation Overview ............................................................................................ 14 1.4.1 Dissertation’s Significance .............................................................................. 14 1.4.2 Dissertation’s Contribution .............................................................................. 15 1.4.3 Outline of the Dissertation ............................................................................... 16 1.5 References ............................................................................................................... 18 Chapter 2: Development of Analytical Predictive Models .......................................... 27 viii 2.1 Introduction ............................................................................................................. 27 2.2 ION and IOFF Currents ............................................................................................... 28 2.3 Gate Injection Modeling for a Single Transistor .................................................... 34 2.4 Drain Injection Modeling for a Single Transistor ................................................... 38 2.5 Gate Injection Modeling for Scaling of Technologies ............................................ 44 2.6 Drain Injection Modeling for Scaling of Technologies .......................................... 47 2.7 Summary ................................................................................................................
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