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Aug. 27, 1963 DAWON KAHNG 3,102,230 ELECTRIC FIELD CONTROLLED SEMICONDUCTOR DEVICE Filed May 31, 1960

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Aug. 27, 1963 DAWON KAHNG 3,102,230 ELECTRIC FIELD CONTROLLED SEMICONDUCTOR DEVICE Filed May 31, 1960 Aug. 27, 1963 DAWON KAHNG 3,102,230 ELECTRIC FIELD CONTROLLED SEMICONDUCTOR DEVICE Filed May 31, 1960 F/a/A _ f’ v IJ Wki§¢£§lmfgkw Q F/G. /B 24 _ 2/ 0 FIG. 2 I I0 - i l V’ 4 S‘ 1 4 _ ~ I 34 -2 | '8/ 2 _ l ‘/ —4 II 38 \ 10-4 IL AMPERES lNl/ENTOR By D.KAHNG ATTORNE V ,. 3,102,230 United States Patent 0 ICC Patented Aug. 27, 1963 1 2 than .025 inch square but occupying a surface area of 3,102,230 less than 3><l0-‘1 (inch)? The oxide coating 19 is in ELECTRIC FIELD CONTROLLED SEMl intimate contact with surface 18 of the wafer. The oxide CONDUCTOR DEVICE is about 1000‘ angstrom units thick and thermally grown Dawon Kahng, Plain?eld, N.J., assignor to Bell Tele phone Laboratories, Incorporated, New York, N.Y., a in accordance with the processes described in United corporation of New York - . States Patent No. 2,930,722, issued March 29, 1960 to Filed May 31, 1%0, Ser. No. 32,801 J. R. Ligenza. These pnocesses leave oxide coatings over 6 Claims. (Cl. 323-94) - the entire device. The ‘oxide can be restricted to selected portions of the surface of the ‘device, if so desired, by This invention relates to circuit arrangements including well-known masking or lapping techniques. The oxide is dielectric coated semiconductor devices. 10 shown restricted in the ?gure primarily for clarity. An More particularly, the present invention relates to cir electrode 21 is deposited over the exposed surface 22 of cuit arrangements utilizing a semiconductive device which the oxide coating 19 to extend over the region of inter comprises either a p-n-p or n-p-n Wafer having a dielec section__of both p-n junctions'lld and 17. Ohmic contacts tric ?lm ‘over a portion of the middle zone. Such a device 24- aiid ‘25 are a?ixed to surface portions 13‘ and 14, re is disclosed in application Serial No. 13,688 of M. M. 15 spectively. A load L and a battery 27 of voltage V Atalla, ?led March 8, 1960. ' are connected serially between contacts 24 and 25. The In accordance with the present, invention useful char battery is poled to reverse bias p-n junction 16 and for acteristics are obtained'irom a device of this type by ward bias p-n junction 17. A voltage source 28 providing arranging the associated circuitry to vary an electric ?eld a voltage V, is connected between electrode 21 and con across the oxide in response to variations in voltage across tact 2.4-. In response to an accumulation of charge of one the junctions. In particular, voltage regulation or am polarity on the electrode 7.1, a charge of opposite polarity pliiication can be achieved by the invention. is induced in the surface portion 23 of wafer '11. I ' Therefore, a feature of this invention is a novel circuit A typical load line drawn for the load L is shown by arrangement which provides across the dielectric layer 25 the broken line 311 in the graph of FIG. 2. First, it can of the above device an electric ?eld which varies in re be seen from the graph that each of the characteristics sponse to variations in voltage across the p-n junctions. corresponding to a ?xed value of V; exhibits a horizontal The invention in its preferred form'comprises a semi portion where the voltage is relatively insensitive to the conductor wafer, typically silicon, including ?rst, second current. Accordingly, the device described is useful as a and third regions de?ning respectively ?rst and second 30 voltage regulator when operated ‘with a constant value of p-n junctions which intersect a major surface of the Vi. Moreover, it can be seen that adjustment to a par wafer. This [major surface of the wafer is coated with a ticular ?xed ‘value of V, permits control of the voltage suitable dielectric, typically a thermally grown silicon di at which regulation occurs. Accordingly, the invention oxide coating for a silicon wafer, and an electrode is con in this aspect is a voltage regulator whose voltage level nected to the surface of this oxide coating so as to extend can be varied simply by variation of the steady voltage beyond the line of intersection with the surface of the between electrode 121 and contact 24‘. two p-n junctions. A ?rst bias voltage is applied between As an alternative mode of operation, a signal source ohmic contacts to the ?rst ‘and third regions poled to for can be inserted serially with the source of Dz-C. voltage ward bias the ?rst p-n junction and to reverse bias the Vf. This arrangement is shown schematically in FIG. second. A second bias voltage is applied between the 40 1B. In this mode, changes in the voltage lot the signal electrode to the oxide coating and the contact to the third source will cause corresponding changes, although with a region. The electric ?eld across the oxide coating is-the phase reversal, in the voltage across the load L. Because result of this second bias and varies in response to varia the input impedance typically is much higher than the tions in the voltage between the two substantially ohmic load impedance, power ampli?cation is possible. contacts. 45 While the speci?c embodiments are disclosed in terms The invention and its objects and features will become of silicon and silincon dioxide, such choices are merely apparent during the course of the following detailed de by way of example. The choice of semiconductor mate scription which is rendered ‘with reference to the accom rial and corresponding dielectric appear to ‘be limited only panying drawing in which: by the availablity of techniques for depositing the dielec FIG. 1A is a perspective View partially in cross section 50 tric. There are, however, well-known considerations im of the preferred embodiment of this invention; portant in selecting the semiconductor material and a FIG. 1B is an alternative circuit arrangement for the suitable dielectric. The main consideration is to produce embodiment of FIG. 1A; and , the highest ?eld E in the semiconductor material with the FIG. 2 is a graph depicting the 'current—voltage charac smallest input voltage Vi. The equation relating E and teristics of the embodiment of FIG. 1A. V is It is to be understood that the ?gures are illustrative E=§LK only and, therefore, not necessarily to scale. eS t‘ Referring now to FIG. 1A in detail, device 10 com prises a semiconductor wafer ‘11, typically monocrystalline where e, is the dielectric constant of the dielectric coating, silicon, having dimensions of approximately .060 inch eS is the dielectric constant of the semiconductor material square by .010 inch thick. The bulk portion 12 of wafer and t-is the thickness of the dielectric coating. To obtain 11 is of n-type conductivity with spaced p-type surface the highest ?eld [for the lowest input voltage, portions \13 and 14 adjacent a major surface 180i the er wafer. Surface portions 13 and 14 are about .001 inch I deep and are formed by well-known vapor-solid diifusion and photo-resist techniques. The portion 15 between-the is maximized. ef for silicon dioxide is 3.8. A typical two surf-ace portions 13' and 14 is approximately .003 inch thickness t ‘for the oxide coating is 1000 angstrom units wide and bounded by p-n junctions 16 and '17, respective or 10*5 centimeters. Therefore, a ?gure of merit is ly. Advantageously, the surface area of portions .13 and 3.8 14 is restricted to avoid excessive capacitance. In this speci?c example, each surface portion has a “key hole” 70 10*5 cms. appearance having extreme surface dimensions of less or 313x10‘5 [cms. -1]. As a comparison, the dielectric 3,102,230 . 3 . 4 constant for titanium oxide is 100. Therefore, a corre ‘may be made therein'without departing from the scope spondingly suitable titanium oxide coating would have to and spirit of this invention. be - What is claimed is: I _ ' ' 100 1. In combination, a semiconductor wafer including at 3.8 X 105 least a ?rst and third region of one conductivity type sepa rated by a second region of the opposite conductivity type or 26,300 .angstrorn units thick. The ease of growing a and de?ning respectively a ?rst and second p-n junction, 1000 angstrom unit silicon dioxide layer on silicon as said ?rst and second p-n junctions intersecting a major compared to the di?iculties in depositing a titanium oxide surface of the wafer, a dielectric coatingover at least , ‘ layer of over 26,000 angstrorn units suggested the present said major surface, means for impressing a voltage across‘ ' advantage of the silicon system. It is expected also that said ?rst and second p-n junctions, means for impressing the thin ?lm ‘found on such compound semiconductors as n-type gallium arsenide is adaptable for use in accordance an electric ?eld across said dielectric in a direction to with this invention. encompass both said dielectric and said semiconductor Furthermore, the highest operating voltage V for a wafer, said electric ?eld being particularly characterized particular device is determined by the equation 15 in that it is responsive to variations in the voltage across sai-d'?rst and second p-n junctions. ‘ V—V£ 2. In combination, a silicon semi-conductor wafer in- ~ Est IlV eluding at least a ?rst and third conductivity-type region where Est is the dielectric strength of the dielectric of one conductivity type separated by a second region of coating.
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