UNIVERSITY OF CINCINNATI
Date:______
I, ______, hereby submit this work as part of the requirements for the degree of: in:
It is entitled:
This work and its defense approved by:
Chair: ______
A Simulation Study of Silicon Nanowire Field
Effect Transistors (FETs)
A thesis submitted to the
Division of Graduate Studies and Research of
the University of Cincinnati
in partial fulfillment of the
requirements for the degree of
MASTER OF SCIENCE
in the Department of
Electrical and Computer Engineering and Computer Science
of the College of Engineering
July, 2007
by
Saumitra Raj Mehrotra
B.E. (Instrumentation & Control Engineering),
Department of Instrumentation & Control Engineering,
University of Delhi, Delhi, India 2005.
Thesis Advisor and Committee Chair: Dr. Kenneth P. Roenker
Committee Members: Dr. Fred R. Beyette, Dr. Punit Boolchand Abstract
Silicon planar MOSFETs are approaching their scaling limits. New device
designs are being explored to replace the existing planar technology. Among the possible
new device designs are Double Gate (DG) FETs, FinFETs, Tri-Gate FETs and Omega-
Gate FETs. The Silicon Nanowire Gate All Around (GAA) FET stands out as one of the
most promising FET designs due to its maximum gate effect in controlling the short
channel effects. Recent developments such as synthesis of highly ordered nanowires and
fabrication of nanowires as small as 1nm in diameter have illustrated the progress possible in silicon nanowire technology In this study we have explored the silicon nanowire FET as a possible candidate to replace the currently planar MOSFETs.
In this thesis we investigated the silicon nanowire FET device and compared its performance with that of a double gate (DG) FET. The software used for the study assumed quantum-ballistic transport (NanoWire), which was developed at Purdue
University. Initially, we presented a comparison of Nanowire FET with DG FET with for devices with same physical parameters. It was seen that superior subthreshold characteristics are exhibited by a silicon nanowire FET. We also conducted an optimization study for the 25 nm node from the ITRS report. The final device was optimized for both High Performance and Low Operating Power applications. A further study on future technology nodes down to the 14 nm node was performed which revealed short channel effects becomes significant at gate lengths ~ 5 nm even for a silicon nanowire device. Finally, a process variation study was conducted in comparison with a
FinFET device. It was concluded that a silicon nanowire FET shows less sensitivity to process variation except it has higher sensitivity in variation with the diameter at less than
~4 nm than for FinFET where significant quantum effects set in. Variation with the gate length was found to be much less sensitive for the silicon nanowire FET because of its superior gate control characteristics.
Acknowledgements
I would like to express my gratitude to the faculty and students of the University of Cincinnati for making my stay here a pleasant experience.
In particular, I would like to thank Dr. Kenneth. P. Roenker for guiding and helping me complete this work. Thanks are due to Dr. Fred R. Beyette and Dr. Boolchand for agreeing to be part of my thesis defense committee and for their help in clarifying a lot of questions I had during my period of stay here.
I would like to thank my former and present lab members, Joe, Subu and Martin for the various discussions we had, both technical and otherwise. It was fun to be part of this research group and share the time in the laboratory.
Special thanks to my parents and my brother for helping me successfully overcome some difficult times during the period of my stay here.
Contents
1. Introduction 1
1.1 Moore’s Law 2
1.2 MOS Transistor 4
1.3 Scaling of MOSFETs 5
1.4 Scaling Issues and Approaches 8
1.4.1 Short Channel Effects 9
1.4.2 Gate Oxide 12
1.4.3 New Materials 14
1.5 Issues at Nanoscale Level 17
1.6 Non Classical Device Structures 22
1.6.1 Ultrathin Body Single Gate MOSFET 22
1.6.2 Dual Gate FET/ FinFET 23
1.6.3 Trigate FET/ Omega Gate FET 26
1.7 Silicon Nanowire Technology 27
1.8 Purpose of Thesis 33
1.9 Organization of Thesis 34
2. Simulation Software: Theory and Preview 41
2.1 Classification of Transport Models 42
i 2.2 Simulation Software Description 43
2.3 Simulation Tool Preview 50
2.4 Comparison with Experimental Results 55
2.5 Conclusion and Summary 59
3. Device Simulation Results and Comparison for
n-channel Silicon Nanowire FET 61
3.1 Baseline Device Structure 62
3.2 Device Simulations Results 63
3.2.1 Comparison of a SiNW FET with DG FET 63
3.2.2 Effects of Scaling on Silicon Nanowire
FET Parameters 67
3.3 Results and Discussions 70
4. Device Optimization and Scaling Potential for a
Silicon Nanowire FET 72
4.1 Device Optimization study of Silicon Nanowire FET
for the ITRS 25 nm node. 73
4.1.1 Device Simulation Structure 73
4.1.2 Simulation Results for the Optimization Study 75
4.2 Scaling Potential of Silicon Nanowire FET 87
4.2.1 Scaling of MOSFETS beyond 45 nm node 87
ii 4.2.2 Device Simulation Structure 89
4.2.3 Simulation Results 89
4.3 Conclusions and Discussions 96
5. Process Sensitivity Study for Silicon Nanowire
Transistors 98
5.1 Baseline Device Simulation Structure 99
5.2 Threshold Voltage 101
5.2.1 Effect of Channel Doping on Threshold Voltage 101
5.2.2 Effect of Diameter on Threshold Voltage 104
5.2.3 Effect of Gate Length on Threshold Voltage 106
5.2.4 Effect of Oxide Thickness on Threshold Voltage 108
5.3 ON-Current, OFF-Current and ON/OFF Current Ratio 110
5.3.1 Current Variation along Diameter 110
5.3.2 Current Variation with Gate Length 114
5.4 Effect of Process Variation on Subthreshold Characteristics 116
5.4.1 DIBL and Subthreshold Slope Variation with
Diameter 116
5.4.2 DIBL and Subthreshold Slope Variation with
Oxide Thickness 120
5.5 Results and Conclusions 121
iii 6. Conclusions & Future Work 125
6.1 Conclusions 125
6.2 Future Work 126
iv List of Figures
Figure 1.1 Increasing number transistors with each new microprocessor technology [50]
Figure 1.2 3-D view of a basic n-channel MOSFET.
Figure 1.3 Constant field scaling and constant voltage scaling parameters [49].
Figure 1.4 Industry-trend scaling (points) contrasted with classical scaling (dashed lines) [18].
Figure 1.5 History and trends for supply voltage (Vdd), threshold voltage (Vt) and oxide thickness (tox) versus channel length for CMOS logic technologies [19].
Figure 1.6 Potential contour for a (a) long channel device and a (b) short channel device [20].
Figure 1.7 Short-channel threshold roll off: measured low- and high- drain threshold voltage of n- and p- MOSFET’s versus channel [20].
Figure 1.8 Band diagram for a (a) long channel and a (b) short channel device.
Figure 1.9 Calculated gate oxide tunneling current vs gate voltage for different oxide thickness [19].
Figure 1.10 Strained silicon grown over a silicon germanium (SiGe) layer [22].
Figure 1.11 (a) Increased mobility and (b) drain current with strained Si technology [23].
Figure 1.12 High-k and metal gate technology proposed by Intel (production year: 2007) [26].
Figure 1.13 Degradation of subthreshold slope due to source-drain tunneling at gate lengths below 10nm. [27].
Figure 1.14 Off current increase with decreasing gate length due to source-drain tunneling for a dual gate device at Vds=1V, Tsi=2nm, tox=1nm [27].
Figure 1.15 Threshold voltage increase with reducing SOI channel width [29].
v Figure 1.16 Variation in Id-Vg curves with different discrete dopant distribution for 24 devices. Solid dots indicate the conventionally doped device. It shows 20- 30mV variation along gate voltage, 30mV shift in subthreshold region and 15 mV shifts in linear region [30].
Figure 1.17 (a) Schematic diagram for UTB MOSFET [33] (b) TEM image of a UTB device [34].
Figure 1.18 Dual-Gate FET structure (left) and a FinFET structure (right)
Figure 1.19 More ideal subthreshold slope/DIBL evident for double gate (DG) FET as compared to a single gate (SG) FET [47].
Figure 1.20 (a) Id-Vg (top) and Id-Vd curves (b) SEM image and gate profile (c) TEM image of a FinFET [35].
Figure 1.21 Schematic diagram for a (a) TriGate FET [36] (b) Omega-Gate FET [37].
Figure 1.22 SEM image of (a) 200 nm long silicon nanowire and (b) after gate electrode definition ; 4 nm grown oxide followed by 130 nm amorphous silicon. [51].
Figure 1.23 (a) Schematic of the back gate SiNW FET (b) TEM image of a 5nm diameter SiNW [38].
Figure 1.24 Size-controlled synthesis of SiNW from Au nanoclusters for diameter control [44].
Figure 1.25 Id-Vd curve for the back gate silicon nanowire transistor [38]. Red curve is after annealing.
Figure 1.26 TEM image of fabricated GAA silicon nanowire transistor structure [14].
Figure 1.27 Id-Vd and Id-Vg curves for a 5 nm diameter GAA silicon nanowire transistor [14].
Figure 2.1 Schematic of intrinsic nanowire device with circular cross section [3].
Figure 2.2 Mesh generated at each slice of the nanowire device for simulations [3].
Figure 2.3 Snapshot of the interface of the NanoWire simulation tool.
Figure 2.4 Snapshot of Id-Vd curve for the baseline device (Vg=0.8V).
Figure 2.5 Snapshot of Id-Vg curve for the baseline device (Vd=0.8V).
vi Figure 2.6 Snapshot of the electron density cloud within the channel of the baseline device.
Figure 2.7 Snapshot of voltage profile within the channel of the baseline device.
Figure 2.8 (a) Fabricated 30 nm long silicon gate all around nanowire FET (b) Id-Vg curve for the fabricated device [6].
Figure 2.9 Comparison gate current characteristics of simulated (circle) and experimental (square) 30 nm long silicon nanowire devices [6].
Figure 2.10 Id-Vg curves for simulated (solid) and experimental (dashed) 30 nm long silicon devices.
Figure 3.1 Device structures for a (a) Double Gate FET and a (b) Silicon Nanowire FET.
Figure 3.2 Simulated Output characteristics for a 10 nm gate length Silicon nanowire FET (▲) and a DG FET (●).
Figure 3.3 Comparison of Id-Vg curves for multi gate transistors with increasing effective number of gates at gate length of 9 nm [2].
Figure 3.4 Simulated Id-Vd curves for the Silicon Nanowire FET (▲) and Double Gate (DG) FET (●).
Figure 3.5 Simulation result for variation in Id-Vg current characteristics with varying diameter.
Figure 3.6 Simulation result for variation in Id-Vg current characteristics with Gate Length.
Figure 3.7 Simulation result for variation in Id-Vg current characteristics with Oxide thickness.
Figure 4.1 A three dimensional (3D) Silicon nanowire FET structure being simulated.
Figure 4.2 Dependence of Ion on diameter for silicon nanowire FET for different gate electrode work functions. The solid and dashed lines mark the Ion targets of ITRS for HP and LOP, respectively.
Figure 4.3 Dependence of Ioff on diameter for silicon nanowire FETs for different gate electrode work functions. The solid and dashed lines mark the Ioff targets of ITRS for HP and LOP, respectively.
vii Figure 4.4 Simulation results for the Ion - Ioff curve of simulated 10 nm Silicon nanowire FET with various work function and nanowire diameter. The solid line represents the HP specifications and the dotted lines represent the LOP specifications.
Figure 4.5 Diameter versus workfunction of 10 nm Silicon nanowire device which satisfy the LOP and HP specifications.
Figure 4.6 Ratio Ion/Ioff of 10 nm silicon nanowire structure with different diameters and work functions.
Figure 4.7 Ratio ∆VT/ VT of the nanowire devices versus diameter for different workfunction. The dashed line in the figure indicates the shift VT specifications.
Figure 4.8 Optimized diameter versus workfunction of 10 nm Silicon nanowire FET for HP25 node. The colored region shows the optimized region for the device performance.
Figure 4.9 Optimized diameter versus workfunction of 10 nm Silicon nanowire FET for LOP25 node. The colored region shows the optimized region for the device.
Figure 4.10 Drain current versus gate voltage characteristics for the optimized device. Drain voltage is selected to be Vd=0.8 V (●) and Vd=0.05 V (○).
Figure 4.11 Figure4.28 Simulated drain current versus drain voltage characteristics for the optimized device.
Figure 4.12 Reduction of body thickness and oxide thickness with future technology node [3].
Figure 4.13 Simulated Id-Vg curve according to HP45 node parameters. Workfunction was adjusted (Φ=4.487eV) to achieve required off state current.
Figure 4.14 Simulated Id-Vg curve according to HP32 node parameters. Workfunction was adjusted (Φ =4.404 eV) to achieve required off state current.
Figure 4.15 Simulated Id-Vg curve according to HP22 node parameters. Workfunction was adjusted (Φ =4.347 eV) to achieve required off state current.
Figure 4.16 Simulated Id-Vg curve according to HP14 node parameters. Workfunction was adjusted (Φ = 4.229 eV) to achieve required off state current.
Figure 4.17 Simulated subthreshold slope values for future technology nodes.
viii Figure 4.18 Simulated DIBL values for future technology nodes.
Figure 4.19 Simulated ON current values (solid) for the future technology nodes compared to target ITRS ON current values (dashed).
Figure 4.20 Simulated Ion current values for Circular nanowire (CNW) FET (○) and Double Gate (DG) FET (□) using Quantum Drift Diffusion (QDD) transport model along with ITRS target (●/■) current values.[3].
Figure 5.1 NMOS threshold voltage variation with channel doping due to random discrete dopant fluctuation [1].
Figure 5.2 Device structure for the (a) Gate All Around silicon nanowire transistor and (b) Dual Gate transistor (FinFET).
Figure 5.3 Random placement of dopant at concentration of 2x1019/cm3 at channel length of 20 nm and thickness 5 nm [1].
Figure 5.4 Simulated threshold voltage (Vth) versus channel doping (NA) at Vd= 50 mV for different channel lengths reported by Chiang [3].
Figure 5.5 Simulation result for threshold voltage variation with channel doping for silicon nanowire FET (solid) and a double gate FET (dashed) [1].
Figure 5.6 Threshold voltage variation of FinFET structure with varying body thickness by Xiong & Bokor. [1].
Figure 5.7 Simulation result for threshold voltage shift with diameter for silicon nanowire FET (solid) and a double gate transistor (dashed) [1].
Figure 5.8 Threshold voltage variation with gate length for FinFET structure reported by Xiong and Bokor [1].
Figure 5.9 Simulation results for threshold voltage variation with gate length for SiNW and FinFET device [1].
Figure 5.10 Threshold voltage variations for FinFET with varying oxide thickness reported by Xiong and Bokor [1].
Figure 5.11 Simulation results for threshold voltage variation with inverse oxide thickness for SiNW and FinFET [1].
Figure 5.12 Variation of ON current with body thickness for a FinFET device reported by Xiong & Bokor [1].
ix Figure 5.13 Simulation result for ON current variation with diameter for SiNW and FinFET devices [1].
Figure 5.14 Variation of OFF current with body thickness for FinFET structure reported by Xiong & Bokor [1].
Figure 5.15 Simulation results for OFF current variation with diameter for SiNW and FinFET devices [1].
Figure 5.16 Simulation results for ON/OFF current variation along diameter for silicon nanowire and FinFET devices[1].
Figure 5.17 Simulation results for ON current variation along gate length for silicon nanowire FET.
Figure 5.18 Simulation results for OFF current variation along gate length for silicon nanowire FET.
Figure 5.19 Variation of DIBL with body thickness for a FinFET structure as reported by Xiong & Bokor [1].
Figure 5.20 Simulation results for DIBL variation with diameter for SiNW and FinFET devices [1].
Figure 5.21 Variation of subthreshold slope with body thickness for FinFET structure reported by Xiong & Bokor [1].
Figure 5.22 Simulation results for subthreshold slope variation with diameter for SiNW and FinFET [1].
Figure 5.23 Simulation results for DIBL variation with oxide thickness for silicon nanowire device.
Figure 5.24 Simulation results for subthreshold slope variation with oxide thickness for the SiNW device.
x
List of Tables
Table 1.1 Nanowire Data Compared with Bulk Data for Silicon Nanowire MOSFETs [38].
Table 2.1 Classification of Simulation Models according to Channel Lengths [5].
Table 2.2 Comparative table for simulated and experimental silicon nanowire FET devices.
Table 4.1 Long-term ITRS Roadmap Specifications for MOSFET Scaling [2].
Table 4.2 Parameters for HP25 and LOP25 Technology Nodes as per ITRS Report [2].
Table 4.3 Parameters for future technology nodes [2].
Table 5.1 Physical and Electrical Parameters of the Silicon Nanowire Device.
Table 5.2 Process variation sensitivity comparison for Silicon Nanowire FET and FinFET devices around baseline structure.
xi Chapter 1
Introduction
The journey of the development of the metal-oxide-semiconductor field-effect-
transistor (MOSFET) started some seventy years ago. Fundamental concepts and design
of a MOSFET were first described by Julius Edgar Lilienfeld of Brooklyn and
Cedarhurst, NY in two of his first three patents [1] [2]. However it was not until 1960
that the first MOSFET was fabricated and demonstrated by Dawon Kahng and Martin
Atalla at the Bell Labs [3]. Making use of a thermally grown silicon dioxide layer to
passivate the surface, this device did not suffer from the high density of surface states
(interface and oxide traps), which had affected the performance of the bipolar junction
transistor (BJT) proposed in 1948 by Shockley and was considered one of the most
important and significant technological advance for that period [4]. The Kahng and Atalla
paper [3] also reported reduction and stabilization in the device’s leakage current and that
the transistor was easy to integrate with the planar fabrication process. This discovery led to MOS transistor integration and the development of the silicon MOSFET integrated circuit manufacturing industry. Later, in 1962 an important idea was conceived by
Wanlass at Fairchild, which was the CMOS (Complementary MOS) concept of
integrating p-channel and n-channel MOSFETs [5]. The development of a passivating
oxide on the semiconductor surface was extremely important in reducing the power used by MOS transistors, which was one of the reasons MOS was lagging behind bipolar
1 technology. By late 1964 the first commercial MOSFETs were announced by Fairchild and RCA.
The dramatic development of the MOSFET fabrication technology enabled the growth of the modern integrated circuit and computer industry [6]. MOS technology required fewer processing steps than bipolar technology, which translated into lower fabrication costs and higher yield. Also, while bipolar transistor technology could not be scaled down in size with harming transistor performance characteristics, MOSFETs could be scaled down without compromising on performance. This led to increased growth of
MOSFET technology and by the end of 1970 it had taken over bipolar as the dominant choice for integrated circuits.
1.1 Moore’s Law
Moore’s Law is one of the ubiquitous concepts associated with dramatic rise of
the semiconductor industry over last few decades. Gordon E Moore made an empirical
observation in 1965 that ‘The complexity for minimum component costs has increased at a rate of roughly a factor of two per year.....That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000. I believe that such a large circuit can be built on a single wafer’ [7]. Though Moore’s prediction made in
1965 envisioned only the next ten years, it has remained relevant over the last forty years.
Moore’s Law is illustrated in Fig. 1.1 and shows the trend of increasing transistor count with each new microprocessor technology. The consequences of Moore’s Law are ever increasing processing power while decreasing costs because of higher levels of
2
Figure 1.1 Increasing number transistors with each new microprocessor technology [50]
transistor and circuit integration. The latest Intel Duo-Core processor now employs about
one billion transistors. Through technology improvements and innovations like strained
Si channels [8], high – k gate dielectric [9] [10], metal gates [10] and the development of
novel device designs like ultra thin body (UTB) transistors [11], FinFETs and other Dual-
Gate transistors [12], Tri-gate transistors [13], and Silicon nanowire gate all around
(GAA) transistors [14], it is possible that Moore’s Law will continue through next
decade.
3 1.2 MOS Transistor
The MOSFET is the basic building block for very large scale integration (VLSI)
circuits and in microprocessors and dynamic memories. Since current in a MOSFET is
primarily transported by carriers of one polarity (e.g., electrons in an n-channel device),
Figure 1.2 3-D view of a basic n-channel MOSFET.
the MOSFET is usually referred to as unipolar or majority carrier device. The basic
structure of a MOSFET is shown in Fig. 1.2. It is a four terminal device with the
terminals designated as gate (G), source (S), drain (D), and substrate or body (B). An n-
channel (p-channel) MOSFET consists of a p-type (n-type) substrate into which two n+
(p+) regions, the source and the drain are formed. The gate electrode is usually made of heavily doped polysilicon and is separated from the semiconductor channel by a thin gate oxide layer. Application of a positive (negative) voltage at the gate terminal for n-channel
(p-channel) MOSFET leads to accumulation of negative (positive) charge at the oxide- silicon interface, creating a channel for current conduction. The gate is capacitively
4 coupled to the channel via the gate electric field and there is effectively no gate drain
current. The transistor effect is achieved by modulating gate electric field using gate-
source bias leading a MOS transistor to be popularly known as the ‘field effect
transistor’.
1.3 Scaling of MOSFETS
It has been now forty five years since the invention of the MOSFET. During these years we have seen rapid and steady progress in the development of integrated-circuit
(IC) technology. The main driving force behind this growth has been the down scaling of the MOSFET’s dimensions, which was first proposed in 1974 by Dennard et. al. [15].
Starting with gate lengths of 10µm in 1970, we have reached about 32nm in 2007
(currently known as 65nm technology node) corresponding to approximately a 15% reduction each year [16].
Two types of scaling mechanisms are commonly used, known as constant voltage scaling and constant electric field scaling as summarized in Fig. 1.3. Constant voltage
scaling is purely a geometric approach where the power supply is kept constant while the
transistor’s dimensions are scaled down by a factor α. However, reducing the channel length and gate dielectric thickness increases electric field in the channel. This initially improves the mobility in the channel, but as the field starts to increase beyond 1MV/cm, it starts decreasing again due to saturation of the carrier velocity, which reduces the current gain. By contrast, the constant field scaling approach involves reducing the transistor’s dimensions along with power voltage supply in order to maintain the electric field strength in the channel and ensure the same transistor physics and operation. As a
5 result, the power per transistor decreases quadratically, as shown in Fig. 1.3, so the power
density (P/L*W) remains constant instead of exploding as in constant voltage scaling
Figure 1.3 Constant field scaling and constant voltage scaling parameters [49].
approach. However the transistor’s speed (fT) only increases linearly. Current density also increases linearly (I/W2) rather than quadratically. Because of its benefits, the computer
industry essentially followed constant voltage scaling for the period from 1973 to 1993,
best reducing the supply voltage only twice instead of continuously with each new
generation. From 1993 to 2003, to the power supply voltage decreased with every new
technology generation, although not as rapidly as the constant electric field scaling
6 approach required [17]. Fig. 1.4 sums up the industry trends in device parameters with channel length scaling. It is apparent that the drain voltage (V) has not been decreasing as fast as channel length (L), which means that the transistor’s electric fields have been increasing as opposed to staying constant for a constant field scaling approach.
Figure 1.4 Industry-trend scaling (points) contrasted with classical scaling (dashed lines) [18].
7 1.4 Scaling Issues and Approaches
Over the past three decades, by reducing the transistor lengths and the gate oxide thickness along with decreasing the supply voltage as seen in Fig. 1.5, there has been a steady improvement in transistor performance a reduction in transistor size and a reduction in cost per function. The more an IC is down scaled, the higher becomes its packing density, the higher its circuit speed, and the lower its power dissipation [15].
However, as CMOS dimensions start approaching the nanometer regime (<100 nm), we
Figure 1.5 History and trends for supply voltage (Vdd), threshold voltage (Vt) and oxide thickness (tox) versus channel length for CMOS logic technologies [19].
8 start seeing new effects in the device performance arising from new physical
phenomenon. To maintain the rate of improvement in device performance with continued down scaling, modifications to device design and fabrication are required. In particular, a collection of undesirable phenomenon problems arises that are collectively called “short channel effects” which impedes further progress in transistor downscaling.
1.4.1 Short Channel Effects
One of the major challenges in transistor scaling are the “short channel effects”
which become more visible with gate lengths less than 100 nm. One short channel effect
is a decrease in threshold voltage as channel length is reduced. As MOSFETs shrink in
dimensions, the source and drain regions move closer to each other. In a long channel
device, the source and drain regions are far apart and sufficiently separated that their
depletion regions have no effect on the potential in the central region under the gate as
seen in Fig 1.6(a). In a short channel device, however, the source-drain distance is
Figure 1.6 Potential contour for a (a) long channel device and a (b) short channel device [20]
9 comparable to the MOS depletion width in the vertical direction, and the source-drain potential has a strong effect on the surface band bending under the gate [20] as seen in
Fig 1.6(b). Since some of the charge is shared between the source and the drain in the channel, the net effective charge being controlled by gate is reduced, lowering the threshold voltage. Fig. 6 (a) and (b) show simulation results of the potential profiles present in both the long channel and short channel devices, respectively. From the Fig.
1.6, it can be seen that in short channel lengths the electric field under the gate has a two
Figure 1.7 Short-channel threshold roll off: measured low- and high- drain threshold voltage of n- and p- MOSFET’s versus channel [20].
10 dimensional nature. Fig. 1.7 shows an example of the threshold voltage roll-off for n- and p-MOSFETs, which affects the circuit design as process variations in the gate length lead to variation in threshold voltage. Also, as we continue to down scale, new techniques are required to obtain adequate control and reproducibility in the threshold voltage for subsequent technology nodes.
A second short channel effect occurs when a high drain bias is applied to a short channel device; the barrier height at the source end of the channel is by the drain bias resulting which reduces the threshold voltage as seen in Fig. 1.8. This effect is known as
Drain Induced Barrier Lowering (DIBL). For the short channel device the drain voltage has an effect on the electron barrier height which appears as a variation in the threshold voltage with drain bias. This effect worsens with reduction in the channel length ultimately leading to the punch through condition when an excessive drain current flows
Figure 1.8 Band diagram for a (a) long channel and a (b) short channel device.
11 and the gate loses all control. Since the power supply voltage is also scaled down
following the constant field scaling approach, there is a reduced gate voltage swing available so that the net effect of the DIBL phenomenon is to cause increased off-current leakage for the transistor.
A third short channel effect is associated with the transistor’s turn-off characteristics. The subthreshold slope (SS) is defined as the change in gate voltage required produce a decade change in drain current (units of mV/dec). As we scale down the transistor with decreasing channel lengths, the subthreshold slope degrades (increases in magnitude from its theoretical minimum of 60mV/dec [20]). Ideally the subthreshold slope should be as small as possible to quickly turn on or off the transistor but the device’s physics limits it to about 60 mV/dec. Subthreshold slope degradation causes increased off-state leakage current and induces another process variability in device and circuit fabrication.
1.4.2 Gate Oxide
Following the constant field scaling approach, the gate oxide (SiO2) thickness has been scaled down in conjunction with gate length. This down scaling helps to keep short channel effects under control and to maintain electrostatic integrity as shown in Fig. 1.5 with the gate oxide thickness now of the order of 1 nm. However, an oxide thickness of
1.2 nm, which is used in the 90 nm logic technology comprises only a five atom thick oxide layer which means we are approaching a physical limit beyond which carrier tunneling current through the gate increases dramatically. As can be seen from Fig. 1.9,
12 the gate oxide tunneling current increases exponentially as the gate oxide thickness
decreases so that it approaches the drain on-current (Ion) at an oxide thickness
Figure 1.9 Calculated gate oxide tunneling current vs gate voltage for different oxide thickness [19] of 1 nm. Since the gate oxide leakage current is an undesirable parasitic current, this is clearly an undesirable circumstance. Another issue associated with an excessively thin gate oxide is the loss of inversion charge, which leads to smaller gate capacitance and so smaller transconductance [19]. Quantum mechanics dictates that the peak of the inversion
charge density lie at a small distance from the Si-SiO2 surface. This decreases the
depletion capacitance and effectively reduces the total gate capacitance. Similarly, a third
effect, known as the polysilicon gate depletion effect, also occurs with a thinner gate
13 oxide. A thin space charge forms in the heavily doped polysilicon gate near the gate oxide surface, which acts to reduce the overall gate capacitance [19]. For a polysilicon doping of 1020 /cm3 and a 2-nm oxide, about 20% of the inversion charge is lost at 1.5 V gate voltage because of the combined effects of polysilicon gate depletion and inversion- layer quantization [19].
1.4.3 New Materials
Scaling of MOSFET transistors has led to increased performance due to the gate length reduction. However, intrinsic semiconductor properties, like electron and hole
Figure 1.10 Strained silicon grown over a silicon germanium (SiGe) layer [22]. mobilities, for the silicon lattice cannot be scaled. Since they are unaffected by scaling, beyond the 90 nm technology node new innovations in transport have been sought to increase the channel carrier mobilities and the MOSFET performance. One approach has been to utilize strain using silicon grown on an underlying SiGe layer [21]. In strained silicon a layer of SixGe1-x is initially grown during epitaxial growth by adding a few Ge atoms near the wafer’s crystalline surface. Since Ge has a larger lattice constant (5.65 Å) than Si (5.4Å), the resulting crystal structure is larger so that a subsequent silicon layer
14 grown on the SiGe is strained. The top Si layer grown over the SixGe1-x surface is in
tensile strain as the Si atoms try to align according the to the expanded lattice as shown in
Figure 1.11 (a) Increased mobility and (b) drain current with strained Si technology [23]
Fig. 1.10. This strain in the Si causes a reduction in the effective electron (hole) mass and increased electron (hole) mobility as shown in Fig. 1.11(a). This increased mobility
15 improves the transistor’s switching delay and leads to a higher transconductance and
larger drain current as can be seen from Fig. 1.11(b). Intel has reported an increase of 10-
20% in the MOSFET’s drive current with strained silicon technology for a 50 nm long
channel [21].
Problems associated with thinning of the oxide layer presents one of the biggest
challenges for continued MOSFET down scaling since the physical limits of oxide scaling are being approached with only few atomic layers for the current technology node. As a result, it is imperative to use an alternate gate dielectric to solve the increasing gate leakage current problem associated with thinning the gate oxide (SiO2). Using a
high-k dielectric allows use of a thicker dielectric while providing same gate capacitance
and so equivalent transistor performance. The gate capacitance for a parallel plate
kffεffffffffAfffffff capacitor is C = 0 where k is the native dielectric constant (=3.9 for SiO ), ε is d 2 0
permittivity of free space (=0.0885 pF/cm), A is the area of the capacitor and d is the
kffff dielectric thickness. To maintain the same gate capacitance, the same ratio is needed. d
kffffffffffffffffffffff Thus, using a high-k dielectric allows a thicker dielectric given by d = d B high @ k . high @ k ox 3.9
For a high-k dielectric with khigh-k=16 and dox=1nm, then the thickness for the high-k of
dhigh-k ~4nm. After almost a decade of research, hafnium-oxide based materials such as
HfO2, HfSixOy, HfOxNy, and HfSixOyNz, (kHfO2 ~ 25) have emerged as a leading candidate
to replace SiO2 gate dielectrics in advanced CMOS applications [24].
Downscaling the gate dielectric also requires replacing polysilicon as the gate electrode material. Metal gate technology involves no poly depletion effects and offers
much better threshold voltage control [24]. Over last few years, research in metal gate
16 technology has identified several promising candidates, such as W, Ti, Mo, Nb, Re, Ru and their binary or ternary derivatives such as WN, TiN, TaN, MoN, and TaSiN [25]. An alternative to metal gates is to fabricate fully silicided gates. It involves converting poly
Si into silicides which are in direct contact with the gate dielectric after their fabrication, e.g. MoSi, WSi, TiSi, HfSi, PtSi, CoSi, and NiSi [24]. Recently, Intel announced plans to introduce high-k dielectric and metal gates for their 45nm technology node, which will be in production by the end of 2007 as shown in Fig. 1.12 [26].
Figure 1.12 High-k and metal gate technology proposed by Intel (production year: 2007) [26]
1.5 Issues at Nanoscale Level
Shrinking of MOSFETs beyond 50-nm-technology node requires additional innovations to deal with barriers imposed by fundamental physics. The classical approach used to scale the conventional MOSFET starts to fail at such a small scale and new issues emerge such as short channel effects which are important to overcome to continue the scaling trend. The issues most often cited are: 1) current tunneling through thin gate
17 oxide (discussed above); 2) quantum mechanical tunneling of carriers from source to drain [27-28]; 3) threshold voltage increase due to quantum confinement [29]; and 4) random dopant induced fluctuations [48].
As the gate length is reduced to around 10 nm level, gate control over the channel region decreases and there is increased source-drain tunneling of electrons. This leads to
Figure 1.13 Degradation of subthreshold slope due to source-drain tunneling at gate lengths below 10nm. [27]
increased off current and degradation in the subthreshold slope as shown in Fig. 1.13 and
1.14. It is still a debatable topic that whether source-drain tunneling or the device’s electrostatics degradation will be the limiting factor for scaling. A simulation study by
Lundstrom et al. revealed that source-drain tunneling might set the scaling limit well below 10 nm [28]. As can be seen from Fig. 1.13, source-drain tunneling significantly
18 degrades the subthreshold slope S at gate lengths less than 10nm, and increases the off- state current as seen in Fig. 1.14.
Figure 1.14 Off current increase with decreasing gate length due to source-drain tunneling for a dual gate device at Vds=1V, Tsi=2nm, tox=1nm [27].
MOSFET’s with gate lengths approaching 10 nm need to have a thinner channel layer to ensure adequate device turnoff. With new device designs like ultra thin body
(UTB) FET’s where the MOSFET is fabricated on a very thin silicon layer on an oxide substrate (SOI), it is imperative to have a body thickness below 10 nm to maintain electrostatic integrity. Due to quantum confinement effects in UTB-FETs we start to see a threshold voltage increase with reducing channel width as shown in Fig. 1.15 [29]. The quantum mechanical narrow channel effect occurs because electrons in the inversion layer are not only located away from the surface but also occupy discrete energy levels in the channel. The lowest energy level is some finite energy higher above the bottom of the conduction band due to energy quantization due to lateral confinement. Hence, a larger surface potential is required to populate the inversion layer, which increases the threshold
19 B voltage [30]. The classical threshold condition ψ s = 2 ψ b (ψ s = surface potential) can be
B modified to ψ s = 2 ψ b +ΔψQM to include the shift of inversion charge density away
CL kTfffffffff Qfffffiffffffff from the surface where Δψ QM = lnh QM i [30]. Thus the threshold voltage shift due fgq Q l i m j k dfffVgffffffffff B B to quantum effect can be calculated as ΔV t = Δψ QM = m Δψ QM where m is the dψ s
Figure 1.15 Threshold voltage increase with reducing SOI channel width [29].
body-effect coefficient usually between 1.2 and 1.5 [30]. As can be seen in Fig. 1.15 for a thin SOI silicon film thickness, the quantum effect becomes important as the silicon thickness is reduced below ~5nm. Random fluctuation of the number of dopant atoms in the channel was predicted as a limiting factor in transistor scaling back in 1970’s [31].
Recall that constant field scaling requires the substrate doping to rise at the rate of scaling factor α (see Fig. 1.3). However, in a deviation from constant field scaling, undoped
20 channels have been adopted for FET’s below 100 nm gate length due to statistical variation in the doping level called random dopant induced fluctuation. Fig. 1.16 shows variation in Id-Vg curves with random dopant fluctuation compared with the conventionally doped device for 24 MOSFET’s with different random “atom” distributions for W=50 nm, L=100 nm, tox=30 Å , and an average uniform substrate doping of 8.6x1017 cm-3 [30]. Variation in threshold voltage can be analytically shown to
Figure 1.16 Variation in Id-Vg curves with different discrete dopant distribution for 24 devices. Solid dots indicate the conventionally doped device. It shows 20- 30mV variation along gate voltage, 30mV shift in subthreshold region and 15 mV shifts in linear region [30].
wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww 3fff 2 ffqffffffffs NffffffafffBfffffffWffffffffdmffffffff fffxffffsfffffff be σ Vt = B 1 @ [30], where Wdm is maximum gate depletion Cox 3BLBW fgWdm width, xs is the width of low impurity region, Na is substrate doping, L is the channel length, W is channel width and Cox is oxide capacitance. While channel doping has historically been used to adjust the MOSFET’s threshold voltage metal gates with appropriate work-function are now used to adjust the threshold voltage.
21 1.6 Non Classical Device Structures
As the MOSFET scaling process continues the International Technology
Roadmap for Semiconductors (ITRS) anticipates that the semiconductor industry would require channel lengths in the range of 10 nm by 2015 [16]. Besides the introduction of new materials and improving bulk MOSFET performance, newer device concepts are likely to be required to continue scaling into the sub-10nm gate length region [25][32].
Advanced MOSFET structures like ultrathin-body (UTB) FET, Dual-gate FET, FinFET,
TriGate FET and Gate All Around (GAA) FET offer the opportunity to continue scaling beyond the bulk because they provide reduced short channel effects, a sharper subthreshold slope, and better carrier transport as channel doping is reduced.
1.6.1 Ultra Thin-Body Single Gate MOSFET
In this section we describe the UTB single gate MOSFET device structure as shown in Fig. 1.17. The basic concept of this device is to have a thin silicon channel with an underlying, insulation oxide to eliminate leakage current paths through the substrate and to reduce parasitic capacitances to enhance the device’s speed. Since most of the off - state current flows through the bottom of the body, it is desirable to replace the semiconductor substrate with an insulating dielectric. However thicker self aligned source and drain structures are required to minimize parasitic source/drain series resistance [33]. As an example, Fig. 17(b) shows a TEM picture of a 40 nm gate length
UTB n-MOSFET with 20 nm thick silicon body and 2.4 nm thick gate oxide [34]. The device shows superior short channel effects with a subthreshold slope of 87mV/dec.
22
Figure 1.17 (a) Schematic diagram for UTB MOSFET [33] (b) TEM image of a UTB device [34]
Raised poly-Si S/D contact regions (not shown) were employed to reduce the parasitic resistance of the device [34]. Drain currents of 400 µA/µm were achieved at a drain voltage of 1V and Vg-Vt=1.2V.
1.6.2 Dual-Gate FET / FINFET
A dual-gate device FET (DG FET) structure allows for more aggressive device scaling as short channel effects are further suppressed by doubling the effective gate control. There have been several variations proposed for DGFET structure, but most of them suffer from process complexities, among these, the FinFET has emerged as the most practical design as shown in the Fig. 1.18 [25]. The channel consists of a thin vertical fin around which the gate wraps on three sides. The FinFET is a double gate FET
23
Figure 1.18 Dual-Gate FET structure (left) and a FinFET structure (right)
since the gate oxide is thin on the vertical sidewall but thick on the top. The fin width is an important parameter for the device as it determines the body thickness and short channel effects depend on it. For effective gate control it is required that the fin width be
Figure 1.19 More ideal subthreshold slope/DIBL evident for double gate (DG) FET as compared to a single gate (SG) FET [47]. half the gate length or less [25]. Because of the vertical nature of a FinFET channel, it has
(110) oriented surfaces when fabricated on a standard (100) wafer. This crystal orientation leads to enhanced hole mobility but degraded electron mobility [25]. The
24 primary advantage of the FinFET over the planar MOSFET is that it offers reduced short channel effects such in Fig. 1.19. It is evident from the figures that a DGFET offers more
Figure 1.20 (a) Id-Vg (top) and Id-Vd curves (b) SEM image and gate profile (c) TEM image of a FinFET [35]. ideal subthreshold slope and better DIBL characteristics. Fig. 1.20 shows an example of a
FinFET with 10 nm fin width and 20 nm gate length with Tox=2.1 nm. For this device, the NMOS drive current is 365 uA/um at Vg-Vt=1 V and Vd= 1 V. The relatively low current is the result of (110) channel orientation and not using a raised S/D [35]. From experimental data it has been found that when the ratio Lg/Wfin is larger than 1.5, subthreshold slope and DIBL are less 100 mV/dec and 0.1 V/V respectively [35]. As a result the channel length is scaled down, the silicon body thickness (fin width) must also be reduced, which poses a fabrication challenge.
25 1.6.3 TriGATE FET /OMEGA-GATE FET
The Tri-Gate and Omega-Gate FETs are multi-gate transistors having three sided gate structures as shown in Fig. 1.21. Omega-Gate FET has the gate extending into the substrate on the sides creating an effective fourth gate which provides better gate control than a Tri-Gate FET.
Figure 1.21 Schematic diagram for a (a) TriGate FET [36] (b) Omega-Gate FET [37]
Intel is pushing with Tri-Gate FET design [36] while Taiwan Semiconductor
Manufacturing Company (TSMC) is focusing on Omega-Gate FET for future device designs [37].
26 1.7 Silicon Nanowire Technology
Semiconductor nanowires are cylindrical single crystal structures with a diameter of a few nanometers that exhibit several interesting and novel properties because of their small one dimensions and confinement in two dimensions. The nanowire approach to nanoscale MOSFET fabrication offers the opportunity for ultimate scaling of the
MOSFET using Gate All Around device structures (GAA-FET) as shown in Fig. 1.22.
Since the addition of extra gates (two or more) improves MOSFET performance, including reducing short channel effects, the GAA FET is attractive for very short channel MOSFET.
Figure 1.22 SEM image of (a) 200 nm long silicon nanowire and (b) after gate electrode definition ; 4 nm grown oxide followed by 130 nm amorphous silicon. [51]
A number of attempts have been made at fabricating discrete silicon nanowire transistors using both back gate [38] [39] and gate-all-around (GAA) device geometries
[14] [40] [41] [51]. Shown in Fig. 1.23 is an example of a back gate nanowire MOSFET with a 5 nm silicon nanowire [38]. Research groups have also successfully fabricated
27 integrated circuits using nanowires as building blocks [42]. Much of the recent (since
2000) research work on fabrication of nanowire devices has been carried out at Harvard
University, USA. The research group led by Charles Lieber at Harvard has done some pioneering work in this area. They were the first to report controlled doping of silicon nanowire devices [43] besides reports of diameter controlled synthesis of nanowires [44]
[45], multishell Si-Ge nanowire heterostructures [46] and also integrated circuits .
Figure 1.23 (a) Schematic of the back gate SiNW FET (b) TEM image of a 5nm diameter SiNW [38].
28 Fig. 1.23 shows one of the first silicon nanowire transistors, a back gated silicon nanowire transistor reported by Cui et al. [38]. The nanowire device was grown via vapor-liquid-solid (VLS) mechanism using gold nanoclusters as the catalysts as shown in
Fig. 1.24. This fabrication method leads to high-quality single-crystal nanowire growth with well-controlled diameter by using well defined Au nanoclusters. Silane (SiH4) was used as the vapor phase reactant as shown in the Fig. 1.24 [44]. The fabricated nanowires
Figure 1.24 Size-controlled synthesis of SiNW from Au nanoclusters for diameter control [44]. were deposited onto oxidized silicon substrates with electrodes separated by about by
800-2000 nm. Thermal annealing was done to improve the contact and passivate Si-SiOx traps as can be seen in the current measurements (Fig. 1.25).
An important observation from the results is that there is an improved mobility in nanowire devices. Hole mobility is estimated to be 1000 cm2/V.s, which is considerably larger than bulk hole mobility (450 cm2/V.s). Silicon nanowire devices also exhibit higher transconductance and more ideal subthreshold behavior. Table 1.1 shows the comparison between converted nanowire MOSFET data and a bulk silicon device. Note the improved on current, reduced off current, lower subthreshold slope and improved transconductance.
Recently, there have been reports of successful fabrication of gate-all-around nanowire MOSFET devices in the literature [14]. The GAA structure is reported to lead
29
Figure 1.25 Id-Vd curve for the back gate silicon nanowire transistor [38]. Red curve is after annealing.
Table 1.1 Nanowire Data Compared with Bulk Data for Silicon Nanowire MOSFETs [38].
to better gate control and better short channel performance. Fig. 1.26 below shows a
TEM image of a reported 200 nm long nanowire with 4 nm diameter and 9 nm thick oxide [14]. The fabrication process started with a p-type silicon-on-insulator (SOI) wafer.
30 Active areas were etched out down to the buried oxide to form a silicon fin structure. The patterned silicon was then oxidized in dry O2 which resulted in two nanowire cores, one at the bottom and another at the top of fin. The top nanowire was etched out and bottom one was released from the underlying oxide using a wet etch process. The release was followed by a 9 nm gate oxide and 130 nm α-Si deposition to form the gate dielectric and polysilicon gate electrode.
Figure 1.26 TEM image of fabricated GAA silicon nanowire transistor structure [14].
The Id-Vd and Id-Vg curves for the device are shown in Fig. 1.27 for fabricated 5 nm diameter and 180 nm channel length SiNW FET shows ON-state currents of 1.5 and 1 mA/µm for n- and p-FETs, respectively, and OFF-state current < 1nA/µm at 1.2 V of
31 operating voltage. The electron and hole mobilities were estimated to be ~ 750 cm2/V.s and ~ 325 cm2/V.s, respectively, for holes and electrons, which are lower than other
Figure 1.27 Id-Vd and Id-Vg curves for a 5 nm diameter GAA silicon nanowire transistor [14].
reported nanowire results [38]. However, the subthreshold characteristics of n-FET were nearly ideal with SS ~ 63 mV/dec (66 mV/dec for p-FET) and the DIBL were also very good, ~ 10 mV/V (20mV/V for p-FET) even with a 9 nm thick gate oxide [14].
32 1.8 Purpose of Thesis
The purpose of this thesis is to use device simulations to examine the performance of the GAA Silicon Nanowire FET. The TCAD tool used is custom software (NanoWire) developed at Purdue University to simulate short channel silicon nanowire devices while taking into account quantum effects associated with the nanoscale. Ballistic transport in the FETs channel was chosen for device modeling design which provides an upper performance limit. It was observed experimentally that fabricated nanowire structures of gate lengths down to 30 nm operate at 20-30% of the ballistic limit. For this work, the subthreshold characteristics and other device performance characteristics for the simulation devices will be compared to the experimental results where they are available.
Subsequently, various comparative studies will be performed with dual gate MOSFETs
(FinFETs) which have also been theoretically and experimentally reported. For this work, the NanoMOS software from Purdue will be used. Physical parameters such as the oxide thickness, gate length, silicon thickness and channel doping will be varied and the results compared with experimental results reported for the dual gate FETs. Threshold voltage, subthreshold slope, DIBL and other key electrical parameters were extracted and compared. A device optimization study will also be conducted for the 25 nm node to determine the extent of a device design window including device performance for both
High Performance (HP) and Low Operating Power (LOP) technologies. In this thesis we will investigate the advantages and characteristics exhibited by silicon nanowire transistors and compared to dual gate MOSFETs.
33 1.9 Organization of Thesis
This thesis is organized into six chapters. Chapter 1 has provided a brief introduction into recent developments in silicon MOSFET device designs and the effects of downscaling of the channel length on device performance. Also introduced has been the concept of multigate and silicon nanowire MOSFET technologies. Chapter 2 will discuss the software tool used for the simulations including the NEGF transport model along with some of the most relevant equations. Chapter 3 discusses the effects of varying the nanowire MOSFET physical parameters and compare the results with those for a dual gate transistor. In particular, short channel and quantum effects will be discussed. Chapter 4 describes the optimization of the device for HP25 and LOP25 technology node and the performance of the nanowire transistor for future nodes. Chapter
5 discusses a process variation study for the silicon nanowire transistor as compared to a dual gate transistor. Chapter 6 provides conclusions and some suggestions for future work.
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40 Chapter 2
Simulation Software: Theory and Preview
Simulation of electronic devices generally involves self consistent solution of the electrostatic potential and carrier distribution inside the device. Over the years device engineers have improved our collective knowledge of carrier transport and semiconductor physics. Earlier treatment of electrons and holes as semiclassical particles with an effective mass was good enough to predict semiconductor device behavior and the drift- diffusion equation was adequate to describe carrier transport. Today, as we stand at 65 nm node and begin to enter 45 nm technology node, MOSFETs have shrunk to nanoscale dimensions, which has required a re-examination of our approach to device modeling. In particular, the properties of materials can be altered using strain, heterojunctions and computational grading are possible, and quantum effects start to show up in the nanometer regime. As a result, the conventional drift-diffusion and Boltzmann equations do not capture the increasingly important role of quantum mechanics in modeling transistors in the ten nanometer regime. For this reason, a more sophisticated analysis of the device physics is needed, such as the non equilibrium Green’s Function (NEGF) approach, to model devices all the way to ballistic level (< 10 nm) [1]. The NEGF transport model is by far the most rigorous approach among existing quantum transport models and is the approach utilized in this modeling study [2][3][4].
41 2.1 Classification of Transport Models
Table 2.1 provides a classification of the existing transport models and their applicability according to channel length for field effect transistor modeling. Generally, when channel length is larger than 0.1 µm, macroscopic variables can be applied such as electron density, velocity, energy and electron temperature. Among semiclassical transport models appropriate for this realm, the drift-diffusion model, the hydrodynamic model and six moment equation can be used for modeling FETs with long channel lengths (L > 0.1 µm) [5]. For short channel lengths, a quantum mechanical description is needed and the density gradient and effective potential approach need to be used. When the channel length is less than 0.1 µm, the Boltzmann transport equation (BTE) must be
Table 2.1 Classification of Simulation Models according to Channel Lengths [5].
L > 0.1 µm Intermediate L<10 nm
- drift – diffusion - Monte Carlo - analytic solution simulation (from ballistic BTE) Semi-classical - hydrodynamics - direct calculation - six moments equation - density gradient - NEGF - NEGF ( no scattering) - effective potential - Wigner function Quantum mechanical - Schrödinger - Pauli master equation equation
42 solved by the Monte Carlo method or by a direct method. At short channel lengths ( <0.1
µm) the NEGF, Wigner and Pauli master equations can be used to describe quantum effects [5]. As we enter the regime of ultra scaled channel lengths for the silicon
MOSFET in the range of 10 nm, it becomes imperative to use the NEGF transport model.
The conventional transport theories based on BTE focus on scattering dominated transport; however for nanoscale MOSFETs, these may operate in a quasi-ballistic transport regime where scattering effects become less important and carrier transport approaches purely ballistic transport. To simulate nanoscale devices, the NEGF provides best framework available.
2.2 Simulation Software Description
The simulation software used here for nanoscale nanowire MOSFET device modeling is based on the work done by Jing Wang et al. and his colleagues at Purdue
[3][4]. The tool (NanoWire) is a 3D self-consistent, quantum, silicon nanowire simulator based on the effective mass approximation. The calculation involves a self-consistent solution of a 3D Poisson equation and a 3D Schrödinger equation with open boundary conditions at the source and drain contacts. Using the finite element method (FEM), the
3D Poisson equation is solved initially to obtain the electrostatic potential throughout the device. At the same time, the 3D Schrödinger equation is solved by a
(coupled/uncoupled) mode space approach, which provides both computational efficiency and high accuracy as compared with direct real space calculations [3][4]. The
(coupled/uncoupled) mode space approach treats quantum confinement and transport separately so the procedure of the calculation is as follows [3][4]:
43 Step 1: Solve the 3D Poisson equation for the electrostatic potential.
Step 2: Solve a 2D Schrödinger equation with a closed boundary condition at each slice
(cross-section perpendicular to current flow) of the nanowire transistor to obtain the electron subbands (along the nanowire) and the eigenfunctions.
Step 3: Solve (coupled/uncoupled) the 1D transport equations along the channel by the nonequilibrium Green’s function (NEGF) approach for the electron charge density.
Step 4: Go back to Step 1 to calculate the electrostatic potential self consistently. If it converges, then calculate the electron charge density and the current by the NEGF approach (as in Step 3) and output the results. Otherwise continue Step 2 and 3.
This software uses the effective mass approximation and the ballistic model because of huge computational costs involved in a detailed calculation of the band structure and a rigorous treatment of scattering [3]. It provides an option for inclusion and treating scattering using Büttiker probes. However, scattering was not included in our simulations because of the huge computational time needed to incorporate these complexities. So our results describe the device’s operation in the ballistic limit.
Fig. 2.1 shows the schematic diagram of the cylindrical silicon nanowire device being simulated. The intrinsic device is connected at its two ends, to the two infinite reservoirs of carriers (electrons) – the source and drain. The source and drain are treated using open boundary conditions at the end of the nanowire [3]. The cross section can be
44 arbitrary in shape; however, in our simulations it has been taken to be circular since cylindrical silicon nanowire MOSFETs have been experimentally reported [7]. The X direction in simulations (along the nanowire length) is assumed to be <100> crystal orientation.
Figure 2.1 Schematic of intrinsic nanowire device with circular cross section [3].
The mesh used in device modeling is created using a uniform grid of spacing a along the channel direction X. In the perpendicular Y-Z plane, a 2D finite element mesh with triangular elements is generated [3]. As an example, Fig. 2.2 shows a cross-section
Figure 2.2 Mesh generated at each slice of the nanowire device for simulations [3].
45 of Y-Z plane with the generated triangular mesh. The 3D Schrödinger equation is solved by the mode space approach where the 2D Schrödinger equation is solved by the finite element modeling (FEM) at each YZ slice of the nanowire device to obtain the subband eigenenergy levels and the eigenfunctions (modes).
Below we discuss the basic equations involved in the simulation scheme. In the
3D domain full stationery Schrödinger equation is given by [3],
H 3D ψ x,y,z = Eψ x,y,z , (2.1) `a `a where H3D is the 3D device Hamiltonian. Assuming an ellipsoidal parabolic energy band with a diagonal effective mass tensor, H3D defined as,
fffffffff-fffff2fffffffffffffff∂fffff2ffffff -fff2fffff∂fffffff fffffffffff1fffffffffffffffffff∂fffffff -fff2ffff∂fffffff fffffffffff1ffffffffffffffffff∂fffffff @ @ @ H 3D = C 2 C C + U x,y,z , 2mx x,y ∂x 2 ∂y fg2m y y,z ∂y 2 ∂zfg2m z y,z ∂z `a `a `a `a (2.2)
+ + + Here m x, m y, and m z are the electron effective masses along x, y and z directions, respectively, and U(x, y, z) is the conduction band-edge profile due to the electrostatic potential in the active device [3]. The effective mass varies in the y and z directions due to the transition between the silicon body and surrounding SiO2 layer. The 3D electron wavefunction can be expanded in the subband eigenfunction space,
Ψ x,y,z =X ϕ n x Aξ n y,z x (2.3) n `a `a `a where ξ n y,z x is the nth eigenfunction of the following 2D Schrödinger equation for `a the cross-sectional slice at (x=x0) of the SiNW,
2 2 -ffffffff∂fffffff fffffffffff1fffffffffffffffffff∂fffffff -fffffff∂fffffff fffffffffff1ffffffffffffffffff∂fffffff n n n @ H C C + Ux0 ,y,z Iξ y,z x0 = E sub x0 ξ y,z x0 2 ∂y fg2m y y,z ∂y 2 ∂zfg2m z y,z ∂z `a`a `a `a J `a `a K
(2.4)
46 n th Here E sub x0 is the n subband energy level at x=x0. According to the orthogonal and `a normalization properties of eigenfunctions, these eigenfunctions satisfy the following equation for any x,
E m n ξ y,z x ξ y,z x dydz =δm,n (2.5) y,z `a`a where δm,n is the Kronecker delta function.
Inserting Eqs. (2.2) and (2.3) into Eq. (2.1) and using the relation described by Eq. (2.4) we obtain
2 2 f-fffffffffff∂fffffffffff n @ X n A X n X n A C 2 ϕ x ξ y,z x + ϕ x Εsub x ξ y,z x = E ϕ x ξ y,z x 2mx ∂x den n den `a `a `a `a `a `a `a (2.6)
Multiplying on both sides by ξ n y,z x and performing an integral in Y-Z plane, then `a according to Eq. (2.5), the following simplified 1D coupled Schrödinger equation is obtained [3],
2 2 2 -fffffff ∂fffffffffff -fffffff 2 f∂fffffff m @ m @ X n @- X n m m amm x 2 ϕ x cmn x ϕ x bmn x ϕ x + Esub x ϕ x = Eϕ x 2 ∂x 2 n n ∂x `a `a `a `a `a `a `a `a (2.7)`a where
E fffffffff1ffffffffffffffff m n amn x = C ξ y,z x ξ y,z x dydz (2.7a) mx y,z `a y,z `a`a `a E fffffffff1ffffffffffffffff m f∂fffffff n bmn x = C ξ y,z x ξ y,z x dydz (2.7b) mx y,z ∂x `a y,z `a `a `a and
E fffffffff1ffffffffffffffff m ff∂fffffffff n cmn x = C ξ y,z x 2 ξ y,z x dydz (2.7c) mx y,z ∂x `a y,z `a `a `a
47 In the above equation (2.7) the coupled mode space formalism is equivalent to the real space calculation if all the modes are included (i.e, m,n= 1,…..,NYZ where NYZ is the number of nodes in the y-z plane) [3]. Due to quantum confinement in the nanowire, only the lowest subbands (i.e., m,n= 1,…,M M<< NYZ ) are occupied and need to be included in our calculations. Thus, with first M subbands considered, the results present a set of M equations, each representing a selected mode given by [3].
1 1 1 ϕ x h11 h12 h13 … h1M ϕ x ϕ x H 2`aI H IH 2`aI H 2`aI ϕ x h21 h22 h23 … h2M ϕ x ϕ x HL … M=L ……………ML … M= EL … M , (2.8) L `aM L ML `aM L `aM L M L ML M L M L … M L ……………ML … M L … M L M M L ML M M L M M L M Lh h h … h ML M L M Lϕ x M L M1 M2 M3 MM MLϕ x M Lϕ x M L M J KL M L M J `aK J `aK J `aK
where
2 2 2 -fffffff ∂ffffffffff m -fffffff 2 f∂fffffff h =δ @ a x + E x @ c x @- b x ,m,n= 1,2, …,M (2.9) mn m,n H 2 mm ∂x2 sub I 2 mn nm ∂x `a `a `a `a bc J K
The size of the device Hamiltonian, H is now M .NX. x M . NX, where Nx is the number of nodes in the x direction and M is the mode number which was selected as 3 for our nanowire device simulations. NYZ is around 1000 in the simulations performed here in this study [3].
The crossectional shape of the Si body has been assumed uniform in the x direction, hence, the potential profile varies slowly along the channel direction. This leads to U(x, y, z) having the same shape but different values at different x. Thus the eigenfunctions ξ m x y,z x are the same along the channel length, although the `a`a m eigenvalues E sum x are different [3]. This leads to the condition, `a f∂fffffff m ξ y,z x = 0 ,m= 1,2, …,M (2.10) ∂x `abc
48 which infers fffffffff 2 E fffffffff1ffffffffffffffff m amn x = C ξ y,z dydz, bmn x = 0,cmn x = 0 m,n = 1,2 …,M (2.11) mx y,z L M `a y,z L `aM `a `a bc L M `aL M
This leads to simplifying the Hamiltonian H with hmn =0 ( m≠n and m,n=1,2,….,M), which means that coupling between the modes is negligible. This approach is known as uncoupled mode space approach, which was used in our simulations.
The electron density and current are calculated after the device Hamiltonian H is obtained using NEGF approach [3]. The relevant equations for the simulations are given below. The retarded Green’s function for mode m of the active device is defined as [3]
@ 1 m m X m X m X m G E = ES @ hmm @ E @ E @ E (2.12) DES 1 2 `a `a `a `a where the device Hamiltonian H is defined by Eq. (2.8), ΣS is the self-energy that accounts for the scattering inside the device ( zero for ballistic case), and Σ1 (Σ2) is the self-energy caused by coupling between device and the source (drain) [3].
m m Using the retarded Green’s function, the spectral density functions A 1(E) and A 2(E) due to the source/drain contacts for each mode m are obtained as [3],
m m m mι m m m mι A1 E = G E Γ1 E G and A2 E = G E Γ 2 E G E (2.13) `a `a `a `a `a `a `a m X m X mι m X m X mι where Γ1 E a i E @ E and Γ1 E a i E @ E . The Local DE1 1 DE2 2 `a `a `a `a `a `a density of states (LDOS) for mode m is then calculated using [3],
m f1ffffffff m m f1ffffffff m D p = A p,p and D p = A p,p ,p= 1,2, …N (2.14) 1 πa 1 2 πa 2 X @A @A @A @Abc The 1D electron density for mode m is then calculated using
+ 1 m Z m m n1D = D1 f μS ,E + D2 f μD ,E dE (2.15) @ 1 DEbc bc
49 where f is the Fermi-Dirac distribution function and µS (µD) is the source (drain) Fermi
m level. The 3D electron density is obtained by combining the n1D with the eigen wavefunction for mode m using
2 m m m n3D x,y,z = n1D x ξ y,z x (2.16) L M `a `aL `aM L M Finally, the total 3D electron density is evaluated by summing the contributions from all of the subbands in each conduction-band valley [3]. After achieving self-consistency, the electron current is be computed using [3]
+ 1 ffqffffffff Z @ I SD = TE f μS ,E f μD ,E dE (2.17) π- DE @ 1 `a bcbc where the transmission coefficient T(E) , can be evaluated using [3]
ι TE= trace Γ1 E GEΓ 2 E G E (2.18) `a B `a `a `a `a
2.3 Simulation Tool Preview
The NanoWire simulation tool discussed above is a sophisticated yet simple to use simulation tool which promises real world simulation capability. The Fig. 2.3 shows a snapshot of the tool’s date input page. The various input parameters for the tool are the nanowire diameter (in nm), oxide thickness (in nm), gate length (in nm), source and drain extension length (in nm), source and drain doping (in /cm3) and channel doping (in /cm3), which are logged in on the geometry and doping section page. The tool also allows for
50
Figure 2.3 Snapshot of the interface of the NanoWire simulation tool.
adjustment of the gate work function within the range 0-100 eV. The drain and gate voltage can be varied in increments of as small as 0.001V and scanned to a maximum achievable value of 1V. The tool provides an option of selecting the number of valleys to be simulated for the device, in the range of 1-10. The number of eigenvalues to be used for device simulation can be selected within a range of 1-10. For our simulations the number of the valleys was selected to be 2 and the number of eigenvalues was taken to be
3 for optimum results. The tool offers the option of three transport models: (1) Uncoupled mode space with averaging of the potential on the slices, (2) Uncoupled mode space with
51 scattering by Büttiker probes and no averaging of the potential and (3) Coupled mode space without scattering and without averaging of the potential. Options (1) and (3) provide similar results with (1) being the quicker option [3]. Option (2) allows for simulations using scattering, but takes much more time. For our modeling study, the ballistic model was chosen for our simulations, the uncoupled mode space (option 1) was the transport model selected. The simulation run time turns out to be about 20-30 minutes per bias point.
Below we present a sample simulation run for a baseline device. The parameters selected seen in the input boxes as shown, in the Fig. 2.3, namely 5 nm nanowire diameter, 1 nm oxide thickness, 10 nm gate length, 8 nm source/drain extension lengths and 2x1020 /cm3 as source/drain doping. The channel doping has been set to zero which provides results similar to that of an intrinsic channel. A midgap workfunction of 4.50 eV was selected for the run while the drain voltage was set at 0.8V. The Uncoupled mode space approach without scattering was selected for the run. The number of eigenvalues to be included in the simulation has been set to three.
52
Figure 2.4 Snapshot of Id-Vd curve for the baseline device (Vg=0.8V).
Figure 2.5 Snapshot of Id-Vg curve for the baseline device (Vd=0.8V).
53
Figure 2.6 Snapshot of the electron density cloud within the channel of the baseline device.
Figure 2.7 Snapshot of voltage profile within the channel of the baseline device.
54 Figs. 2.4-2.7 above show snapshots of the simulation run results for the device structure mentioned above. Figs. 2.4 and 2.5 depict the Id-Vd and Id-Vg curves for the simulated structure respectively. Figs. 2.6 and 2.7 show the electron density and the potential profile within the channel respectively. It can be seen that the device exhibits low OFF state leakage current and near ideal sub threshold slope. Also high output resistance is displayed by the device as can be inferred from Fig 2.5. We take a more comprehensive look at this device in the next chapter.
2.4 Comparison with Experimental Results
In this section simulation results have been compared with results of fabricated silicon nanowire FETs reported in literature. It is imperative to have an experimental
Figure 2.8 (a) Fabricated 30 nm long silicon gate all around nanowire FET (b) Id-Vg curve for the fabricated device [6].
55 comparison to benchmark the simulation results. Fig 2.8 below shows a fabricated 30 nm long silicon nanowire FET along with its subthreshold current-voltage characteristics [6].
The experimental device is a 30 nm long n-channel silicon nanowire FET device with 10 nm diameter and 2 nm oxide thickness, which was reported by the Samsung group in the
International Electron Devices Meeting (IEDM), 2005 [6]. The gate electrode material used in fabrication was TiN metal whose work function placed the Fermi energy in the middle of the silicon bandgap and a drain voltage of 1V was used. Ion implantation was not performed to have an intrinsic channel and avoid any random dopant fluctuation.
Diameter = 10 nm 10000 Gate Length = 30 nm Oxide Thickness = 2 nm
1000
100
10
1
0.1 Simulated Vd=1V
Drain Current, Id (uA/um) Simulated Vd=0.05V Experimental Vd=1V 0.01 Experimental Vd=0.05V
0.001
0.0 0.2 0.4 0.6 0.8 1.0
Gate Voltage, Vg (V)
Figure 2.9 Comparison gate current characteristics of simulated (circle) and experimental (square) 30 nm long silicon nanowire devices [6].
56 The same physical parameters were used for the device simulations where the gate work function was chosen to be 4.4 eV. As can be seen from the Fig. 2.9, the simulation results match pretty well with the experimental one. A subthreshold slope of
67.9 mV/dec was obtained for the simulated structure, compared to 71 mV/dec reported for the experimental structure. The better subthreshold slope for the simulated structure can be attributed to the ideal wrap around gate assumed in the simulated structure. The
Off state current is similar at 5.7 nA/µm for simulated device compared to 3.1 nA/µm for the experimental one. The threshold voltage was defined in our simulated structure as
Vth=Vg at Id=1 µA/um. This leads to a threshold voltage of
Table 2.2 Comparative table for simulated and experimental silicon nanowire FET devices.
Simulated SiNW FET Experimental SiNW FET [6] Gate Length 30 nm 30 nm Diameter 10nm 10 nm Oxide Thickness 2 nm 2 nm Gate Material 4.4 eV TiN metal ON current 8.63 mA/µm 2.64 mA/µm OFF current 5.7 nA/µm 3.1 nA/µm ON/OFF current ratio ~ 106 ~ 106 Threshold Voltage 0.15 V 0.24 V DIBL 30 mV/V 13 mV/V Subthreshold Slope 67.91 mV/dec 71 mV/dec
0.15V. The drain induced barrier lowering (DIBL) value calculated for the simulated device is 30 mV/V, which is comparable to 13 mV/V for the experimental result.
57 Fig. 2.10 shows a comparison of linear Id-Vg curves for Vd = 1 V. It is interesting to compare the ON current ratios obtained using the ballistic simulation scheme with the fabricated structure. The current ratio comes out to be ~ 3.2 ( Iballistic=
8.63 mA/µm and Iexperimental = 2.64 mA/µm) which means, actual devices work at ~30% of the ballistic regime at 30 nm gate lengths based on our calculations. It can be argued that the simulation tool predicts subthreshold characteristics pretty closely. However, the drive current is overestimated since it is being calculated using a ballistic simulation scheme. Also, no series resistance was included at the source and drain, which also contributes to a higher drain current. The fact that the experimental device had a gap
Figure 2.10 Id-Vg curves for simulated (solid) and experimental (dashed) 30 nm long silicon devices.
58 between the channel (gate edge) and the source/drain [as shown in Fig. 2.9 (a)] also likely leads to a reduction the drain current value obtained.
2.5 Conclusion and Summary
In this chapter we discussed in depth the methodology of the simulation software and the associated physics behind it. Initially, we talk about the relevancy of the NEGF transport model in modern day scenario when devices are shrinking to 10 nm regime.
Later on the physics used in simulation scheme was discussed and the necessary equations used were derived. In the next section a baseline device was used to present a sample simulation run and results were presented to illustrate the operation of the program. Lastly, we presented a comparison of simulation and experimental results for a
30 nm long fabricated silicon gate all around FET. The simulation results compare pretty well with the experimental ones, which gives us confidence to proceed with further simulations. In the next chapter we will present silicon nanowire simulation results in which we compare and contrast our nanowire transistor results with those for a double gate transistor. A subsequent chapter takes a look at optimization of the silicon nanowire device for the 25 nm node.
59 REFERENCES
[1] M. P. Anantram, M. S. Lundstrom and D. E. Nikonov, "Modeling of Nanoscasle
Devices," arXiv.org cond-mat/0610247 (2005).
[2] Z. Ren, “Nanoscale MOSFETs: Physics, Simulation, and Design,” Ph.D. dissertation,
Purdue University, 2001.
[3] Jing Wang, Eric Polizzi, Mark Lundstrom, "A three-dimensional quantum simulation of silicon nanowire transistors with the effective-mass approximation," Journal of
Applied Physics 96(4), pages 2192-2203, 2004.
[4] https://www.nanohub.org/tools/nanowire/
[4] S. Jin, “Modeling of Quantum Transport in Nano-Scale MOSFET Devices,” Ph.D. dissertation, Seoul National University, 2006.
[6] S.D. Suk et al, “High Performance 5nm radius Twin Silicon Nanowire
MOSFET(TSNWFET) :Fabrication on Bulk Si Wafer, Characteristics, and Reliability”,
IEDM 2005, pp 717-720, Dec 2005
[7] S.D. Suk et al, “Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET
(TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires”, IEDM 2006, pp 1-4,
Dec 2006
60 Chapter 3
Device Simulation Results and Comparison for n-channel Silicon Nanowire FET
The first part of this chapter discusses the current characteristics of an n-channel
Silicon Nanowire FET compared with a Double Gate (DG) FET. Devices with a 10 nm gate length were studied, which corresponds to the 25 nm node according to International
Technology Roadmap for Semiconductors (ITRS) report. Transfer and output characteristics of the two devices have been examined and compared. The study illustrates the differences and advantages that a wrap around gate device presents over a double gate device [1] [2]. Simulations were performed in the quantum-ballistic environment for both the devices which is imperative to study devices in the sub-10 nm regime [1]. The silicon nanowire FET was simulated using the tool (NanoWire) discussed in previous chapter. The double gate FET was simulated using the software nanoMOS
3.0 [3] [4]. NanoMOS 3.0 is a 2-D double gate device simulator which allows simulations to run in the quantum-ballistic mode and was selected for all DG FET simulations. In the later part of the chapter we look at the scaling effects of device parameters like gate length, diameter and gate oxide thickness. The silicon nanowire FET physical parameters were varied around the baseline device simulated initially and described in the previous chapter.
61 3.1 Baseline Device Structure
The baseline device structure selected for comparative simulation study is a 10 nm long n–type channel FET. The double gate and nanowire device structures are showed in Fig 3.1 below. For this comparison, the nanowire diameter was set equal to the width of the channel between the gates in the double gate (FinFET) FET.
Figure 3.1 Device structures for a (a) Double Gate FET and a (b) Silicon Nanowire FET.
For this study the devices have been simulated with the same physical and electrical parameters. As a starting point the body thickness for the DG FET was taken to be 5 nm while correspondingly nanowire diameter has been set at 5 nm. The gate oxide
62 thickness was set at 1 nm for both the devices. The channel has been left undoped for all the simulations while source and drain are kept at uniform high n-type doping level of 2 x
1020 /cm3. No grading was assumed at the edges of source and drain, which leads to abrupt source/drain doping profile near the channel ends. No gate overlap with the source/drain junctions was assumed. Source and drain extension lengths are kept at 8 nm.
The gate material has been assumed to have an adjustable work function and has been set to mid-gap value of 4.5 eV for both the devices. A drain voltage supply of 0.8 V was used for the simulations.
3.2 Device Simulations Results
3.2.1 Comparison of a SiNW FET with DG FET.
The simulation results of the subthreshold characteristics of the two devices for the study are shown above in Fig. 3.2. The figure plots the log Id-Vg curve for silicon nanowire FET and for DG FET for two different drain biases of 0.05 V and 0.8 V. The current values have been normalized by dividing it to the nanowire diameter or body thickness for DG FET. It can be seen from the figure that due to higher effective number of gates for the nanowire, a lower off state current is achieved. As the gate control is enhanced for the nanowire FET, the leakage paths in the channel are eliminated decreasing the off state leakage current. Ioff for DG FET is calculated to be 4 µA/µm compared to about 1 nA/µm for the silicon nanowire device, a factor of 4000 times smaller. Also, slightly a higher drive current is achieved for the nanowire FET at 5024
µA/µm as compared to 4746 µA/µm for a double gate FET, a 6% difference. The results are in general agreement with previous simulation results reported by Bescond et. al. [2]
63
Figure 3.2 Simulated Output characteristics for a 10 nm gate length Silicon nanowire FET (▲) and a DG FET (●).
in Fig 3.3, which shows increasing Ion and reducing Ioff with an increasing number of gates and better gate control over the channel. Specifically Fig. 3.3 shows the simulation result for a Tri-gate (~3), Pi-gate, Omega-gate (~4) and a Gate All Around FET. GAA
FET is the same as the silicon nanowire FET being simulated in our results. Our results also correspond to higher Ion / Ioff ratio for SiNW FET, which is calculated to be of the order of 106 while the current ratio for DG FET is about 103. This is significantly larger than that shown by Bescond et. al. [2] in Fig 3.3.
Looking at the subthreshold characteristics for the two device structures, it can be seen from the Fig. 3.1 that the silicon nanowire FET provides much better control over
64
Figure 3.3 Comparison of Id-Vg curves for multi gate transistors with increasing effective number of gates at gate length of 9 nm [2].
short channel effects. Subthreshold slope is significantly better for the nanowire FET at
75.38 mV/dec compared to 136.19 mV/dec for DG FET. Defining the threshold voltage at a constant current level of Id=1 uA for our purpose, this gives us a threshold voltage of
0.243 V for DG FET and 0.449 V for the silicon nanowire FET. The nanowire FET exhibits a higher threshold voltage value which is a direct result of enhanced gate control and the higher potential energy barrier between the source and drain. The drain induced barrier lowering (DIBL) is calculated as shift in threshold voltage with drain voltage changing from Vd= 0.05 V to Vd= 0.8 V. The DIBL calculated for DG FET from Fig 3.1 is 270 mV/V while, as expected, the silicon nanowire device shows a significantly smaller DIBL value of 94.6 mV/V.
65 Fig. 3.4 below shows the output characteristics for a silicon nanowire and a
DG FET transistor. It is clear from the figure that the silicon nanowire transistor shows a higher output resistance (lower conductance) than a double gate FET. The calculated
Rout at a gate voltage of Vg=0.8 V for the SiNW FET is 187.46 kΩ as compared to 70.42 kΩ for DG FET. This output resistance is an important parameter in analog circuit applications as the voltage gain is directly related to it. Table 3.1 shown below provides a comparative summary of the results.
6000
5000
Vg=0.8V 4000
3000
2000 Vg=0.6V
1000 Drain Current, Id (uA/um) Id Current, Drain Vg=0.4V 0
0.0 0.2 0.4 0.6 0.8 Drain Voltage, Vd (V)
Figure 3.4 Simulated Id-Vd curves for the Silicon Nanowire FET (▲) and Double Gate (DG) FET (●).
66 Table 3.1 Comparison between DG FET and a SiNW FET.
DG FET SiNW FET ON Current, Ion 4746 µA/µm 5024 µA/µm OFF current, Ioff 4 µA/µm 1 nA/µm Ion/Ioff ~103 ~106 Vth (at Id= 1µA) 0.243 0.449 DIBL 270 mV/V 94.6 mV/V SS 136.19 mV/dec 75.38 mV/dec Rout 70.42 kΩ 187.46 kΩ
3.2.2 Effects of Scaling on Silicon Nanowire FET Parameters
In this section we take a look at the variation in the physical parameters of a silicon nanowire FET and how it affects the Id-Vg characteristics. Fig. 3.5 shows the current variation in the subthreshold characteristics with nanowire diameter. The drain current values have been normalized to the nanowire diameter. The nanowire device being simulated here has constant gate length of 10 nm and gate oxide thickness of 1 nm.
The diameter value of the device has been varied from 3 nm to 7 nm. It can be seen that off state current drops exponentially with decreasing diameter while on state current increases linearly with the diameter. As the diameter is decreased gate control over the channel increases, which eliminates the off state current leakage paths, hence we see reducing Ioff with decreasing diameter. Also quantum mechanical confinement effects start to play an important role as channel thickness is reduced below 5 nm [5]. As can be seen from the Fig 3.5, for a diameter approaching D=3 nm we see a significant reduction
67
Figure 3.5 Variation in Id-Vg current characteristics with varying diameter.
in on and off state current and a rapid increase in the threshold voltage. Going from D=4 nm to D=3nm, Ion reduces from 4177 µA/µm to 2673 µA/µm while Ioff shows a reduction of the order of 102. A more complete analysis of the effects of variation of the nanowire diameter has been done in chapter 5.
Fig 3.6 below shows the variation in Id-Vg curves with varying gate lengths. Here the nanowire diameter has been kept constant at 5 nm while the oxide thickness was maintained at 1 nm. The gate length was varied from 8 nm to 12 nm. It can be seen from the figure that off state current increases as gate length is reduced. The reason for it is the short channel effects that start playing a role with reducing gate lengths as has been discussed in chapter 1. The potential energy barrier height at the source and the channel
68
Figure 3.6 Variation in Id-Vg current characteristics with Gate Length.
Figure 3.7 Variation in Id-Vg current characteristics with Oxide thickness.
69 decreases with shortened channel length, which leads to a smaller threshold voltage and increasing leakage current.
The variation in Id-Vg characteristics with changing oxide thickness is shown in
Fig. 3.7 where the simulated nanowire has a 10 nm gate length and 5 nm diameter. It can be seen that decreasing oxide thickness improves the device performance because of increased gate control. The Off state current decreases while the on state current shows an increasing trend with thinning of the oxide. Here gate tunneling has not been considered, however it becomes an important limiting scaling factor as the gate oxide is thinned below 1nm [6].
3.3 Results and Discussions
In this chapter we have provided a comparative study between a 10 nm gate length silicon nanowire FET and a Double Gate FET. Both, transfer and output characteristics were studied and it was concluded from the results that nanowire FET shows much superior device performance. In the latter part of the chapter we did a study on scaling effects of different physical parameters like nanowire diameter, gate length, and oxide thickness. The Id-Vg current characteristics were studied with the variation of these parameters. In next chapter we conduct an optimization study on silicon nanowire device and we optimize the device for the 25 nm node corresponding to 10 nm channel length for both Low Operating Power (LOP) and High Performance (HP). Also, a study on scaling of silicon nanowire FET up to 5 nm gate lengths has been done.
70 REFERENCES
[1] J. Wang, E. Polizzi, M.S. Lundstrom, “A computational study of ballistic silicon nanowire transistors," IEDMTech. Dig.,p . 695,2003.
[2] M. Bescond, K. Néhari, J.L. Autran, N. Cavassilas, D. Munteanu, and M. Lannoo,
"3D Quantum Modeling and Simulation of Multi-Gate Nanowire MOSFETs," in IEDM
Tech. Dig., pp. 617-620, 2004.
[3] Zhibin Ren, Ramesh Venugopal, Sebastien Goasguen, Supriyo Datta, and Mark S.
Lundstrom "nanoMOS 2.5: A Two -Dimensional Simulator for Quantum Transport in
Double-Gate MOSFETs," IEEE Trans. Electron. Dev., special issue on Nanoelectronics,
Vol. 50, pp. 1914-1925, 2003.
[4] Simulations were performed by nanoMOS 3.0 on http://nanohub.org
[5] H. Majima, H. Ishikuro, and T. Hiramoto, “Experimental evidence for quantum mechanical narrow channel effect in ultra-narrow MOSFETs,” IEEE Electron Device
Lett., vol. 21, pp. 396-398, Aug. 2000.
[6] Y. Taur, “CMOS design near the limit of scaling,” IBM J. Res. Develop., pp. 213–
222, Mar./May 2002.
71 Chapter 4
Device Optimization and Scaling Potential for a Silicon Nanowire FET
The CMOS MOSFET scaling is expected to be ultimately limited by the level of off-state leakage current [1]. At gate dimensions of sub-10 nanometers, the silicon nanowire FET presents a promising option as it offers maximum gate control due to its wrap around structure. Nanowire FETs show very low (better) off-state leakage current and superior short channel effects (SCE) compared to planar and dual gate MOSFETs
(FinFETs) as discussed in chapter 3. The International Technology Roadmap for
Semiconductors (ITRS) is an annual publication that charts out a consensus roadmap for how semiconductor companies can sustain growth in view of the challenges posed by
MOSFET downscaling [2]. Table 4.1 provides a look at the long-term projections made by ITRS for high performance logic technology requirements. The MOSFET’s physical
Table 4.1 Long-term ITRS Roadmap Specifications for MOSFET Scaling [2].
72 gate length is predicted to be at 10 nm by 2015 for the then 25 nm node as shown in the
Table 4.1.
In this chapter we report the results of an optimization study for the silicon nanowire FET device for the 25 nm node according to International Technology
Roadmap for Semiconductors (ITRS). Working with a constant gate length at 10 nm as required for the 25 nm technology node, the study was carried out by changing gate work-function and the diameter of the nanowire devices. Both the low operation power
(LOP) and high-performance (HP) logic application were considered. In the later section we have assessed silicon nanowire FETs for four future technology generations, i.e.
HP14, HP22, HP32 and HP45.
4.1 Device Optimization Study of Silicon Nanowire FET for the ITRS 25 nm node.
4.1.1 Device Simulation Structure
Simulations were performed using the three-dimensional (3D) NanoWire tool as was described in chapter 2. The quantum-ballistic transport model was used for all the simulations. According to the ITRS roadmap for 25 nm technology node, the gate length was set at 10 nm. The oxide thickness (Tox) and drain voltage (Vd) for HP25 node were set at 0.6 nm and 0.8 V respectively while for LOP25 node, they were set at 1.0 nm and
1.0 V, respectively. However, in our simulations more tolerable parameters were considered, i.e. Tox was taken to be 1 nm and Vd was taken to be 0.8 V for both technology requirements in the view of an enhanced device structure of nanowire FET being simulated. The ON-state and OFF-state current specifications have been defined in
73 Table 4.2 as per ITRS roadmap at 2275 µA/µm and 0.11 µA/µm respectively for the
HP25 node and 863 µA/µm and 10-5 µA/µm respectively for LOP25 node respectively.
The nanowire channel has been left undoped to avoid any random dopant induced fluctuations [4]. The source and drain regions have been heavily doped at 2x1020 /cm3.
Gate material work-function was varied over the range from 4.2 – 4.8 eV while the nanowire diameter range was considered from 2 – 8 nm. We optimized the workfunction
Table 4.2 Parameters for HP25 and LOP25 Technology Nodes as per ITRS Report [2].
HP25 LOP25 Gate Length, Lg 10 nm 10 nm
Oxide Thickness, Tox 0.6 nm 1.0 nm Drain Voltage, Vd 0.8 V 1.0 V
-5 OFF current, Ioff 0.11 µA/µm 10 µA/µm
ON current, Ion 2275 µA/µm 863 µA/µm
Figure 4.1 A three dimensional (3D) Silicon nanowire FET structure being simulated.
74 and the diameter for the device. Fig. 4.1 below shows a 3D structure of the nanowire device being simulated.
4.1.2 Simulation Results for the Optimization Study.
We begin our initial study by examining the relationship of the diameter and workfunction on the ON-current and OFF-current requirements. In this study ON state current value is defined as the current level at gate voltage of, Vg=0.8 V and drain voltage Vd=0.8 V while OFF state current value is defined at gate voltage of Vg=0 V and drain voltage of Vd=0.8 V. Figs. 4.2 and 4.3 show the dependence of ON-current (Ion)
4.2eV 4.3eV 8000 4.4eV 4.5eV 4.6eV 6000 4.7eV 4.8eV
4000
Ion (uA/um) Ion HP 2000 LOP
0
246810
Diameter (nm) Figure 4.28 Dependence of Ion on diameter for silicon nanowire FET for different gate electrode work functions. The solid and dashed lines mark the Ion targets of ITRS for HP and LOP, respectively.
75 and OFF-current (Ioff) on the nanowire diameter for different work functions. Initially it can be seen from the Fig. 4.3 that Ioff decreases with decreasing diameter, which is due to reduced current carrying modes. As seen in Fig. 4.2 Ion decreases with decreasing nanowire diameter due to an increase in threshold voltage. Also it can be noted from the two figures that with the increase of gate work function, both Ion and Ioff decrease because of an increase in the threshold voltage, Since the work function directly controls the threshold voltage. From Figs. 4.2 and 4.2 it can be noticed that Ioff decreases exponentially while Ion decreases linearly with varying work function. Also, it can be seen that for gate materials with a higher work function, Ioff decreases more rapidly with nanowire diameter as compared to Ion. According to ITRS roadmap, to satisfy the future
1e+2 1e+1 1e+0 HP 1e-1 1e-2 1e-3 1e-4 LOP 1e-5 1e-6 1e-7 1e-8
Ioff (uA/um)Ioff 1e-9 4.2eV 1e-10 4.3eV 1e-11 4.4eV 1e-12 4.5eV 1e-13 4.6eV 4.7eV 1e-14 4.8eV 1e-15 1e-16 246810
Diameter (nm)
Figure 4.3 Dependence of Ioff on diameter for silicon nanowire FETs for different gate electrode work functions. The solid and dashed lines mark the Ioff targets of ITRS for HP and LOP, respectively.
76 current technology requirements Ion should be greater than 2275 µA/µm and Ioff should be less than 0.11 µA/µm for HP applications while for LOP applications we need to have Ion
-5 more than 863 µA/µm and Ioff less than 10 µA/µm. The dashed lines in the Fig. 4.2 and
4.3 show the requirements for LOP devices while solid lines depict the requirements for
HP devices.
To better examine the off-current and on-current limitations, we can plot the Ion vs Ioff for a range of diameter and work function to explore how to satisfy the ITRS 25 nm node requirement. Fig. 4.4 shows the plots for a range of diameters from 2 to 7 nm and work functions from 4.2eV to 4.8eV. Each curve corresponds to a specific work function and each of the data points along the curve relate to a different diameter. Since
Figure 4.4 Simulation results for the Ion - Ioff curve of simulated 10 nm Silicon nanowire FET with various work function and nanowire diameter. The solid line represents the HP specifications and the dotted lines represent the LOP specifications.
77 Ion needs to larger than a minimum and Ioff less than a maximum all the data points on the right of the vertical Ion requirement line and below the horizontal Ioff requirement line are in the desired range. From Fig. 4.4 we can derive a design window with gate work function and nanowire diameter as variables.
Using the results from Fig. 4.4, Fig. 4.5 shows the optimized design window
(irregularly shaped area) obtained for the HP and LOP applications for the 25 nm node. It can be seen that HP has a larger window (larger range of diameters) as compared to LOP device design. This is a consequence of the higher Ioff current requirement for the HP
10
HP Window LOP Window 8
6
4 Diameter (nm) Diameter
2
0 4.2 4.4 4.6 4.8 Work Function (eV)
Figure 4.5 Diameter versus workfunction of 10 nm Silicon nanowire device which satisfy the LOP and HP specifications.
78 devices. It is also interesting to note that the design window spans the whole of the work function range from 4.2 – 4.8 eV for the HP application. By contrast, there is no window available for LOP applications above the 6.5 nm diameter, for HP applications the upper limit is the 9 nm diameter.
Besides the ON and OFF-current specifications, one can also base the design window on other measures of device performance. For further, FET optimization, we have selected the Ion /Ioff current ratio and the drain induced barrier lowering (DIBL) as the limiting factors. The Ion/Ioff ratio versus diameter for the given range of work function is shown in Fig. 4.6. The limiting current ratios can be calculated from the required minimum ON and maximum OFF current specifications from the ITRS roadmap. The
Figure 4.6 Ratio Ion/Ioff of 10 nm silicon nanowire structure with different diameters and work functions.
79 dashed and solid lines on Fig. 4.6 represent the minimum Ion/Ioff ratio for the LOP and
HP applications, respectively. From the figure it can be seen that the current ratio required for LOP devices is pretty high at around 108 as it requires very low OFF currents. By comparison, for the HP devices the current ratio required is of the order of
104. It is obvious from the figure that at a given diameter, the higher the work function, the higher the current ratio Ion / Ioff .
Along with ON and OFF current ratio another limiting condition worth considering is the drain induced barrier lowering (DIBL) effect which was discussed in chapter 1. Fig. 4.7 shows the ratio of ∆VT/ VT (VT shift caused by DIBL effect) of the 10 nm nanowire device versus diameter for different work functions, where ∆VT = Vth (Vd
=0.05V) – Vth (Vd = 0.8V). It is clear that with reducing the nanowire diameter the threshold voltage shift is suppressed due to improved gate control of the charge in the channel and less penetration of electric field lines from source to the drain. It is also seen that the work function has no effect on threshold voltage shift. Also, it is known that threshold voltage of devices increase with increasing workfunction. Therefore devices with higher workfunction result in smaller ∆VT/ VT ratio. For optimal performance the device should have smaller ∆VT to contain the size of the DIBL and a smaller VT to have higher ON current. To obtain good performance, ∆VT/ VT < 0.3 is used as the DIBL criterion for both LOP and HP applications. So the region below the dashed line in Fig.
4.7 can meet the performance requirement.
80
Figure 4.7 Ratio ∆VT/ VT of the nanowire devices versus diameter for different work function. The dashed line in the figure indicates the shift VT specifications.
The final optimization window is obtained by using the limiting condition for
Ion/Ioff current ratio and the DIBL condition from the results shown in Fig. 4.6 and 4.7, respectively. From the Fig. 4.6, it is seen that the solid line for the HP case represents the minimum Ion/Ioff ratio required and each curve corresponds to a specific work function.
The required Ion/Ioff ratio is calculated from the specified ON and OFF current for HP25 node in Table 4.2. We can obtain a maximum diameter value for each work function which satisfies the current ratio requirement from the Fig. 4.6. Similarly from the Fig. 4.7 it can be seen that each curve corresponds to a specific work function. Applying the
DIBL criteria i.e. ∆VT/ VT < 0.3 (shown as dashed line in Fig. 4.7) leads to again a maximum diameter value for each work function. From the two limiting criteria
81
Figure 4.8 Optimized diameter versus workfunction of 10 nm Silicon nanowire FET for HP25 node. The colored region shows the optimized region for the device performance. discussed above the lower maximum diameter can be selected to define the limiting curve seen in Fig. 4.8. It should be noted that the limiting curve for HP application is mainly determined by the DIBL condition as the required Ion/Ioff condition is met for much wider range of diameter. Since the limiting curve defines the upper limit for the diameter, the area common to the region below the limiting curve and the HP window gives the final design window. It is clear from the Fig. 4.8 that workfunction range for HP25 node ranges up to the value of 4.72 eV from 4.2 eV and at the mid-gap work function, a broad range diameter is available which satisfies the requirement.
82 Similarly for the LOP case the dashed line in Fig. 4.6 defines the minimum
Ion/Ioff required for different work function and diameter ranges. The specified Ion/Ioff ratio is calculated from the ON and OFF currents specified for LOP25 node in Table 4.2.
We can obtain a maximum diameter value for different work function values based on the
Ion/Ioff ratio requirement from Fig 4.6. Applying the DIBL criteria i.e. ∆VT/ VT < 0.3
(shown as dashed line in Fig. 4.7) leads to again a maximum diameter value for each work function. From the two limiting criteria discussed above the lower maximum
Figure 4.9 Optimized diameter versus workfunction of 10 nm Silicon nanowire FET for LOP25 node. The colored region shows the optimized region for the device.
83 diameter can be selected to define the limiting curve seen in Fig. 4.9. It should be noted that the limiting curve for LOP application is mainly determined by Ion/Ioff ratio due to its high current ratio requirement. Since the limiting curve defines the upper limit for the diameter, the area common to the region below the limiting curve and the LOP window gives the final design window as shown in Fig 4.9. It should be noted that the limiting curve for LOP25 doesn’t intersect the original window and whole of the design area is available. It is interesting to see that LOP design window extends over whole of the work function range, however the diameter range is not wide as for HP25. In the midgap work function region the window provides the widest thickness range of about 1 nm. Also it should be noted that for the same work function, the LOP25 window requires a smaller diameter as compared to HP25 window.
From the Figs. 4.8 and 4.9, a diameter of 4 nm and work function value of 4.56 eV can be selected for an optimized device. Since the selected device falls within both the technology design windows, it should achieve both the HP25 and LOP25 technology node requirements. The Id-Vg curve is shown in Fig 4.10 for the selected device. It can
-6 be seen that it a low Ioff value of 4.3 x 10 µA/µm and a high Ion value of 2900 µA/µm.
8 The Ion/Ioff ratio can be calculated and is found of the order of ~ 10 . Subthreshold characteristics can also be calculated from the given current-voltage plots. Threshold voltage here has been defined at Id=10-8 A which leads to a value of 0.401 V. DIBL value obtained is pretty low at 53.33 mV/V. The subthreshold slope for the device is calculated to be close to the ideal value of 60 mV/dec at 66.67 mV/dec . It can be concluded that a silicon nanowire FET is capable of meeting the 25 nm node specifications.
84
Figure 4.10 Drain current versus gate voltage characteristics for the optimized device. Drain voltage is selected to be Vd=0.8 V (●) and Vd=0.05 V (○).
However, it should be noted this analysis assumes ballistic transport and it must be considered an optimistic assessment.
Fig. 4.11 shows the Id-Vd curve for the 10 nm optimized device. The device shows a high output impedance of 0.53 MΩ at Vg=0.8 V. It can be seen that the current values increase exponentially with increasing gate voltage which is a short channel characteristic.
85 1.4e-5
Vg=0.8V 1.2e-5
1.0e-5
8.0e-6
6.0e-6 Vg=0.7V
4.0e-6 Drain Current, Id (A) Id Current, Drain 2.0e-6 Vg=0.6V
0.0 Vg=0.5V
0.0 0.2 0.4 0.6 0.8 Drain Voltage, Vd (V)
Figure 4.11 Simulated drain current versus drain voltage characteristics for the optimized device.
86 4.2 Scaling Potential of Silicon Nanowire FET.
4.2.1 Scaling of MOSFETS beyond 45 nm node.
In this section we have discussed the scaling potential of silicon nanowire devices for future technology nodes from 45 nm down to 14 nm node. With devices scaling to smaller dimensions with every technology node, as can be seen from Fig 4.12, the body thickness (TSi) (nanowire diameter for the nanowire FET) is projected to reduce nearly linearly. However, as also shown in Fig. 4.12 in the case of effective oxide thickness
(EOT) we are approaching a limiting regime where gate tunneling becomes excessive .
Figure 4.12 Reduction of body thickness and oxide thickness with future technology node [3].
87 The EOT is expected to be at 0.9 nm for the 45 nm node and is projected to remain constant at 0.5 nm at the HP22 and HP14 technology nodes as seen from Fig. 4.12 [2] .
The ITRS roadmap predicts that the semiconductor industry will reach the 45 nm technology node by 2010 with gate lengths shrunk to 18 nm and EOT to be 0.9 nm as shown in Table 4.3 [2]. The body thickness is projected to be 11.8 nm at HP45 which is a linear extrapolation from previous nodes. Gate lengths are expected to go below the 10 nm mark by the year 2016 with continued scaling. The extrapolated body thickness is expected to reach the 5 nm mark by the year 2016. When reducing body thickness to dimensions below 5 nm, the device starts to show significant quantum effects which
Table 4.3 MOSFET Parameters for Future Technology Nodes [2].
HP45 HP32 HP22 HP14 Year 2010 2013 2016 2020 Lg (nm) 18 13 9 5 EOT (nm) 0.9 0.6 0.5 0.5
TSi (nm) 11.8 8.4 5.51 2.59 Vd (V) 1.0 0.9 0.8 0.7
Ioff (nA/µm) 145 107 108 108
affects its performance as was discussed in chapter 1. The drain voltage is also planned to be scaled down along with decreasing gate lengths to maintain the performance of the devices. The voltage reduces from 1 V for HP45 to 0.7 V for HP14 technology node. The
OFF state leakage current is one of the critical parameters and the target Ioff set by ITRS is 108 nA/µm for the HP14 technology node and the Ioff requirement is also seen to becoming more stringent with reducing gate lengths.
88 4.2.2 Device Simulation Structure
The Id-Vg curves for the four future technology nodes HP45, HP32, HP22, HP14 have been simulated using the NanoWire tool discussed previously. A study of these nodes provides insight into future device performance for the silicon nanowire FET with a corresponding structure. An ideal n-channel silicon gate all around FET has been considered as the device for the four nodes. The physical parameters have been chosen as those described in Table 4.2. Body thickness of the device has been considered to be same as the nanowire diameter in the simulations. The required OFF current values were achieved by adjusting the work function for the devices. The channel was kept undoped to avoid any random dopant induced fluctuation. The source and drain were highly doped at 2x1020 /cm3. Threshold voltage was defined at constant current level of 10-6 A for all the nodes.
4.2.3 Simulation Results
Figs. 4.13-4.16 below show the current voltage results for the four nodes discussed above. OFF state current for all the four nodes were adjusted using proper gate material work function. It can be seen from Fig. 4.13 that HP45 current curve shows an
ON/OFF ratio of ~8000. However, this is likely an overestimation as a ballistic simulation model is being used. The transistor exhibits a subthreshold slope of 83.4 mV/dec and a DIBL value of 104 mV/V. Device performance simulated at this node is seen to be somewhat worse than next two successive nodes. The reason is likely that a thick channel body of 11.8 nm is being simulated which leads to less gate control and increased short channel effects.
89
Figure 4.13 Simulated Id-Vg curve according to HP45 node parameters. Workfunction was adjusted (Φ=4.487eV) to achieve required off state current.
Figure 4.14 Simulated Id-Vg curve according to HP32 node parameters. Workfunction was adjusted (Φ =4.404 eV) to achieve required off state current.
90
Figure 4.15 Simulated Id-Vg curve according to HP22 node parameters. Workfunction was adjusted (Φ =4.347 eV) to achieve required off state current.
Figure 4.16 Simulated Id-Vg curve according to HP14 node parameters. Workfunction was adjusted (Φ = 4.229 eV) to achieve required off state current.
91 Fig. 4.14 and 4.15 above show the current characteristics for HP32 and HP22 technology nodes. HP32 and HP22 both show ON/OFF current ratio of the order of 105.
Here we see somewhat similar subthreshold characteristics for the two nodes. Threshold voltage defined at 10-6 A were found to be 0.27 V and 0.28 V for 32 nm and 22 nm nodes, respectively. Fig. 4.16 shows current characteristics for the ultra scaled 14 nm node predicted for the year 2020 using a silicon nanowire FET. At gate lengths of 5 nm and body thickness of 2.59 nm severe quantum effects start playing a role in device performance such as source-drain tunneling, which increase the threshold voltage. From the figure it can be seen that threshold voltage rises to pretty high value of 0.36 V defined at 10-6 A as compared to devices at prior nodes. With the OFF state current adjusted using the work function a ON/OFF current ratio of 104 is achieved.
Figs. 4.17 and 4.18 show the subthreshold slope and DIBL plotted against gate
lengths for the different technology nodes. The subthreshold slope for the two devices
were found to be acceptable 78.3 mV/dec, 76.2 mV/dec for HP32 and HP22,
respectively. DIBL values for the two devices were again similar at 77.33 mV/V and
77.52 mV/V. It can be argued from above simulation results that silicon nanowire FET
seems to be a promising candidate for 32 nm and 22 nm nodes. However, looking at the
HP14 node subthreshold characteristics seem to degrade with subthreshold slope of
86.8 mV/dec and DIBL value of 104 mV/V. It can be observed that performance seem
to deteriorate at channel lengths approaching sub-10 nm regime.
92 . Figure 4.17 Simulated subthreshold slope values for future technology nodes.
Figure 4.18 Simulated DIBL values for future technology nodes.
93 Fig. 4.19 shows the simulated ON current calculated for the different technology nodes for comparison, the ITRS projected ON currents have been plotted against channel lengths. It can be seen that ON current values deteriorate below the 32 nm node but are still well above the ITRS requirement. The HP45 shows a lower ON state value than its lower HP32 node. The HP14 ON current value is seen to be reduced to about 9000
µA/µm under ballistic mode, that is about a factor of three higher than the target ITRS
ON current value.
14000 HP32 HP22 HP45 12000
Ballistic SiNW Simulation 10000 HP14
8000
6000 Ion (uA/um)
4000 ITRS 2006 2000
0 4 6 8 10 12 14 16 18 20
Gate Length (nm)
Figure 4.19 Simulated ON current values (solid) for the future technology nodes compared to target ITRS ON current values (dashed).
Fig. 4.20 shows the reported simulation of ON currents for different future technology nodes using Quantum Drift Diffusion (QDD) transport model. It can be seen
94 that specified ITRS values are not met for HP14 and HP22 Ion current requirements when ballistic effects are ignored. It is interesting to compare Figs. 4.19 and 4.20 and it
Figure 4.20 Simulated Ion current values for Circular nanowire (CNW) FET (○) and Double Gate (DG) FET (□) using Quantum Drift Diffusion (QDD) transport model along with ITRS target (●/■) current values.[3].
can be argued from the curves that at gate lengths below 10 nm when ballistic regime is expected to set in, it remains a critical technology booster needed to achieve the desired
ON state currents.
95 4.3 Conclusions and Discussions
In this chapter we have examined the device design for the 25 nm technology node. Both the High Performance (HP) and Low Operating Power (LOP) technologies were considered for this design study. The optimized device was simulated and found to exhibit the desired performance and subthreshold characteristics. DIBL and subthreshold slope were at acceptable values of 53.33 mV/V and 66.67 mV/dec. In the second part of the chapter we looked into the feasibility of silicon nanowire FET as a future replacement or the planar MOSFET. Four of the future nodes were considered and nanowire simulation were performed with the device specifications based on the ballistic transport, the nanowire FETs showed acceptable performance to meet the ITRS requirements. It is interesting to find that below 10 nm gate lengths extreme shorts channel effects set in affecting performance of even the nanowire FET devices. In the next chapter we take a look at process variation sensitivity of a silicon nanowire FET as compared to a FinFET.
96 REFERENCES
[1] An, "Design guideline of an ultra-thin body SOI MOSFET for low-power and high- performance applications," Semiconductor Science and Technology, vol. 19, pp. 347,
2004.
[2] ITRS (Int. Technology Roadmap for Semiconductors) 2006 Edition, http://public.itrs.net, 2006.
[3] E. Gnani, S. Reggiani, M. Rudan and G. Baccarani: “Effects of high-κ (HfO) gate dielectric in Double-Gate and Cylindrical-Nanowire MOSFETs scaled to the ultimate technology nodes”, Silicon Nanoelectronics Workshop, Honolulu, Hawaii, June 11-12,
2006.
[4] D. J. Frank, Y. Taur, M. Ieong, and H.-S. P. Wong, “Monte Carlo modeling of threshold variation due to dopant fluctuations,” in VLSI Tech. Dig., 1999, pp. 169–170.
97 Chapter 5
Process Sensitivity Study for Silicon Nanowire Transistors
Chapter 4 described an optimization study and the scaling potential for silicon nanowire (SiNW) transistors. While silicon nanowire transistors have been well studied and are looked upon as future candidates for device design, with the advancement of this technology as a potential replacement for conventional MOSFETs, it becomes important to understand the effects on the gate all around (GAA) nanowire MOSFET of process variations and how they compare with those for the dual gate MOSFET (FinFET). In general, the fabrication process for multi-gate transistors, e.g. FinFET and silicon nanowires, are more complicated. For example the gate oxide is etched on the FinFET sidewall and it is more difficult to control its uniformly. For scaled MOSFETs, channel- oxide surface roughness becomes a serious scattering issue [1]. Another important issue is related to the random discrete dopant placement. At very small gate lengths the actual number of dopant particles in the channel is of the order of few hundred, which is quite difficult to control during fabrication process. Statistical variation causes threshold voltage variation with doping levels as shown in Fig 5.1 [1]. It can be seen from the figure that as the channel doping is increased the threshold variation increases especially above 1018 /cm3.
98
Figure 5.1 NMOS threshold voltage variation with channel doping due to random discrete dopant fluctuation [1].
In this chapter we have investigated the effects on the device characteristics of process variations due to the body thickness, gate length and gate dielectric thickness.
The results have been compared with previous results reported as a study of process variations for the FinFET and the differences quantified and discussed.
5.1 Baseline Device Simulation Structure
The device structure chosen as the baseline device and studied was an n-channel silicon nanowire transistor with a diameter D=5 nm, gate oxide thickness of Tox=1 nm and a gate length L=20 nm with no overlapping of the gate with source/drain as shown in
Fig. 5.2 (a). The dual gate MOSFET’s (FinFET) structure is shown in Fig. 5.2(b). The
15 3 channel was taken as undoped (Nch=1x10 /cm ) to avoid issues with random dopant
20 3 induced fluctuations; the source and drain were doped at Ns/d=2x2 /cm . The work
99 function for the gate was adjusted to achieve an off state current of 1 nA/µm in accordance with ITRS roadmap for low operating power technology, which resulted in a gate work function of 4.344 eV which has been used for all simulations. A drain voltage of 0.8 V was chosen. The electrical and physical device structures and performance parameters are summarized in Table 5.1 along with those reported for a FinFET with nearly the same structure including the same channel length.
Figure 5.2 Device structure for the (a) Gate All Around silicon nanowire transistor and (b) Dual Gate transistor (FinFET).
100 The FinFET structure as shown above in Fig 5.2(b) is basically a dual gate transistor with thin oxides on the vertical fin sides and a fin which describes the channel.
The FinFET device used in this comparison has the same gate length, oxide thickness, and body thickness dimensions as the simulated silicon nanowire transistor described above. Fin height for the compared baseline FinFET is double the body thickness, i.e. 10 nm. Shown below in Table 5.1 are electrical and physical parameters for the silicon nanowire device.
Table 5.1 Physical and Electrical Parameters of the Silicon Nanowire Device
In the next three sections we talk about threshold voltage, current, and sub- threshold characteristics and their dependence on process variations.
5.2 Threshold Voltage
5.2.1 Effect of Channel Doping on Threshold Voltage
Traditionally channel doping has been used for adjusting the threshold voltage in planar MOSFET. With the MOSFET gate length becoming shorter than 100 nm, new problems arise with doping such channel regions such as random dopant fluctuation (see
Fig. 5.1 and 5.3) [2]. That is, due to the discrete nature of the dopant atoms, at very small dimensions the average dopant concentration for a very small volume can change
101
Figure 5.3 Random placement of dopant at concentration of 2x1019/cm3 at channel length of 20 nm and thickness 5 nm [1].
markedly with the addition or subtraction of a few atoms. As a starting point in this study of process variations, the effect of variation in the channel doping was examined.
However, another study has showed that as we scale MOSFETs threshold voltage (Vth) becomes more insensitive to doping densities because of band gap splitting (see Fig. 5.4)
[3]. Fig 5.5 shows the result of our study for a FinFET with a 20 nm gate length and 5 nm
Figure 5.4 Simulated threshold voltage (Vth) versus channel doping (NA) at Vd= 50 mV for different channel lengths for a DG FET reported by Chiang [3].
102
Figure 5.5 Simulation result for threshold voltage variation with channel doping for silicon nanowire FET (solid) and a double gate FET (dashed) [1].
body thickness showing negligible threshold voltage variation up to a 1018 /cm3 doping with very similar result seen for the nanowire FET. This result further emphasizes the need for metal gates for adjusting the threshold voltage for scaled MOSFETs. Nanowire transistors have a wrap around structure exhibit more band splitting due to stronger quantum effects as compared to FinFET devices; hence it is expected to show an even smaller threshold variation with doping which is what is seen in Fig 5.5. It should be noted that reported threshold voltage variation by Chiang et al (Fig. 5.4) for a 25 nm long gate and 7 nm body thickness is ~ 0.15 V, which is comparable to ~ 0.10 V for the 20 nm long and 5 nm thick FinFET (Fig. 5.5) reported by Xiong & Bokor [3][1]. The simulated silicon nanowire transistor, as expected, shows an overall threshold voltage shift of about
0.14 V as compared to 0.26 V for the FinFET structure demonstrated by Xiong & Bokor
103 at a channel doping of 2x1019/cm3 [1]. Since undoped channels are preferred due to uncertainties in the threshold voltage due to statistical dopant fluctuations, this difference between the nanowire FET and double gate FinFET is inconsequential.
5.2.2 Effect of Diameter on Threshold Voltage
In this study the simulated results for the nanowire transistor showed that threshold voltage depends significantly on the nanowire diameter. As the nanowire diameter is reduced, there is stronger gate control of the charge in the channel which reduces the short channel effects and increases Vth. Another factor which starts to dominate at smaller diameters is the quantum confinement effect discussed earlier in chapter 1. As we decrease the diameter the energy levels go up due to more significant quantization and larger splitting of the band gap. At very small
Figure 5.6 Threshold voltage variation of FinFET structure with varying body thickness by Xiong & Bokor. [1]
104 diameters the lowest subband edge lies above the conduction band of the bulk. This raises the total energy of the electrons in the inversion layer and more band bending is required leading to an increase in the threshold voltage [1]. It has been shown experimentally that this quantum confinement effect is more serious in nanowires than silicon-on-insulator
(SOI) film transistors [4]. Fig. 5.6 above shows the results reported by Xiong & Bokor
[1] for the threshold voltage variation for the FinFET device using both classical theory
Figure 5.7 Simulation result for threshold voltage shift with diameter for silicon nanowire FET (solid) and a double gate transistor (dashed) [1].
and including quantum effects. It can be seen that it becomes important to incorporate quantum effects at smaller body thickness (<5 nm). Our simulation results for the nanowire FET (Fig. 5.7) show a similar trend with a Vth shift of about 0.15 V higher for the silicon nanowire transistor as compared to FinFET at a body thickness of 2 nm.
105 Threshold voltages were set to zero for the baseline devices to obtain the voltage shift values shown in Fig 5.7. It should be noted that quantum effects start showing marked effects below 5 nm and nanowire Vth rises more quickly below 4 nm compared to FinFET device. A silicon nanowire transistor shows a rate of variation of about 34-49 mV/nm around the baseline device thickness of 5 nm, which is comparable to 33 mV/nm for the
FinFET structure [1]. The total threshold voltage shift over the range of 2 – 8 nm diameter thickness for SiNW is 0.426 V as compared to 0.229 V exhibited by the FinFET structure.
5.2.3 Effect of Gate Length on Threshold Voltage
The dependence of the threshold voltage variation gate length has been well studied. Threshold voltage roll-off at small gate length due to short channel effects is
Figure 5.8 Threshold voltage variation with gate length for FinFET structure reported by Xiong and Bokor [1].
106 particularly visible in simulation results for FinFETs such as those of Xiong and Bokor shown in Fig. 5.8. As can be seen from the figure, the threshold voltage roll-off follows an exponential curve for the FinFET [1]. Fig. 5.9 provides a Vth comparison as the gate length is varied for the nanowire and FinFET device based on our simulation results.
Looking at the figure an important thing that can be noted is the scaling advantage that the nanowire FET exhibits over the dual-gate devices. It can be seen from Fig. 5.9 below that SiNW FET shows significantly less rate of threshold voltage variation of ~ 2 mV/nm as compared to ~ 9 mV/nm for FinFET around the baseline device structure at gate length of 20 nm. It should be also noted that Vth roll-off for the SiNW zFET begins at much smaller gate lengths ~ 15 nm versus an onset around 25 nm for the FinFET. In addition,
Figure 5.9 Simulation results for threshold voltage variation with gate length for SiNW and FinFET device [1].
107 the nanowire FET exhibits a smaller total voltage drop of ~ 0.1V as compared to that of a
FinFET (~0.3V) as the gate length is downscaled from 40 nm to 10 nm. This is expected to enable easier transitioning of circuit designs to newer technology nodes with shorter gate lengths when the nanowire FET is employed.
5.2.4 Effect of Oxide Thickness on Threshold Voltage
The gate oxide thickness strongly influences the extent of gate control for the
MOSFET. A thinner gate oxide leads to better electrostatic gate control over the channel and leads to higher threshold voltages and lower OFF state currents. Fig. 5.10 shows variation of threshold voltage plotted versus the inverse of oxide thickness for a FinFET structure as reported by Xiong & Bokor [1]. It can be seen from the figure that it follows an exponential curve variation with inverse oxide thickness. By comparison Fig. 5.11
Figure 5.10 Threshold voltage variations for FinFET with varying oxide thickness reported by Xiong and Bokor [1].
108
Figure 5.11 Simulation results for threshold voltage variation with inverse oxide thickness for SiNW and FinFET [1].
shows the threshold voltage variation for a silicon nanowire transistor as compared to a
FinFET device based on our simulations. It can be seen that with the nanowire FET shows much smaller threshold voltage sensitivity to the oxide thickness variation is seen as compared to the FinFETs. Threshold voltage sensitivity was measured to be 1.2 mV/Å for the nanowire transistor while it was found to be 5 mV/Å for the FinFET device at the oxide thickness for the baseline device of 1 nm [1]. This is an important result since process variations complicate circuit design in practice.
109 5.3 ON-Current, OFF-Current and ON/OFF Current Ratio
5.3.1 Current Variation with Nanowire Diameter
The ON and OFF current values are dependent on device’s physical parameters such as gate length, diameter or body thickness and oxide thickness. Variation in currents with the nanowire diameter is sensitive and the point of study in this section. We have defined the ON state current as the current value at the gate voltage Vg= 0.8 V and drain voltage Vd = 0.8 V while OFF state current is defined at Vg=0 V and Vd=0.8 V. Here we take a look at variation in the ON current, the OFF current and the ON/OFF current ratio with changes in the diameter. Fig. 5.12 shows variation in ON current with body thickness for a FinFET device at a gate length of 20 nm as reported by Xiong & Bokor
[1]. It can be seen that including quantum effects leads to a lower ON current by about
Figure 5.12 Variation of ON current with body thickness for a FinFET device reported by Xiong & Bokor [1].
110
Figure 5.13 Simulation result for ON current variation with diameter for SiNW and FinFET devices [1].
16% at a 5 nm body thickness [1]. Fig. 5.13 shows our simulation results for a comparison for 20 nm long silicon nanowire device with a 20 nm long FinFET device.
The silicon nanowire device shows a ON current variation of about 2.6-5.1% around a nominal body thickness of 5 nm which is comparable to the reported FinFET results of 5-
7% variation [1]. An interesting observation from the simulation results is rapid reduction in Ion with decreasing the diameter size because of increased quantum confinement effect, especially for the nanowire FET below ~ 3 nm. Simulation results show a 3x reduction for nanowire as diameter changes from 3 nm to 2 nm while the FinFET showed only a
1.5x for the same range of diameter [1]. This observation is in accordance with the previously reported results by Zhao et al. that the quantum confinement effects become serious beyond 2.2 nm diameter [5]. Also, we observe that this effect is more prominent
111 in silicon nanowire as compared to a FinFET especially below 3 nm, as the results show in Fig. 5.13 [1]. We also observe that the ON current for silicon nanowire is much higher than the reported FinFET values. A plausible reason for this observation can be the ballistic transport conditions assumed for nanowire FET device modeling used in this study.
A similar performance difference is seen in OFF state current variation for both the compared devices. It can be observed from the results of Xiong & Bokor [1] for
FinFET from Fig. 5.14 that there is rapid reduction in OFF current as the body thickness is reduced below 8 nm for a FinFET, which is even larger when quantum effects are included. Fig. 5.15 shows our simulation results for a silicon nanowire device compared to FinFET structure. The results are very similar to those of Xiang & Bokor [1] and nearly the same for the nanowire FET and FinFET down to a diameter of 3 nm. However,
Figure 5.14 Variation of OFF current with body thickness for FinFET structure reported by Xioing & Bokor [1].
112 it should be noted that silicon nanowire shows about three orders more Ioff reduction as compared to FinFET at a diameter of 2 nm. The Ioff variation with body thickness is quite high and comparable for both the devices, 4-7x /nm for nanowire and 5x /nm for the
FinFET structure around the baseline body thickness or diameter of 5 nm[1]. Such a high variation in off current can be an impediment for device scaling and requires more sophisticated lithography tools for future device designs to better control the body thickness or diameter.
Fig. 5.16 shows the ON/OFF current ratio variation with varying diameter based on our simulations. It is interesting to see that both the curves show an increasing current ratios with decreasing diameters. The possible reason for it is much more rapid decline in
OFF state current as compared to the ON state current as the diameter is reduced which is
Figure 5.15 Simulation results for OFF current variation with diameter for SiNW and FinFET devices [1].
113
Figure 5.16 Simulation results for ON/OFF current variation along diameter for silicon nanowire and FinFET devices[1].
likely due to quantum effects. The silicon nanowire current ratio is observed to be higher than that for the FinFET by an order of one or two. The most probable reason for this observation is the ballistic transport assumed in our simulation approach for nanowire
FET.
5.3.2 Current Variation with Gate Length
The gate length is a critical physical parameter in determining the MOSFET’s performance. The ON and OFF current’s variation with gate length is studied in this section. Silicon nanowires being gate all around devices have better control over short channel effects than double gate transistors. In this study Ion variation with the gate length for nanowire FET devices (shown in Fig. 5.17) was found to be much lower 0.17-0.2%
114 as compared to 2-3% reported for FinFET device [1]. Also, our simulation results for the variation in the OFF current with gate length were found to be much less at 0.6x /nm for nanowire FET (as can be seen in Fig. 2.17) as compared to 1.7x /nm for FinFETs [1].
This is the result of the much longer channel length than the nanowire diameter and the improved gate control with the surrounding gate for the nanowire FET.
4.6e-5
4.5e-5
4.4e-5
4.3e-5
4.2e-5
ON current, Ion (A) ON current, 4.1e-5
4.0e-5
3.9e-5 5 1015202530354045
Gate Length, L (nm)
Figure 5.17 Simulation results for ON current variation along gate length for silicon nanowire FET.
115 7e-10
6e-10
5e-10
4e-10
3e-10
2e-10 OFF current, Ioff (A) 1e-10
0
5 1015202530354045
Gate Length, L (nm)
Figure 5.18 Simulation results for OFF current variation along gate length for silicon nanowire FET.
5.4 Effect of Process Variation on Subthreshold Characteristics
5.4.1 DIBL and Subthreshold Slope Variation with Diameter
Drain Induced Barrier Lowering (DIBL) and subthreshold slope (SS) are
important parameters for a device and signifies the extent of its gate control. As discussed
in chapter 1, an increase in DIBL and subthreshold slope are the short channel effects that
show up with downscaling of MOSFETs. Fig 5.19 shows the variation of DIBL with
diameter for 20 nm FinFET device reported by Xiong & Bokor [1]. It can be seen that
116 DIBL curve follows a second order variation with body thickness where the DIBL value increases with increasing body thickness as a wider channel leads to smaller gate control and increasing short channel effects. By comparison, Fig. 5.20 shows the DIBL variation comparison for silicon nanowire with that for the FinFET based on our simulations. Our results are in excellent agreement with those of Xiong & Bokor [1] for the FinFET. It can be seen from the figure that the nanowire device shows a variation in DIBL with changes in the diameter of about 4-5.33 mV/nm. By comparison, the intrinsic nanowire device showed a DIBL value of 12 mV/V at a diameter of 5 nm. These values are much lower compared to the FinFET structure, which shows a variation of 17 mV/nm with changes in the diameter and the nominal DIBL for a FinFET around baseline device is 50 mV/V at a thickness of 5 nm[1]. The excellent gate control characteristic of nanowire devices
Figure 5.19 Variation of DIBL with body thickness for a FinFET structure as reported by Xiong & Bokor [1].
117
Figure 5.20 Simulation results for DIBL variation with diameter for SiNW and FinFET devices [1].
Similarly, superior subthreshold slope characteristics are displayed by nanowire devices over the FinFET structure. Fig. 5.21 shows the subthreshold slope variation of a
FinFET structure with varying body thickness reported by Xiong & Bokor [1]. It can be seen from the figure that the curve follows an exponential track. As discussed earlier in this chapter, the slope degrades with increasing body thickness due to increasing short channel effects. By comparison, Fig 5.22 shows the variation of silicon nanowire device as compared with a FinFET device based on our simulations. Again, our results are in good agreement with Xiong & Bokor [1] for the FinFET. The subthreshold slope for nanowire device is nearly ideal at 61.07 mV/dec as compared to 68.4 mV/dec for the
FinFET device at 5 nm diameter [1] but degrades with increasing diameter. Owing to
118
Figure 5.21 Variation of subthreshold slope with body thickness for FinFET structure reported by Xioing & Bokor [1].
Figure 5.22 Simulation results for subthreshold slope variation with diameter for SiNW and FinFET [1].
119 better gate control for the nanowire FET, it exhibits much smaller slope variation of 0.87-
1.16 mV/dec//nm compared to 4 mV/dec/nm for FinFET as the diameter is varied, as shown in Fig. 5.22 [1]. Also, the nanowire FET shows a full range swing of only 6 mV/dec compared to 26 mV/dec for FinFET design [1].
5.4.2 DIBL and Subthreshold Slope Variation with Oxide Thickness
The effects of oxide thickness variation on the short channel effect parameters were also studied for the nanowire devices; the results are shown in Fig. 5.23 and Fig.
5.24. In Fig. 5.23 we see a DIBL variation of about 16 mV/V for the range of oxide
Figure 5.23 Simulation results for DIBL variation with oxide thickness for silicon nanowire device.
120
Figure 5.24 Simulation results for subthreshold slope variation with oxide thickness for the SiNW device. thickness from 0.5 nm to 2 nm for the nanowire FET where the DIBL variation around the nominal thickness of 1 nm oxide is about 1.2 mV/Å. Similarly, as seen in Fig. 5.24, the subthreshold swing for the same oxide variation is ~ 4 mV/dec and the variation around nominal thickness is 0.242 mV/Å as compared to 1.4 mV/Å for FinFET [1].
These results for the DIBL and Subthreshold swing are excellent for the nanowire FET and improve as the oxide thickness is reduced.
5.5 Results and Conclusions
A summary of the simulation results for compared nanowire FET and FinFET devices is shown in Table 5.2. We can infer from the values in the table that the silicon nanowire FETs are less sensitive to variations in the body thickness compared to FinFET
121 devices. It can be seen that nanowires show somewhat higher threshold voltage (33-49 mV/nm Vs 33 mV/nm), but less ON current variation (2.6-5.1% mV/nm Vs 5-7%) and very similar OFF current (4-7x /nm Vs 5x /nm) sensitivity with the diameter.
However, short channel effects like subthreshold slope (0.87-1.16 mV/dec Vs 4 mV/dec) and DIBL (4-5.33 mV/nm Vs 17 mV/nm) are better controlled in the nanowire
FET with variations in the body thickness owing to better gate control.
Parameter variation sensitivity with variation in the gate length was also examined and was found to be much lower for the nanowire FET compared to FinFETs, i.e. threshold voltage (1.5-2.5 mV/nm Vs 9 mV/nm), ON current (0.17-0.2 % Vs 2-3 %) and OFF current (0.6x /nm Vs 1.7x /nm). It is again a result of the superior short channel effects exhibited by nanowires device over FinFETs.
Finally, the oxide thickness variation sensitivity was examined. Again it was found to be less for the silicon nanowire FET than FinFETs with threshold voltage variation being 1.2 mV/Å Vs 5 mV/Å for the FinFET and the OFF current being 0.6x /nm
Vs 1.7x /nm. The ON current variation shows a similar variation for the two devices, i.e.
3.6-7% as compared to 4% for FinFET. Here again we found improved short channel effects with a much smaller subthreshold slope variation of 0.242 mV/Å compared to 1.4 mV/Å.
In conclusion, it can be argued that silicon nanowires show superior short channel effects over FinFETs. However, sensitivity to variation in the diameter is much more pronounced for silicon nanowire due to enhanced quantum effects for very small nanowire diameters, i.e. below 3 nm.
122 Table 5.2 Process Variation Sensitivity Comparison for Silicon Nanowire FET and FinFET Devices around Baseline Structure for a Gate length of 20 nm.
SiNW FET (20nm) FinFET (20nm) [1]
Change in Vth with body thickness 34-49 mV/nm 33 mV/nm
Change in ION with body thickness 2.6-5.1 % 5-7 %
Change in IOFF with body thickness 4-7x /nm 5x /nm
Change in SS with body thickness 0.87-1.16 mV/dec 4 mV/dec
Change in DIBL with body thickness 4-5.33 mV/nm 17 mV/nm
Change in Vth with gate length 1.5-2.5 mV/nm 9 mV/nm
Change in ION with gate length 0.17-0.2 % 2-3 %
Change in IOFF with gate length 0.6x /nm 1.7x /nm
Change in Vth with oxide thickness 1.2 mV/Å 5 mV/Å
Change in ION with oxide thickness 3.6-7 % 4 %
Change in IOFF with oxide thickness 0.28-0.32x /Å 5.2x /Å
Change in SS with oxide thickness 0.242 mV/Å 1.4 mV/Å
123 REFERENCES
[1] S. Xiong and J. Bokor "Sensitivity of double-gate and FinFETDevices to process variations," IEEE Trans. Electron Devices, vol. 50, pp. 2255, 2003.
[2] D. J. Frank, Y. Taur, M. Ieong, and H.-S. P. Wong, “Monte Carlo modeling of threshold variation due to dopant fluctuations,” in VLSI Tech. Dig., 1999, pp. 169–170.
[3] M.-H. Chiang “Threshold voltage sensitivity to doping density in extremely scaled
MOSFETs,” Semiconductor Science and Technology, v. 21 issue 2, 2006, p. 190.
[4] Majima, "Experimental evidence for quantum mechanical narrow channel effectin ultra-narrow MOSFET's," IEEE Electron Device Lett., vol. 21, pp. 396, 2000.
[5] X. Zhao, C. Wei, L. Yang and M. Chou, "Quantum confinement and electronic properties of silicon nanowires," Phys. Rev. Lett., vol. 92, pp. 236805, 2004.
124 Chapter 6
Conclusion & Future Work
6.1 Conclusions
In this study we have investigated the electrical characteristics of an n-channel
Silicon Nanowire Field Effect Transistor (FET) using the quantum-ballistic transport model. As a starting point a comparative study was done between an experimental and simulation device. Both the simulated and experimental devices showed similar subthreshold characteristics and OFF state current. The ON current for the simulation result was higher owing to the ballistic transport model selected. The results were impressive which provided us confidence to move on with further simulations. Later, a simulation study was conducted to assess the advantages of silicon nanowire FET over
Double Gate FET. It was found that nanowire FET exhibited superior current characteristics and controlled short channel effects better.
An optimization study was also conducted for the 25 nm node considering a 10 nm gate length silicon nanowire FET as the device. Both High Performance (HP) and
Low Operating Power (LOP) were considered and an optimized design window was achieved. The optimized device was able to achieve the required ON and OFF currents for both the technology applications. Excellent subthreshold characteristics were also achieved with a DIBL value of 53.33 mV/V and subthreshold slope of 66.67 mV/dec. A
MOSFET scaling study done in the succeeding section which delved into future
125 technology nodes from 32 nm to 14 nm. It was interesting to find that at gate lengths below ~ 10 nm even a silicon nanowire FET displayed excessive short channel effects.
In the next chapter a comparative study on process variation sensitivity was performed in comparison with that for a FinFET structure. In general, the nanowire FET showed less process sensitivity than the FinFET. However, it was found that a silicon nanowire FET showed much higher sensitivity along the diameter (body thickness) at values < 4 nm due to quantum confinement effects. Also it was seen that much smaller variation was exhibited for the nanowire FET for varying gate length owing to the excellent gate control properties of silicon nanowire FET.
In conclusion, the simulation study revealed that the silicon nanowire FET is an attractive candidate for FET device design for future technology nodes. It is expected that a nanowire FET can carry forward MOSFET downscaling to ~ 10 nm gate lengths.
However, quantum effects would start playing an important role as device shrinks deep into sub-10nm nanometer regime.
6.2 Future Work
The current transport model used for simulations assumes a ballistic transport, i.e. carrier transport without any scattering in the channel. A more accurate transport model could be used bringing into account the surface scattering effects, which start to dominate at very small diameters (<5 nm) [1]. Also the simulation software assumes an ideal wrap around gate for the nanowire FET. Since this ideal structure is not possible in practice, changes can be incorporated into the device structure to more faithfully reproduce the actual device structure. Also, as new materials are being used for fabrication of
126 MOSFETs as discussed in chapter 1, further work could be done by simulating nanowire
FET with new materials such as SiGe nanowire channel and high-k dielectrics.
127 REFERENCES
[1] Wang, "Theoretical investigation of surface roughness scattering in silicon nanowire transistors," Appl. Phys. Lett., vol. 87, pp. 043101, 2005.
128