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University of Cincinnati UNIVERSITY OF CINCINNATI Date:___________________ I, _________________________________________________________, hereby submit this work as part of the requirements for the degree of: in: It is entitled: This work and its defense approved by: Chair: _______________________________ _______________________________ _______________________________ _______________________________ _______________________________ A Simulation Study of Silicon Nanowire Field Effect Transistors (FETs) A thesis submitted to the Division of Graduate Studies and Research of the University of Cincinnati in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE in the Department of Electrical and Computer Engineering and Computer Science of the College of Engineering July, 2007 by Saumitra Raj Mehrotra B.E. (Instrumentation & Control Engineering), Department of Instrumentation & Control Engineering, University of Delhi, Delhi, India 2005. Thesis Advisor and Committee Chair: Dr. Kenneth P. Roenker Committee Members: Dr. Fred R. Beyette, Dr. Punit Boolchand Abstract Silicon planar MOSFETs are approaching their scaling limits. New device designs are being explored to replace the existing planar technology. Among the possible new device designs are Double Gate (DG) FETs, FinFETs, Tri-Gate FETs and Omega- Gate FETs. The Silicon Nanowire Gate All Around (GAA) FET stands out as one of the most promising FET designs due to its maximum gate effect in controlling the short channel effects. Recent developments such as synthesis of highly ordered nanowires and fabrication of nanowires as small as 1nm in diameter have illustrated the progress possible in silicon nanowire technology In this study we have explored the silicon nanowire FET as a possible candidate to replace the currently planar MOSFETs. In this thesis we investigated the silicon nanowire FET device and compared its performance with that of a double gate (DG) FET. The software used for the study assumed quantum-ballistic transport (NanoWire), which was developed at Purdue University. Initially, we presented a comparison of Nanowire FET with DG FET with for devices with same physical parameters. It was seen that superior subthreshold characteristics are exhibited by a silicon nanowire FET. We also conducted an optimization study for the 25 nm node from the ITRS report. The final device was optimized for both High Performance and Low Operating Power applications. A further study on future technology nodes down to the 14 nm node was performed which revealed short channel effects becomes significant at gate lengths ~ 5 nm even for a silicon nanowire device. Finally, a process variation study was conducted in comparison with a FinFET device. It was concluded that a silicon nanowire FET shows less sensitivity to process variation except it has higher sensitivity in variation with the diameter at less than ~4 nm than for FinFET where significant quantum effects set in. Variation with the gate length was found to be much less sensitive for the silicon nanowire FET because of its superior gate control characteristics. Acknowledgements I would like to express my gratitude to the faculty and students of the University of Cincinnati for making my stay here a pleasant experience. In particular, I would like to thank Dr. Kenneth. P. Roenker for guiding and helping me complete this work. Thanks are due to Dr. Fred R. Beyette and Dr. Boolchand for agreeing to be part of my thesis defense committee and for their help in clarifying a lot of questions I had during my period of stay here. I would like to thank my former and present lab members, Joe, Subu and Martin for the various discussions we had, both technical and otherwise. It was fun to be part of this research group and share the time in the laboratory. Special thanks to my parents and my brother for helping me successfully overcome some difficult times during the period of my stay here. Contents 1. Introduction 1 1.1 Moore’s Law 2 1.2 MOS Transistor 4 1.3 Scaling of MOSFETs 5 1.4 Scaling Issues and Approaches 8 1.4.1 Short Channel Effects 9 1.4.2 Gate Oxide 12 1.4.3 New Materials 14 1.5 Issues at Nanoscale Level 17 1.6 Non Classical Device Structures 22 1.6.1 Ultrathin Body Single Gate MOSFET 22 1.6.2 Dual Gate FET/ FinFET 23 1.6.3 Trigate FET/ Omega Gate FET 26 1.7 Silicon Nanowire Technology 27 1.8 Purpose of Thesis 33 1.9 Organization of Thesis 34 2. Simulation Software: Theory and Preview 41 2.1 Classification of Transport Models 42 i 2.2 Simulation Software Description 43 2.3 Simulation Tool Preview 50 2.4 Comparison with Experimental Results 55 2.5 Conclusion and Summary 59 3. Device Simulation Results and Comparison for n-channel Silicon Nanowire FET 61 3.1 Baseline Device Structure 62 3.2 Device Simulations Results 63 3.2.1 Comparison of a SiNW FET with DG FET 63 3.2.2 Effects of Scaling on Silicon Nanowire FET Parameters 67 3.3 Results and Discussions 70 4. Device Optimization and Scaling Potential for a Silicon Nanowire FET 72 4.1 Device Optimization study of Silicon Nanowire FET for the ITRS 25 nm node. 73 4.1.1 Device Simulation Structure 73 4.1.2 Simulation Results for the Optimization Study 75 4.2 Scaling Potential of Silicon Nanowire FET 87 4.2.1 Scaling of MOSFETS beyond 45 nm node 87 ii 4.2.2 Device Simulation Structure 89 4.2.3 Simulation Results 89 4.3 Conclusions and Discussions 96 5. Process Sensitivity Study for Silicon Nanowire Transistors 98 5.1 Baseline Device Simulation Structure 99 5.2 Threshold Voltage 101 5.2.1 Effect of Channel Doping on Threshold Voltage 101 5.2.2 Effect of Diameter on Threshold Voltage 104 5.2.3 Effect of Gate Length on Threshold Voltage 106 5.2.4 Effect of Oxide Thickness on Threshold Voltage 108 5.3 ON-Current, OFF-Current and ON/OFF Current Ratio 110 5.3.1 Current Variation along Diameter 110 5.3.2 Current Variation with Gate Length 114 5.4 Effect of Process Variation on Subthreshold Characteristics 116 5.4.1 DIBL and Subthreshold Slope Variation with Diameter 116 5.4.2 DIBL and Subthreshold Slope Variation with Oxide Thickness 120 5.5 Results and Conclusions 121 iii 6. Conclusions & Future Work 125 6.1 Conclusions 125 6.2 Future Work 126 iv List of Figures Figure 1.1 Increasing number transistors with each new microprocessor technology [50] Figure 1.2 3-D view of a basic n-channel MOSFET. Figure 1.3 Constant field scaling and constant voltage scaling parameters [49]. Figure 1.4 Industry-trend scaling (points) contrasted with classical scaling (dashed lines) [18]. Figure 1.5 History and trends for supply voltage (Vdd), threshold voltage (Vt) and oxide thickness (tox) versus channel length for CMOS logic technologies [19]. Figure 1.6 Potential contour for a (a) long channel device and a (b) short channel device [20]. Figure 1.7 Short-channel threshold roll off: measured low- and high- drain threshold voltage of n- and p- MOSFET’s versus channel [20]. Figure 1.8 Band diagram for a (a) long channel and a (b) short channel device. Figure 1.9 Calculated gate oxide tunneling current vs gate voltage for different oxide thickness [19]. Figure 1.10 Strained silicon grown over a silicon germanium (SiGe) layer [22]. Figure 1.11 (a) Increased mobility and (b) drain current with strained Si technology [23]. Figure 1.12 High-k and metal gate technology proposed by Intel (production year: 2007) [26]. Figure 1.13 Degradation of subthreshold slope due to source-drain tunneling at gate lengths below 10nm. [27]. Figure 1.14 Off current increase with decreasing gate length due to source-drain tunneling for a dual gate device at Vds=1V, Tsi=2nm, tox=1nm [27]. Figure 1.15 Threshold voltage increase with reducing SOI channel width [29]. v Figure 1.16 Variation in Id-Vg curves with different discrete dopant distribution for 24 devices. Solid dots indicate the conventionally doped device. It shows 20- 30mV variation along gate voltage, 30mV shift in subthreshold region and 15 mV shifts in linear region [30]. Figure 1.17 (a) Schematic diagram for UTB MOSFET [33] (b) TEM image of a UTB device [34]. Figure 1.18 Dual-Gate FET structure (left) and a FinFET structure (right) Figure 1.19 More ideal subthreshold slope/DIBL evident for double gate (DG) FET as compared to a single gate (SG) FET [47]. Figure 1.20 (a) Id-Vg (top) and Id-Vd curves (b) SEM image and gate profile (c) TEM image of a FinFET [35]. Figure 1.21 Schematic diagram for a (a) TriGate FET [36] (b) Omega-Gate FET [37]. Figure 1.22 SEM image of (a) 200 nm long silicon nanowire and (b) after gate electrode definition ; 4 nm grown oxide followed by 130 nm amorphous silicon. [51]. Figure 1.23 (a) Schematic of the back gate SiNW FET (b) TEM image of a 5nm diameter SiNW [38]. Figure 1.24 Size-controlled synthesis of SiNW from Au nanoclusters for diameter control [44]. Figure 1.25 Id-Vd curve for the back gate silicon nanowire transistor [38]. Red curve is after annealing. Figure 1.26 TEM image of fabricated GAA silicon nanowire transistor structure [14]. Figure 1.27 Id-Vd and Id-Vg curves for a 5 nm diameter GAA silicon nanowire transistor [14]. Figure 2.1 Schematic of intrinsic nanowire device with circular cross section [3]. Figure 2.2 Mesh generated at each slice of the nanowire device for simulations [3]. Figure 2.3 Snapshot of the interface of the NanoWire simulation tool. Figure 2.4 Snapshot of Id-Vd curve for the baseline device (Vg=0.8V).
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