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Needs and Opportunities for Nanotribology in Mems and Nems R.W NEEDS AND OPPORTUNITIES FOR NANOTRIBOLOGY IN MEMS AND NEMS R.W. Carpick 1*, G.E. Wabiszewski1, F. Streller2 1 Dept. of Mechanical Engineering and Applied Mechanics, U. Pennsylvania, Philadelphia, Pennsylvania, USA 2 Dept. of Materials Science and Engineering, U. Pennsylvania, Philadelphia, Pennsylvania, USA ABSTRACT Nanoelectromechanical systems (NEMS) switches are a can- NEMS Switches as an Alternative to the Transistor didate “beyond CMOS” technology, with a key benefit being mas- Ohmic NEMS switches provide the same functionality as the sively reduced power consumption. However, the reliability of the conventional metal-oxide-semiconductor field-effect transistor contact interface is a principal challenge, as the electrically con- (MOSFET). In both technologies, the application of a gate signal ducting contacting surfaces need to be able to open and close up to results in current transfer from the source to drain. However, a quadrillion times without excessive adhesion, wear, or contami- CMOS relies on a fully-electronic, semiconductor junction to nation. Similar failure mechanisms occur in microelectromechani- achieve this functionality whereas NEMS logic switches rely on cal systems (MEMS). These failure mechanisms are not well un- the mating of conductive contacts (see Figure 1). derstood, and materials that can exhibit the needed performance NEMS ohmic switches utilize mechanical motion to modulate have not yet been demonstrated. Here we highlight key challenges the distance between two conductive contacts which serve as the and opportunities for applying scientific insights from nanotribolo- source (S) and drain (D) electrodes. Figure 1(a) shows the topolo- gy to address these reliability challenges. gy and working principal of a NEMS switch prototype by Piazza and co-workers [5], [6]. The device is in an “off-state” when the INTRODUCTION source and drain electrodes are! separated by a physical gap, and Nanoelectromechanical systems (NEMS) switches have been the “on-state” when the source and drain electrodes are closed with identified as a potential next-generation transistor with far lower sufficient force to establish an electrical connection. The space power consumption than existing electronic integrated circuits, a separating the electrodes in the off-state is the switch gap. Ideally, critical technological need. These switches are nanoscale moving closure of the source and drain electrodes results in current flow devices that convert an electrical input signal into motion to close a from the biased source to the drain, while contact release results in conductive contact [1]. NEMS switches are thus a mechanical a near-infinitely resistive junction. Successful operation is depend- version of a transistor with topologies that often mimic larger mi- ent on reliably and repetitively making and breaking the source and croelectromechanical systems (MEMS) switches. However, NEMS drain electrodes while maintaining a conductive contact in the switches require small dimensions for the fast, competitive switch- device on-state and a high resistance in the off-state. ing speeds (<100 ns) desired in computer logic applications. The 1E10 !404% .(A) %(A)% Switching! DS nanoscale dimensions and complex operating conditions at the DS 1E10 !606% voltage!(Vact)! electrical contact make NEMS logic switches susceptible to tribo- ! 1E10 !808% Vact=!VB4Vth!! logically-mediated failure mechanisms. In particular, low contact .........V .....V B th Vact!~!0.5!V! and restoring forces may lead to device “stiction” (device perma- 1E10 !10010% .......(mV)..(mV) ! .!450...73 nently stuck closed), or intolerable increases in switch contact Rc!~ 2.3!KΩ! .!490...23 1E10 !12012% resistance due to the formation of insulating tribopolymer (TP) .!520...0.4 .!570...!51 films. It may be possible to mitigate these failures with the use of Drain0source%current%I 014 Drain!sourCe.Current.I 1E10 !14 % low adhesion and catalytically inactive contact materials. This !300 !200 !100 0 100 200 300 Gate.voltage.V (mV) paper will review the opportunities presented by NEMS switch Gate%voltage%VG%(mV)%G technology, and will discuss needs and approaches to address the Figure 1. (a) SEM top view image of a working NEMS switch. (b) technological barriers arising from tribological issues. The device shows a steep subthreshold slope, low leakage current, and low switching voltage (VB = switch body bias voltage, Vth = The Need for Low Power Computation gate threshold voltage for switching, Vact = total actuation voltage, Sustained growth in computing power and decrease in compu- RC = contact resistance). From [6]. ting cost has led to the proliferation of devices utilizing integrated An input voltage, the gate (G) signal, is converted to mechan- processors in the last half century. These processors are over- ical motion to modulate the gap. This motion can be achieved whelmingly based on fully-electronic CMOS technology. While through various means of transduction using many topologies. this technology has proven exceptional for decreasing transistor Ohmic NEMS switches utilizing electrostatic [7]–[9] and piezoe- real estate and increasing speed [2], it is currently encountering a lectric [5], [6] actuation employing a range of geometries (see “power crises.” Further scaling of CMOS leads to intractable in- review in [10]) have been demonstrated. Regardless, all ohmic creases in power loss per computation due to irreversible processes NEMS switches depend on reliable closure and separation of a inherent to the physics controlling device operation [2]–[4]. The conductive interface to achieve switching. significant power requirements of computer processors, the power CMOS faces a scaling and power crisis. Continued Moore’s crisis of conventional CMOS, trends towards smart devices, the Law scaling has contributed to increasing device leakage, resulting increasing penetration of home and laptop computers, the desire in significant power loses even when switching is not occurring for long lasting battery-operated mobile devices, and power con- [11]. Furthermore, a breakdown of Moore’s law is predicted by sumption requirements of CMOS outpacing battery capacities approximately 2020 as critical MOSFET dimensions exceed phys- motivates the need to explore lower power transistors. Recognizing ical limitations [2], [12]. Ohmic NEMS logic switches that reduce the physical limitations of existing CMOS technology, the Interna- power draw per computation have been identified in the ITRS as a tional Technology Roadmap for Semiconductors (ITRS) has in- potential next-generation technology to cohabitate or usurp FETs cluded nanoelectromechanical systems (NEMS) switches as a pos- [2]. Comparisons between NEMS relay-based logic to convention- sible disruptive, low-power technology to cohabitate or usurp the al CMOS revealed that energy savings of one to three orders of conventional, fully electronic transistor. 9781940470016/HH2014/$25©2014TRF 28 Solid-State Sensors, Actuators and Microsystems Workshop Hilton Head Island, South Carolina, June 8-12, 2014 magnitude may be achieved with NEMS relays due to the low CONTACT: NEMS’ “ACHILLES’ HEEL” power consumption at the individual switch level [13]–[15] and Despite the potential benefits of NEMS logic switches, tribo- design advantages unique to mechanical relays that reduce the logical failure mechanisms at the electrical contact interface limit number of switches necessary to perform logic operations [16]. their viability [2]. Transistor functionality critically depends on The reduced power consumption is primarily a consequence of the maintaining high isolation in the off-state and low resistance in the physics underpinning device operation [17]. Figure 1(b) demon- on-state. Failure due to stiction that results in permanent welding strates the potential power savings via the steep on-off slope and of the switch interface, wear of contact materials, adsorbed layers the low gate voltage, as low as 0.4 mV through use of a body bias. of insulating contaminant films on free surfaces, and insulating The power consumption of a digital switch is characterized by tribopolymer (TP) formation of chemomechanical origin have been power dissipated during both the off-state (VG<0, sub-threshold observed in microscale and nanoscale electrical contacts testing leakage) and on-state (VG>0, dynamic switching power). NEMS [10], [29]. The term tribopolymer (TP) is used in place of the more logic switches afford power savings both regimes [18], [19]. commonly used term “friction polymer”. Friction polymers were Off-state leakage in CMOS is dominated by source-drain and first observed in sliding electrical contacts. However, it has since gate leakage that scales unfavorably with decreasing device dimen- been observed that such polymer formation can be achieved under sions [17]. This is seen as a current offset for voltages below the normal stresses (absence of significant shear stresses)[30]. turn on threshold voltage. This leakage is due shorter and thinner The effects of stiction, insulating contaminant layers, and TP oxide gate channels necessary to continue Moore’s Law scaling. formation are expected to increase in severity as NEMS relays are Sub-threshold leakage in CMOS currently represents ~50% of the scaled down in size. This is a consequence of the dominance of total microprocessor power density [17] with standby leakage cur- surface forces and the limited closure and separation forces availa- rents of 1 nA/transistor having been reported at 250
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