2.1Charge Carrier Transport in Single-Crystal Organic Field-Effect
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Room Temperature Ultrahigh Electron Mobility and Giant Magnetoresistance in an Electron-Hole-Compensated Semimetal Luptbi
High Electron Mobility and Large Magnetoresistance in the Half-Heusler Semimetal LuPtBi Zhipeng Hou1,2, Wenhong Wang1,*, Guizhou Xu1, Xiaoming Zhang1, Zhiyang Wei1, Shipeng Shen1, Enke Liu1, Yuan Yao1, Yisheng Chai1, Young Sun1, Xuekui Xi1, Wenquan Wang2, Zhongyuan Liu3, Guangheng Wu1 and Xi-xiang Zhang4 1State Key Laboratory for Magnetism, Beijing National Laboratory for Condensed Matter Physics, Institute of Physics, Chinese Academy of Sciences, Beijing 100190, China 2College of Physics, Jilin University, Changchun 130023, China 3State Key Laboratory of Metastable Material Sciences and Technology, Yanshan University, Qinhuangdao 066004, China 4Physical Science and Engineering, King Abdullah University of Science and Technology (KAUST), Thuwal 23955-6900, Saudi Arabia. Abstract Materials with high carrier mobility showing large magnetoresistance (MR) have recently received much attention because of potential applications in future high-performance magneto-electric devices. Here, we report on the discovery of an electron-hole-compensated half-Heusler semimetal LuPtBi that exhibits an extremely high electron mobility of up to 79000 cm2/Vs with a non-saturating positive MR as large as 3200% at 2 K. Remarkably, the mobility at 300 K is found to exceed 10500 cm2/Vs, which is among the highest values reported in three-dimensional bulk materials thus far. The clean Shubnikov-de Haas quantum oscillation observed at low temperatures and the first-principles calculations together indicate that the high electron mobility is due to a rather small effective carrier mass caused by the distinctive band structure of the crystal. Our finding provide a new approach for finding large, high-mobility MR materials by designing an appropriate Fermi surface topology starting from simple electron-hole-compensated semimetals. -
Imperial College London Department of Physics Graphene Field Effect
Imperial College London Department of Physics Graphene Field Effect Transistors arXiv:2010.10382v2 [cond-mat.mes-hall] 20 Jul 2021 By Mohamed Warda and Khodr Badih 20 July 2021 Abstract The past decade has seen rapid growth in the research area of graphene and its application to novel electronics. With Moore's law beginning to plateau, the need for post-silicon technology in industry is becoming more apparent. Moreover, exist- ing technologies are insufficient for implementing terahertz detectors and receivers, which are required for a number of applications including medical imaging and secu- rity scanning. Graphene is considered to be a key potential candidate for replacing silicon in existing CMOS technology as well as realizing field effect transistors for terahertz detection, due to its remarkable electronic properties, with observed elec- tronic mobilities reaching up to 2 × 105 cm2 V−1 s−1 in suspended graphene sam- ples. This report reviews the physics and electronic properties of graphene in the context of graphene transistor implementations. Common techniques used to syn- thesize graphene, such as mechanical exfoliation, chemical vapor deposition, and epitaxial growth are reviewed and compared. One of the challenges associated with realizing graphene transistors is that graphene is semimetallic, with a zero bandgap, which is troublesome in the context of digital electronics applications. Thus, the report also reviews different ways of opening a bandgap in graphene by using bi- layer graphene and graphene nanoribbons. The basic operation of a conventional field effect transistor is explained and key figures of merit used in the literature are extracted. Finally, a review of some examples of state-of-the-art graphene field effect transistors is presented, with particular focus on monolayer graphene, bilayer graphene, and graphene nanoribbons. -
The Pennsylvania State University the Graduate School THE
The Pennsylvania State University The Graduate School THE EFFECTS OF INTERFACE AND SURFACE CHARGE ON TWO DIMENSIONAL TRANSITORS FOR NEUROMORPHIC, RADIATION, AND DOPING APPLICATIONS A Dissertation in Electrical Engineering by Andrew J. Arnold © 2020 Andrew J. Arnold Submitted in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy August 2020 The dissertation of Andrew J. Arnold was reviewed and approved by the following: Thomas Jackson Professor of Electrical Engineering Co-Chair of Committee Saptarshi Das Assistant Professor of Engineering Science and Mechanics Dissertation Advisor Co-Chair of Committee Swaroop Ghosh Assistant Professor of Electrical Engineering Rongming Chu Associate Professor of Electrical Engineering Sukwon Choi Assistant Professor of Mechanical Engineering Kultegin Aydin Professor of Electrical Engineering Head of the Department of Electrical Engineering ii Abstract The scaling of silicon field effect transistors (FETs) has progressed exponentially following Moore’s law, and is nearing fundamental limitations related to the materials and physics of the devices. Alternative materials are required to overcome these limitations leading to increasing interest in two dimensional (2D) materials, and transition metal dichalcogenides (TMDs) in particular, due to their atomically thin nature which provides an advantage in scalability. Numerous investigations within the literature have explored various applications of these materials and assessed their viability as a replacement for silicon FETs. This dissertation focuses on several applications of 2D FETs as well as an exploration into one of the most promising methods to improve their performance. Neuromorphic computing is an alternative method to standard computing architectures that operates similarly to a biological nervous system. These systems are composed of neurons and operate based on pulses called action potentials. -
3 Carbon Nanotubes – the Dispersion
DEPARTMENT OF PHYSICS UNIVERSITY OF JYVÄSKYLÄ RESEARCH REPORT No. 11/2018 DEVELOPMENT OF MICROFLUIDICS FOR SORTING OF CARBON NANOTUBES BY JÁN BOROVSKÝ Academic Dissertation for the Degree of Doctor of Philosophy To be presented, by permission of the Faculty of Mathematics and Science of the University of Jyväskylä, for public examination in Auditorium FYS1 of the University of Jyväskylä on December 13th, 2018 at 12 o’clock noon Jyväskylä, Finland December 2018 Preface The work reviewed in this thesis has been carried out during the years 2012 & 2014-2018 at the Department of Physics and Nanoscience Center in the University of Jyväskylä. First and foremost, I would like to thank my supervisor Doc. Andreas Jo- hansson for his guidance during my Erasmus internship and consequent Ph.D. studies. I am very grateful for his willingness to share both the professional com- petence and personal wisdom. Equal gratitude belongs to Prof. Mika Pettersson, without whom this project would never exist. His ability to see the big picture, his interesting insights, and genuine joy from the beauty of the microworld were a true motivation for me. It has been a great experience to work in the Nanoscience Center for all these years. I would like to express my gratitude to the whole staff for being supportive, sharing good ideas, or just having fun meaningful conversations. A special thanks goes to Prof. Janne Ihalainen for providing me access to the facilities of the Department of Biology. I humbly acknowledge the irreplaceable help of our technical staff, namely Dr. Kimmo Kinnunen, Mr. Tarmo Suppula, Dr. -
Design and Analysis of Double Gate MOSFET Devices Using High-K Dielectric
International Journal of Electrical Engineering. ISSN 0974-2158 Volume 7, Number 1 (2014), pp. 53-60 © International Research Publication House http://www.irphouse.com Design and Analysis of Double Gate MOSFET Devices using High-k Dielectric Asha Balhara* and Divya Punia Department of E.C.E., B.P.S. Women University, khanpur kalan, Sonepat, India. *E-mail id: [email protected] Abstract Double gate MOSFET is one of the most promising and leading contender for Nano regime devices. In this paper an n-channel symmetric Double-Gate MOSFET using high-k (TiO2) dielectric with 80nm gate length is designed and simulated to study its electrical characteristics. ATHENA and ATLAS simulation tools from SILVACO are used in simulating electrical performance and analyzing the effectiveness of double gate MOSFET. High-k gate technology is emerging as a strong alternative for replacing the conventional SiO2 dielectrics gates in scaled MOSFETs for both high performance and low power applications. High-k oxides offer a solution to leakage problems that occur as gate oxide thickness’ are scaled down. Non-ideal effect of a MOSFET design such as short channel effects are investigated. The most common effect that generally occurs in the short channel MOSFETs are channel modulation, drain induced barrier lowering (DIBL). It is observed in the results that the device engineering would play an important role in optimizing the device parameters. Keywords- MOSFET-metal oxide semiconductor field effect transistor; DG- MOSFET-double-gate MOSFET; SG-MOSFET-single -
Electrical Properties of Silicon Nanowires Schottky Barriers Prepared by MACE at Different Etching Time
Electrical Properties of Silicon Nanowires Schottky Barriers Prepared by MACE at Different Etching Time Ahlem Rouis ( [email protected] ) Universite de Monastir Faculte des Sciences de Monastir https://orcid.org/0000-0002-9480-061X Neila Hizem Universite de Monastir Faculte des Sciences de Monastir Mohamed Hassen Institut Supérieur des Sciences Appliquées et de Technologie de Sousse: Institut Superieur des Sciences Appliquees et de Technologie de Sousse Adel kalboussi Universite de Monastir Faculte des Sciences de Monastir Original Research Keywords: Electrical Properties of Silicon, Etching Time, symmetrical current-voltage, capacitance-voltage Posted Date: February 11th, 2021 DOI: https://doi.org/10.21203/rs.3.rs-185736/v1 License: This work is licensed under a Creative Commons Attribution 4.0 International License. Read Full License Electrical properties of silicon nanowires Schottky barriers prepared by MACE at different etching time Ahlem Rouis 1, *, Neila Hizem1, Mohamed Hassen2, and Adel kalboussi1. 1Laboratory of Microelectronics and Instrumentation (LR13ES12), Faculty of Science of Monastir, Avenue of Environment, University of Monastir, 5019 Monastir, Tunisia. 2Higher Institute of Applied Sciences and Technology of Sousse, Taffala City (Ibn Khaldoun), 4003 Sousse, Tunisia. * Address correspondence to E-mail: [email protected] ABSTRACT This article focused on the electrical characterization of silicon nanowires Schottky barriers following structural analysis of nanowires grown on p-type silicon by Metal (Ag) Assisted Chemical Etching (MACE) method distinguished by their different etching time (5min, 10min, 25min). The SiNWs are well aligned and distributed almost uniformly over the surface of a silicon wafer. In order to enable electrical measurement on the silicon nanowires device, Schottky barriers were performed by depositing Al on the vertically aligned SiNWs arrays. -
Outline MOS Gate Dielectrics Incorporation of N Or F at the Si/Sio
MOS Gate Dielectrics Outline •Scaling issues •Technology •Reliability of SiO2 •Nitrided SiO2 •High k dielectrics araswat tanford University 42 EE311 / Gate Dielectric Incorporation of N or F at the Si/SiO2 Interface Incorporating nitrogen or fluorine instead of hydrogen strengthens the Si/SiO2 interface and increases the gate dielectric lifetime because Si-F and Si-N bonds are stronger than Si-H bonds. Nitroxides – Nitridation of SiO2 by NH3 , N2O, NO Poly-Si Gate – Growth in N2O – Improvement in reliability – Barrier to dopant penetration from poly-Si gate Oxide N or F – Marginal increase in K – Used extensively Si substrate Fluorination – Fluorination of SiO2 by F ion implantation – Improvement in reliability – Increases B penetration from P+ poly-Si gate – Reduces K – Not used intentionally – Can occur during processing (WF6 , BF2) araswat tanford University 43 EE311 / Gate Dielectric 1 Nitridation of SiO2 in NH3 H • Oxidation in O2 to grow SiO2. • RTP anneal in NH3 maximize N at the interface and minimize bulk incorporation. • Reoxidation in O2 remove excess nitrogen from the outer surface • Anneal in Ar remove excess hydrogen from the bulk • Process too complex araswat tanford University 44 EE311 / Gate Dielectric Nitridation in N2O or NO Profile of N in SiO2 Stress-time dependence of gm degradation of a NMOS SiO2 Ref. Bhat et.al IEEE IEDM 1994 (Ref: Ahn, et.al., IEEE Electron Dev. Lett. Feb. 1992) •The problem of H can be circumvented by replacing NH3 by N2O or NO araswat tanford University 45 EE311 / Gate Dielectric 2 Oxidation of Si in N2O N2O → N2 + O N2O + O → 2NO Ref: Okada, et.al., Appl. -
Organic Light-Emitting Transistors with Optimized Gate Dielectric
Organic light-emitting transistors with optimized gate dielectric Supervisor: Jakob Kjelstrup-Hansen Per B. W. Jensen Jian Zeng JUNE, 2013 ABSTRACT Organic materials have been developed as promising candidates in a variety of electronic and optoelectronic applications due to its semiconducting properties, synthesis, low temperature processing and plastic film compatibility. Hence, the organic light emitting transistor (OLET) has attracted considerable interest in realizing large-area optoelectronic devices and made tremendously progress in recent years. In order to further improve the device performance, one possibility is to optimize the gate dielectric material. Typically, silicon dioxide (SiO2) works as gate dielectric. However, SiO2 traps electrons at the semiconductor/dielectrics interface, which can prevent charge carriers transport. Therefore, the focus of this project is to look into the performance of OLETs with optimized gate dielectrics and investigate the improvement compared with conventional OLETs. The optimized gate dielectric used in this project is poly(methyl methacrylate) (PMMA), which is a promising polymer material. The device is developed with bottom contact/bottom gate (BC/BG) and top contact/bottom gate (TC/BG) configuration. Taking BC/BG configuration as an example, in an OLET, silicon substrate PPTTPP thin film acting as organic semiconductor is connect to gold (Au) source and drain electrodes, which is positioned on top of PMMA layer on Au bottom layer. Aluminum (Al) also be investigated as source and drain electrode. Then a suitable microfabrication recipe is introduced, which involves the fabrication recipe of stencil. The fabrication process is realized in clean room and optical lab, followed by the electrical and optical measurements to characterize the devices. -
A Vertical Silicon-Graphene-Germanium Transistor
ARTICLE https://doi.org/10.1038/s41467-019-12814-1 OPEN A vertical silicon-graphene-germanium transistor Chi Liu1,3, Wei Ma 1,2,3, Maolin Chen1,2, Wencai Ren 1,2 & Dongming Sun 1,2* Graphene-base transistors have been proposed for high-frequency applications because of the negligible base transit time induced by the atomic thickness of graphene. However, generally used tunnel emitters suffer from high emitter potential-barrier-height which limits the tran- sistor performance towards terahertz operation. To overcome this issue, a graphene-base heterojunction transistor has been proposed theoretically where the graphene base is 1234567890():,; sandwiched by silicon layers. Here we demonstrate a vertical silicon-graphene-germanium transistor where a Schottky emitter constructed by single-crystal silicon and single-layer graphene is achieved. Such Schottky emitter shows a current of 692 A cm−2 and a capacitance of 41 nF cm−2, and thus the alpha cut-off frequency of the transistor is expected to increase from about 1 MHz by using the previous tunnel emitters to above 1 GHz by using the current Schottky emitter. With further engineering, the semiconductor-graphene- semiconductor transistor is expected to be one of the most promising devices for ultra-high frequency operation. 1 Shenyang National Laboratory for Materials Science, Institute of Metal Research, Chinese Academy of Sciences, 72 Wenhua Road, Shenyang 110016, China. 2 School of Materials Science and Engineering, University of Science and Technology of China, 72 Wenhua Road, Shenyang 110016, China. 3These authors contributed equally: Chi Liu, Wei Ma. *email: [email protected] NATURE COMMUNICATIONS | (2019) 10:4873 | https://doi.org/10.1038/s41467-019-12814-1 | www.nature.com/naturecommunications 1 ARTICLE NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-019-12814-1 n 1947, the first transistor, named a bipolar junction transistor electron microscope (SEM) image in Fig. -
3-July-7Pm-Resistivity-Mobility-Conductivity-Current-Density-ESE-Prelims-Paper-I.Pdf
_____________________________________________________________________ Carrier drift Current carriers (i.e. electrons and holes) will move under the influence of an electric field because the field will exert a force on the carriers according to F = qE In this equation you must be very careful to keep the signs of E and q correct. Since the carriers are subjected to a force in an electric field they will tend to move, and this is the basis of the drift current. Figure illustrates the drift of electrons and holes in a semiconductor that has an electric field applied. In this case the source of the electric field is a battery. Note the direction of the current flow. The direction of current flow is defined for positive charge carriers because long ago, when they were setting up the signs (and directions) of the current carriers they had a 50:50 chance of getting it right. They got it wrong, and we still use the old convention! Current, as you know, is the rate of flow of charge and the equation you will have used should look like Id = nAVdq where Id = (drift) current (amperes), n = carrier density (per unit volume) A = conductor (or semiconductor) area, vd = (drift) velocity of carriers, q = carrier charge (coulombs) which is perfectly valid. However, since we are considering charge movement in an electric field it would be useful to somehow introduce the electric field into the equations. We can do this via a quantity called the mobility, where d = E In this equation: 2 -1 -1 = the drift mobility (often just called the mobility) with units of cm V s -1 E = the electric field (Vcm ) We know that the conduction electrons are actually moving around randomly in the metal, but we will assume that as a result of the application of the electric field Ex, they all acquire a net velocity in the x direction. -
Carrier Concentrations
2 Numerical Example: Carrier Concentrations 15 -3 Donor concentration: Nd = 10 cm Thermal equilibrium electron concentration: ≈ 15 –3 no Nd = 10 cm Thermal equilibrium hole concentration: 2 2 ⁄ ≈2 ⁄ ()10 –3 ⁄ 15 –3 5 –3 po =ni no ni Nd ==10 cm 10 cm 10 cm Silicon doped with donors is called n-type and electrons are the majority carriers. Holes are the (nearly negligible) minority carriers. EECS 105 Fall 1998 Lecture 2 Doping with Acceptors Acceptors (group III) accept an electron from the lattice to fill the incomplete fourth covalent bond and thereby create a mobile hole and become fixed negative charges. Example: Boron. B– + mobile hole and later trajectory immobile negatively ionized acceptor -3 Acceptor concentration is Na (cm ), we have Na >> ni typically and so: one hole is added per acceptor: po = Na equilibrium electron concentration is:: 2 no = ni / Na EECS 105 Fall 1998 Lecture 2 Compensation Example shows Nd > Na positively ionized donors + + As As B– − negatively ionized acceptor mobile electron and trajectory ■ Applying charge neutrality with four types of charged species: ρ () ===– qno ++qpo qNd – qNa qpo–no+Nd–Na 0 2 we can substitute from the mass-action law no po = ni for either the electron concentration or for the hole concentration: which one is the majority carrier? answer (not surprising): Nd > Na --> electrons Na > Nd --> holes EECS 105 Fall 1998 Lecture 2 Carrier Concentrations in Compensated Silicon ■ For the case where Nd > Na, the electron and hole concentrations are: 2 n ≅ ≅ i no Nd – Na and po ------------------- Nd – Na ■ For the case where Na > Nd, the hole and electron concentrations are: 2 n ≅ ≅ i p o N a – N d and n o ------------------- N a – N d Note that these approximations assume that | Nd - Na|>> ni, which is nearly always true. -
Schottky Barrier Height Dependence on the Metal Work Function for P-Type Si Schottky Diodes
Schottky Barrier Height Dependence on the Metal Work Function for p-type Si Schottky Diodes G¨uven C¸ ankayaa and Nazım Uc¸arb a Gaziosmanpas¸a University, Faculty of Sciences and Arts, Physics Department, Tokat, Turkey b S¨uleyman Demirel University, Faculty of Sciences and Arts, Physics Department, Isparta, Turkey Reprint requests to Prof. N. U.; E-mail: [email protected] Z. Naturforsch. 59a, 795 – 798 (2004); received July 5, 2004 We investigated Schottky barrier diodes of 9 metals (Mn, Cd, Al, Bi, Pb, Sn, Sb, Fe, and Ni) hav- ing different metal work functions to p-type Si using current-voltage characteristics. Most Schottky contacts show good characteristics with an ideality factor range from 1.057 to 1.831. Based on our measurements for p-type Si, the barrier heights and metal work functions show a linear relationship of current-voltage characteristics at room temperature with a slope (S = φb/φm) of 0.162, even though the Fermi level is partially pinned. From this linear dependency, the density of interface states was determined to be about 4.5 · 1013 1/eV per cm2, and the average pinning position of the Fermi level as 0.661 eV below the conduction band. Key words: Schottky Diodes; Barrier Height; Series Resistance; Work Function; Miedema Electronegativity. 1. Introduction ear dependence should exist between the φb and the φm. Corresponding to this, SB heights of various el- The investigation of rectifying metal-semiconductor emental metals, including Au, Ti, Pt, Ni, Cr, have contacts (Schottky diodes) is of current interest for been reported [14 – 16].