MOS Gate Dielectrics Outline •Scaling issues •Technology •Reliability of SiO2 •Nitrided SiO2 •High k dielectrics araswat tanford University 42 EE311 / Gate Dielectric Incorporation of N or F at the Si/SiO2 Interface Incorporating nitrogen or fluorine instead of hydrogen strengthens the Si/SiO2 interface and increases the gate dielectric lifetime because Si-F and Si-N bonds are stronger than Si-H bonds. Nitroxides – Nitridation of SiO2 by NH3 , N2O, NO Poly-Si Gate – Growth in N2O – Improvement in reliability – Barrier to dopant penetration from poly-Si gate Oxide N or F – Marginal increase in K – Used extensively Si substrate Fluorination – Fluorination of SiO2 by F ion implantation – Improvement in reliability – Increases B penetration from P+ poly-Si gate – Reduces K – Not used intentionally – Can occur during processing (WF6 , BF2) araswat tanford University 43 EE311 / Gate Dielectric 1 Nitridation of SiO2 in NH3 H • Oxidation in O2 to grow SiO2. • RTP anneal in NH3 maximize N at the interface and minimize bulk incorporation. • Reoxidation in O2 remove excess nitrogen from the outer surface • Anneal in Ar remove excess hydrogen from the bulk • Process too complex araswat tanford University 44 EE311 / Gate Dielectric Nitridation in N2O or NO Profile of N in SiO2 Stress-time dependence of gm degradation of a NMOS SiO2 Ref. Bhat et.al IEEE IEDM 1994 (Ref: Ahn, et.al., IEEE Electron Dev. Lett. Feb. 1992) •The problem of H can be circumvented by replacing NH3 by N2O or NO araswat tanford University 45 EE311 / Gate Dielectric 2 Oxidation of Si in N2O N2O → N2 + O N2O + O → 2NO Ref: Okada, et.al., Appl. Phys. Lett. 63(2), 1993 •RTP oxidation shows N accumulation near the Si/SiO2 interface •Furnace oxidation shows almost uniform N profile ⇒lower Qbd araswat tanford University 46 EE311 / Gate Dielectric Dopant Penetration From Poly-Si Gate Thick gate oxide Thin gate oxide Thin nitrided gate oxide P+ Poly-Si Gate B B B B in SiO2 SiOXNY Si Si Si • Incorporation of nitrogen at the interface suppresses dopant diffusion from gate poly-Si into the channel which can can cause VT shift. • The problem is more serious for P+ poly-Si as boron diffuses more readily in SiO2. • It is desirable to use P+ gate for PMOS transistors, for scaled CMOS technology to minimize short channel effects araswat tanford University 47 EE311 / Gate Dielectric 3 MOS Gate Dielectrics Outline •Scaling issues •Technology •Reliability of SiO2 •Nitrided SiO2 •High k dielectrics araswat tanford University 48 EE311 / Gate Dielectric High-k MOS Gate Dielectrics Ichannel ∝ charge x source injection velocity ∝ (gate oxide cap x gate overdrive) vinj ∝ Cox (VGS - VT) Esource µinj Historically Cox has been increased by decreasing gate oxide thickness. It can also be increased by using a higher K dielectric K I "C " D ox thickness 40 Å 20 Å SiO2 K ≈ 4 Si N K ≈ 8 ! 3 4 Si #tox Higher thickness -> reduced gate leakage JDT "e araswat tanford University 49 EE311 / Gate Dielectric ! 4 Benefits of High-κ Gate Dielectrics Low VDD leakage Gate VDD High leakage Gate e- 60 Å High-κ κ = 16 e- V V κ = 4 15 Å SiO2 DD DD - - source e drain source e drain !tox J DT " e channel channel Si substrate Si substrate Higher-κ film ⇒ thicker gate dielectric ⇒ lower leakage and power dissipation with the same capacitance !" A ') high $ C = 0 ⇒ t % () " t ox high() = ! SiO2 tox % ) " & SiO2 # Historically Cox has been increased by decreasing gate oxide thickness. It can also be increased by using a higher K dielectric araswat tanford University 50 EE311 / Gate Dielectric Alternatives to SiO2: Silicon Nitride (Ref: Guo & Ma, IEEE Electron Dev. Lett. June. 1998) A factor of 2 increase in K Reduction in bandgap ⇒ increased gate leakage araswat tanford University 51 EE311 / Gate Dielectric 5 Nitridation of Silicon Thermal Nitridation of Si in NH3 Id - Vg of 1.5 µm Si3N4 gate NMOS ) A 25 Å Si3N4 m ( Vg = 2V t n e r r u 1.5V C n i a r D 1V 0.5V Drain Voltage (V) (Ref: Moslehi & Saraswat, EEE Trans. Electron Dev. Feb. 1985) • Si reacts with NH3 to grow Si3N4 – Excellent gate dielectric properties – Reaction needs very high temperatures • Si reacts with atomic nitrogen – Reaction temperature could be reduced using nitrogen plasma – More research needed • Several deposition methods under investigations, e.g., rapid thermal CVD, jet vapor deposition (JVD) araswat tanford University 52 EE311 / Gate Dielectric Nitride / Nitroxide Sandwich Gate MOS Id 1.2 nm EOT Gate dielectric Ig Ref: Q. Xiang, et.al., (AMD), IEDM 2000 • 1.2 nm EOT (Equivalent oxide thickness) gate dielectric can be formed by 1.2 nm EOT - thermally growing ultrathin oxinitride - CVD of Si3N4 • Low gate leakage • 40 nm channel length CMOS demonstrated Ref: M. Bohr, (Intel), IEDM 2002. araswat tanford University 53 EE311 / Gate Dielectric 6 Requirements for the MOS gate dielectrics • High dielectric constant ⇒ higher charge induced in the channel • Wide band gap ⇒ higher barriers ⇒ lower leakage • Ability to grow high purity films on Si with a clean interface. • High resistivity and breakdown voltage. • Low bulk and interfacial trap densities. • Compatibility with the substrate and top electrode. • minimal interdiffusion and reaction • minimal silicon reoxidation during growth and device processing - even a thin SiO2 layer would deteriorate the Cgate significantly. • Thermal stresses — most oxides have larger thermal expansion coefficients than Si. • Good Si fabrication processing compatibility. • Stability at higher processing temperatures and environments • Ability to be cleaned, etched, etc. araswat tanford University 54 EE311 / Gate Dielectric Candidates for High K Gate Dielectrics Dielectric Permittivity Band Gap !EC to Si (eV) SiO2 3.9 9 3.5 Si3N4 7 5.3 2.4 Al2O3 9 8.8 2.8 TiO2 80 3.5 0 Ta2O5 26 4.4 0.3 Y2O3 15 6 2.3 La2O3 30 6 2.3 HfO2 25 6 1.5 ZrO2 25 5.8 1.4 ZrSiO4 15 6 1.5 HfSiO4 15 6 - Ref: Robertson, J., Appl. Surf. Sci. (2002) 190 (1-4), 2 • Higher K materials have lower bandgap • There are many performance, reliability and process integration issues yet to be solved • More research is needed to make these materials manufacturable araswat tanford University 55 EE311 / Gate Dielectric 7 Thermodynamic Stability of High-K Dielectric Oxides 100 Å K ≈ 20 75 Å K ≈ 20 10 Å Si3N4 • Unstable oxides (e.g. TiO2, Ta2O5, BST) – React with Si to form SiO2 and silicides upon thermal annealing – Barrier (e.g. Si3N4) is required to prevent such a reaction • Dielectric stack: poly-Si/nitride/unstable oxide/nitride/Si substrate • A monolayer of nitride on both sides of gate dielectric already contributes 5 Å to the physical oxide thickness • Stable oxides (e.g. HfO2, ZrO2, Al2O3) and their silicates (e.g. ZrSixOy) and aluminates (e.g. ZrAlxOy) – Do not react with Si upon thermal annealing (up to 1000°C) – May not require a barrier layer between Si and the metal oxide • simple structure: poly-Si/stable oxide/Si substrate araswat tanford University 56 EE311 / Gate Dielectric Stability of Metal Oxides with Si After Beyers,J. Appl. Phys. 56, 157, 1984 And Wang and Meyer J. Appl. Phys. 64, 4711 , 1988 araswat tanford University 57 EE311 / Gate Dielectric 8 Capacitance and Leakage for High-k Gate Dielectric Films Grown Using ALCVD V 0 Germanium 10 Silicon 1m ) ) 2 c 2 -2 m ±V/ 10 SiO m c 2 c / AB/ A A ( F( @( V e -4 2.5 nm 1 10 + g B F e a 2 ) k V g a e -6 ALCVD @ a t L 10 k n e e ZrO2 t r a r a -8 u e G 10 C L 4 nm e t a 10-10 G 0 0.05 0.1 0.15 0.2 1/C' (µm2/fF) ox Equivalent SiO2 Thickness (nm) Perkins, Saraswat and McIntyre, Chui, Kim, Saraswat and McIntyre, Stanford Univ. 2002 Stanford Univ. 2004 araswat tanford University 58 EE311 / Gate Dielectric Atomic Layer CVD of Hi-κ Dielectric Rotary Pump Pump Turbo Pump 4 4 MFC Loadlock ZrCl HfCl O 2 H Main Chamber Throttle Valve MFC MFC MFC Turbo Pump Scrubber Rotary Pump Carrier Gas (N2) araswat McIntyre, Saraswat, Stanford tanford University 59 EE311 / Gate Dielectric 9 Atomic Layer Deposition ZrCl4/HfCl4 (g) Substrate ON 1/4 cycle : Reactant A Injection of reactant A (ZrCl4/HfCl4) OFF (ZrCl4/HfCl4) Reactant B (H2O) 1 cycle araswat Time (sec) tanford University 60 EE311 / Gate Dielectric Atomic Layer Deposition * Zr " OH + ZrCl4 # Zr " O " ZrCl3 + HCl ! Saturated adsorption Substrate ON 2/4 cycle : Reactant A Purging (N ) (ZrCl /HfCl ) 2 4 4 OFF Reactant B (H2O) 1 cycle araswat Time (sec) tanford University 61 EE311 / Gate Dielectric 10 Atomic Layer Deposition HCl (g) H2O (g) Substrate ON 3/4 cycle : Reactant A Injection of reactant B (ZrCl4/HfCl4) OFF (H2O) Reactant B (H2O) 1 cycle araswat Time (sec) tanford University 62 EE311 / Gate Dielectric Atomic Layer Deposition * * Zr " Cl + H 2O # Zr " OH + HCl ! ZrO2/HfO2 (s) Substrate ON 4/4 cycle : Reactant A Purging (N ) (ZrCl /HfCl ) 2 4 4 OFF Reactant B (H2O) 1 cycle araswat Time (sec) tanford University 63 EE311 / Gate Dielectric 11 Atomic Layer Deposition ZrCl4/HfCl4 (g) Saturated adsorption Substrate Substrate HCl (g) H2O (g) ZrO2/HfO2 (s) Substrate Substrate - Surface saturation controlled process - Layer-by-layer deposition process - Excellent film quality and step coverage araswat tanford University 64 EE311 / Gate Dielectric Microstructure of ALD HfO2 and HfO2 ZrO =29Å 2 ZrO2=43Å ZrO2=82Å As-deposited ALD- ZrO2 is polycrystalline. ZrO2 Chemical oxide Si As-deposited ALD-HfO HfO2=28Å HfO2=45Å HfO2=62Å 2 is amorphous.