Integration of Metallic Source/Drain Contacts in MOSFET Technology

Home , Electrical contacts, Gate dielectric, Gate oxide, Leakage (electronics), Metal gate, Passivation (chemistry)

Doctoral Thesis By Jun Luo

Stockholm, Sweden 2010 Integrated Devices and Circuits,

School of Information and Communication Technology (ICT),

Royal Institute of Technology (KTH)

Integration of metallic source/drain contacts in MOSFET technology

A dissertation submitted to Kungliga Tekniska Högskolan (KTH), Stockholm, Sweden, in partial fulfillment of the requirements for the degree of Teknologie Doktor (Doctor of Philosophy)

TRITA-ICT/MAP AVH Report 2010:06 ISSN 1653-7610 ISRN KTH/ICT-MAP/AVH-2010:06-SE ISBN 978-91-7415-680-5 © Jun Luo, 2010

Cover SEM image: SB-FinFET (Courtesy Valur Gudmundsson)

Jun, Luo: Integration of metallic source/drain contacts in MOSFET technology, Integrated Devices and Circuits, School of Information and Communication Technology (ICT), Royal Institute of Technology (KTH), Stockholm, Sweden, 2010. TRITA-ICT/MAP AVH Report 2010:06, ISSN 1653-7610, ISRN KTH/ICT-MAP/AVH- 2010:06-SE, ISBN 978-91-7415-680-5

Abstract The continuous and aggressive downscaling of conventional CMOS devices has been driving the vast growth of ICs over the last few decades. As the CMOS downscaling approaches the fundamental limits, novel device architectures such as metallic source/drain Schottky barrier MOSFET (SB-MOSFET) and SB-FinFET are probably needed to further push the ultimate downscaling. The ultimate goal of this thesis is to integrate metallic Ni1-xPtx silicide (x=0∼1) source/drain into SB-MOSFET and SB-FinFET, with an emphasis on both material and processing issues related to the integration of Ni1-xPtx silicides towards competitive devices. First, the effects of both carbon (C) and nitrogen (N) on the formation and on the Schottky barrier height (SBH) of NiSi are studied. The presence of both C and N is found to improve the poor thermal stability of NiSi significantly. The present work also explores dopant segregation (DS) using B and As for the NiSi/Si contact system. The effects of C and N implantation into the Si substrate prior to the NiSi formation are examined, and it is found that the presence of C yields positive effects in helping reduce the effective SBH to 0.1-0.2 eV for both conduction polarities. In order to unveil the mechanism of SBH tuning by DS, the variation of specific contact resistivity between silicide and Si substrates by DS is monitored. The formation of a thin interfacial dipole layer at silicide/Si interface is confirmed to be the reason of SBH modification. Second, a systematic experimental study is performed for Ni1-xPtx silicide (x=0∼1) films aiming at the integration into SB-MOSFET. A distinct behavior is found for the formation of Ni silicide films. Epitaxially aligned NiSi2-y films readily grow and exhibit extraordinary o morphological stability up to 800 C when the thickness of deposited Ni (tNi) <4 nm. Polycrystalline NiSi films form and tend to agglomerate at lower temperatures for thinner films for tNi≥4 nm. Such a distinct annealing behavior is absent for the formation of Pt silicide films with all thicknesses of deposited Pt. The addition of Pt into Ni supports the above observations. Surface energy is discussed as the cause responsible for the distinct behavior in phase formation and morphological stability. Finally, three different Ni-SALICIDE schemes towards a controllable NiSi-based metallic source/drain process without severe lateral encroachment of NiSi are carried out. All of them are found to be effective in controlling the lateral encroachment. Combined with DS technology, both n- and p-types of NiSi source/drain SB-MOSFETs with excellent performance are fabricated successfully. By using the reproducible sidewall transfer lithography (STL) technology developed at KTH, PtSi source/drain SB-FinFET is also realized in this thesis. With As DS, the characteristics of PtSi source/drain SB-FinFET are transformed from p-type to n-type. This thesis work places Ni1-xPtx (x=0∼1) silicides SB- MOSFETs as a competitive candidate for future CMOS technology.

Key words: CMOS technology, MOSFET, Schottky barrier MOSFET, metallic source/drain, contact resistivity, NiSi, PtSi, Ni1-xPtxSi, SALICIDE, SOI, nanowire device, ultrathin silicide

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Table of Contents

List of Papers………………………………………………………………………………..vi Summary of Appended Papers……………….……………………………………………..vii Acknowledgements………………………………………………………………………….viii Symbols & Acronyms………………………………………………………………………..x 1. Introduction……………………………………………………………………………….1 References………………………………………………………………………………...5 2. Device Physics, Downscaling and Novel Device Architectures…………………………...7 2.1 Fundamentals of MOSFETs…………………………………………………………….7 2.1.1 MOSFET structure……………………………………………………………...7 2.1.2 I-V characteristics…………………………………………………………………8 2.2 MOSFET downscaling……………………………………………………………….10 2.2.1 Short channel effects and scaling rules………………………………………...10 2.2.2 Scaling issues…………………………………………………………………...12 2.3 Introduction of novel device architectures…………………………………………...13 2.4 Operation principles of SB-MOSFETs……………………………………………….15 2.4.1 SB-MOSFETs structure…………………………………………………………15 2.4.2 Operation principles……………………………………………………………..16 2.4.3 DIBL-like effect of SB-MOSFETs……………………………………………...20 2.4.4 SCEs of SB-MOSFETs………………………………………………………….21 References...……………………………………………………………………………….23 3. Implementation of Ni1-xPtx (x=0∼1) Silicides……………………………………………..27 3.1 SALICIDE process and choice of silicides for SB-MOSFETs……………………….27 3.1.1 SALICIDE process……………………………………………………………...27 3.1.2 Choice of silicides for SB-MOSFETs…………………………………………..30 3.2 Properties of Ni1-xPtx silicide (x=0)……………………………………………….....33 3.2.1 Effects of C and N on the formation of Ni1-xPtx silicide (x=0)……….………...33 3.2.2 Effects of C and N on SBH of Ni1-xPtx silicide (x=0) by DS…………………..35 3.3 Mechanism of SBH tuning by DS…………………………………………………….38 3.4 Ultrathin Ni1-xPtx silicides (x=0∼1)…………………………………………………...43 References……………………………………………………………………………….48 4. SB-MOSFETs: Fabrication and characterization………………………………………….53 4.1 Key issues related to integration and solutions……………………………………...53 4.1.1 Methods for nanowire fabrication……………………………………………...53 4.1.2 Severe lateral encroachment of NiSi…………………………………………...56 4.1.3 SBH modification of NiSi……………………………………………………...61 4.2 NiSi integration with Si technology………………………………………………….61 4.2.1 Ion implantation damage and recovery………………………………………...62 4.2.2 Etching of NiSi…………………………………………………………………63 4.2.3 SiNx-SiO2 double layer…………………………………………………...…….65 4.3 SB-MOSFETs on UTB-SOI…………………………………………………………66 4.4 SB-FinFETs fabrication……………………………………………………………….71 References………………………………………………………………………………..73 5. Summary, Conclusions and Future Perspective………………………………………….77

Appended Papers

I. Effect of carbon on Schottky barrier heights of NiSi modified by dopant segregation J. Luo, Z.-J. Qiu, D. W. Zhang, P. E. Hellström, M. Östling and S.-L. Zhang IEEE Electron Device Lett., vol. 30, no.6, pp. 608-610, Jun. 2009.

II. Interaction of NiSi with dopants for metallic source/drain applications J. Luo, Z.-J. Qiu, M. Östling and S.-L. Zhang J. Vac. Sci. Technol. B, vol. 28, no. 1, pp. C1I1-C1I11, Jan. 2010.

III. Surface-energy triggered phase formation and epitaxy in nanometer-thick Ni1-xPtx silicide films J. Luo, Z.-J. Qiu, C. L. Zha, Z. Zhang, D. P. Wu, J. Lu, J. Åkerman, M. Östling, L. Hultman, and S.-L. Zhang Appl. Phys. Lett., vol. 96, no. 3, pp. 031911-1-031911-3, Jan. 2010.

IV. Kinetics and morphology of Ni1-xPtx-silicide epitaxy on Si(001) J. Lu, J. Luo, S.-L. Zhang, M. Östling, and L. Hultman Submitted to Electrochemical and Solid-State Letters, May. 2010.

V. On different process schemes for a controllable NiSi-based metallic source/drain MOSFETs with dopant segregation J. Luo, D. P. Wu, Z. J. Qiu, J. Lu, L. Hultman, M. Östling and S.-L. Zhang Submitted to IEEE Trans. Electron Devices, Mar. 2010.

VI. Fully depleted UTB and trigate N-channel MOSFETs featuring low-temperature PtSi Schottky-barrier contacts with dopant segregation V. Gudmundsson, P.-E. Hellström, J. Luo, J. Lu, S.-L. Zhang, and M. Östling IEEE Electron Device Lett., vol. 30, no.5, pp. 541-543, May. 2009.

VII. Nanoscaling of MOSFETs and Implementation of Schottky barrier S/D contacts M. Östling, J. Luo, V. Gudmundsson, P.-E. Hellström and B. G. Malm Proceedings of 27th international conference on microelectronics, Niś, Serbia, pp. 9-13, May 16-19, 2010.

Summary of the Appended Papers

Paper I. This paper investigates the effects of carbon on Schottky barrier heights (SBHs) of NiSi modified by dopant segregation. The presence of C at the interface between NiSi and Si is found to participate in the process of modification of effective SBHs using dopant segregation (DS). The author of this thesis has performed 100% of the device fabrication, 100% of the measurement, 90% of the data analysis, and 80% of the manuscript writing. Paper II. This work is an extension of Paper I. The present work explores DS using B and As for the NiSi/Si contact system in order to tune the effective SBHs. The effects of C and N implantation into Si substrate prior to the NiSi formation are examined thoroughly. An effective SBH of 0.1-0.2 eV for both conduction polarities has been realized. The author has performed 100% of the device fabrication, 100% of the measurement, 90% of the data analysis and 40% of the manuscript writing.

Paper III. This paper systematically explores the formation of ultrathin silicide films of o Ni1-xPtx (x=0, 0.04, 0.08, 0.14, and 1) at 450-850 C. Ultrathin epitaxially aligned NiSi2-y (y<1) films exhibit extraordinary morphological stability up to 800 oC. The role of surface energy is discussed as the root cause for the distinct behavior in phase formation and morphological stability. The author has performed 100% of the device fabrication, 100% of the measurement, 90% of the data analysis, and 70% of the manuscript writing.

Paper IV. To some extent, this manuscript is the extension of Paper III. Instead of the thermodynamics investigation on the epitaxial formation of Ni1-xPtx-silicide on Si(001), this work focuses on the kinetics and detailed morphology of Ni1-xPtx-silicide epitaxy on Si(001). o Upon annealing pre-deposited 2-nm thick Ni or Ni0.96Pt0.04 films on Si(001) at 500 C, the grown Ni(Pt)Si2-y (y<1) films, 5.4-5.6 nm thick and 61-70 µΩ-cm in resistivity, are found to o be expitaxially aligned. At 750 C, the epitaxial Ni(Pt)Si2-y films become 6.1-6.2 nm thick with a resistivity of 42-44 µΩ-cm. The author has performed 100% of the device fabrication, 100% of the measurement, and 50% of the data analysis.

Paper V. This work focuses on different SALICIDE schemes towards a controllable NiSi- based metallic source/drain (MSD) process without severe lateral encroachment of NiSi. These schemes include thickness control of Ni, Ni-Pt alloying, and two-step annealing. The experimental results show that all the three process schemes can give rise to an effective control of the lateral encroachment during Ni-silicidation. The author has performed 100% of the device fabrication, 100% of the measurement, 90% of the data analysis and 90% manuscript writing.

Paper VI. This paper studies the fully depleted ultrathin body (UTB) and N-channel SB- FinFETs featuring low-temperature PtSi Schottky-barrier contacts with dopant segregation. The author has taken part in the device fabrication.

Paper VII. This paper provides an overview of metallic source/drain (MSD) Schottky- barrier (SB) MOSFET technology. A preliminary guideline for designing a high-performance MSD SB-MOSFET is discussed and provided. The author has performed 50% of the device fabrication, 50% of the data analysis, and 80% of the manuscript writing.

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Acknowledgements This thesis summarizes the research work I have conducted as a PhD candidate at the Royal Institute of Technology (KTH). During this period, I have received numerous help and encourage from many people. First of all, I would like to thank Prof. Mikael Östling, my principle supervisor, for accepting me as a PhD student at KTH. You have always given me the utmost support, encouragement and guidance on the research work. Also, I would like to thank you for creating a very friendly and exciting environment to do research in. Furthermore, the communication skills I benefit from you are for sure helpful in my life. I would also like to express my gratitude to my practical supervisor, Prof. Shi-Li Zhang, for the supervision starting from Sept. 2007. I have to say, without your insightful guidance, I can hardly finish this thesis within such a short time. I have not only benefited from your broad knowledge and deep insight in the silicide field, but also, most importantly, learnt the strict, careful and aspiring attitude towards the science and research. I would also thank my supervisor at Fudan University, Prof. David Zhang, for his help in taking care of issues regarding my study at Fudan and also for the encouragement. Many thanks go to other members of the Si technology group, Docent Per-Erik Hellström, Dr. Julius Hållstedt, Valur Gudmundsson, Dr. Zhen Zhang, Zhijun Qiu for your help, fruitful discussion and collaboration. A big gratitude goes to Dr. Jun Lv for his wonderful TEM analysis, to Anders Hallén for his help of ion implantation, to Margareta Linnarsson for the SIMS analysis, and to Majid Mohseni, Johan Persson and Sohrab Redjai Sani for the metal sputtering. I am deeply grateful to Dr. Zhibin Zhang, Dr. Yong-Bin Wang, and Dr. Caolin Zha for your constant help and good suggestions in both my research and my everyday life in Stockholm. I would also like to thank Prof. Carl-Mikael Zetterling, Docent Henry Radamson, and Dr. Gunnar Malm for your insightful discussion and valuable help. I am very grateful to my officemate, Buono Benedetto, for sharing and enjoying the happy time during the past 3 years. A special thank is given to Christian Ridder, Kristina Bellander, Klara Ridder and Cornelia Ridder for your invitation and hospitality when I visited your family. I really enjoyed the time with you. I am also very grateful to all the colleagues at EKT and at KTH for their help, support and discussions: Timo Söderqvist, Dr. Martin Domeij, Dr. Hyung Seok Lee, Jiantong Li, Mohammadreza Kolahdouz Esfahani, Reza Ghandi, Muhammad Usman, Dr. Yohannes Assefaw-Redda, Gina Lanni, Maziar Amir Manouchehry Naiini, and Ming Hung Weng. Thanks are also given to all my friends in Sweden: Christina Besmer, Jian Chen, Jiajia Chen, Si Chen, Yeyu Fang, Mi Liang, Shuai Li, Zhiying Liu, Ying Ma, Jian Qin, Botao Shao, Huimin She, Yaocheng Shi, Qie Sun, Sha Tao, Jie Tian, Peng Wang, Xiaodi Wang, Yan Wu, Chunsheng Yan, Geng Yang, Shun Yu, Xingang Yu, Xiang Yu, Zhangwei Yu, Dongying Zhan, Qian Zhan, Ning Zhu….Life would be quite boring without you. I would also thank my badminton friends, Shanghua Li (Peter), Han-Hsuan Lin, Abhilash Sugunan, and Mohsin Saleemi for the fun time. The staff at the Electrum cleanroom-lab is also acknowledged for their valuable work in keeping the lab running smoothly. viii

Many thanks go to Gunilla Gabrielsson and Zandra Lundberg for all the help and excellent administrative work. Finally, I sincerely wish to thank all members of my family and loved ones, for providing all sorts of supporting and encouragement. Especially, to my parents, Yuliang Luo and Taoxiu Wang, for always believing in me and supporting me to discover my own life path. Most importantly, I want to express my deep love and gratitude to my girl friend, Yan Wu, for the patient waiting and supporting me during all these years. Words cannot fully express my gratitude. This thesis is dedicated to you. Thank you all!

Jun Luo Stockholm 2010-5-18

Symbols and Acronyms A The area of a Schottky contact A* The Richardson constant

Cdm Maximum depletion-layer capacitance per unit area

Cox Gate oxide capacitance per unit area

Eeff Effective electric field

Eg Band gap energy

Ids Drain current

Ioff Off current

Ion On current

Idssat Drain current in saturation

Ife Field emission current

Ith Thermionic emission current k Boltzmann’s constant (1.38×10-23 J/K)

Lg Gate length m MOSFET body-effect coefficient m* Effective mass of carriers

ni Intrinsic carrier concentration

NA Acceptor doping concentration Q Electronic charge (1.602×10-19 C) T Absolute temperature

tox Gate oxide thickness

Vds Drain voltage

Vg Gate voltage

Vdsat Drain voltage in saturation

Vt Threshold voltage

Wdm Maximum depletion layer width

Wg Gate width -12 εSi Silicon permittivity (1.04×10 F/cm)

ψB Difference between Fermi level and intrinsic level

φbp Schottky barrier height to holes

φbn Schottky barrier height to electrons

φb Schottky barrier height

ρc Specific contact resistivity τ Circuit delay time

μeff Effective mobility BOX Buried oxide CBKR Cross-bridge Kelvin resistors CMOS Complementary metal-oxide-semiconductor x

CSE Charge sharing effect DIBL Drain induced barrier lowering DIBT Drain induced barrier thinning DS Dopant segregation EDS Energy dispersive X-ray spectroscopy EBL Electron beam lithography FGA Forming gas annealing HR-SEM High resolution scanning electron microscope HR-TEM High resolution transmission electron microscope IC Integrated circuits I/I Ion implantation IDP In situ doped polysilicon LOCOS Local oxidation of Silicon MOSFET Metal-oxide-semiconductor field effect transistor MSD Metallic source and drain PECVD Plasma-enhanced chemical vapor deposition RTP Rapid thermal processing SADS Silicide as diffusion source SAED Selective area electron diffraction SALICIDE Self-aligned silicide SB Schotty Barrier SBH Schottky barrier height SB-MOSFET Schottky-Barrier Source/Drain MOSFET SCE Short channel effect S/D Source/Drain SEM Scanning electron microscope SIDS Silicidation induced dopant segregation SIMS Secondary ion mass spectrum SS Substhreshold slope STI Shallow trench isolation STL Sidewall transfer lithography TEM Transmission Electron Microscopy UTB-SOI Ultrathin body silicon-on-insulator

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Chapter 1. Introduction

Metal-oxide-semiconductor field-effect-transistor (MOSFET), since its demonstration in 1959, has been dominating in integrated circuits (ICs) for a few decades as the fundamental component of nearly all modern electronic products. As microelectronics industry’s never- ending pursuit for low cost and high performance, the continuous downscaling of MOSFETs has always been the main driving force in IC industry. The smaller the MOSFETs dimensions, in particular the distance between source and drain (S/D), the higher performance and packing density and the lower cost per MOSFET. This scaling phenomenon has been closely following the famous Moore’s law, according to which the number of transistors placed inexpensively on an IC is doubled approximately every two years [1]. A good example of downscaling trend predicted by Moore’s law is shown in Fig. 1.1 [2], the number of MOS transistors integrated into the different generations of Intel’s microprocessors indeed doubled about every two years. Moreover, each time the feature size of MOS transistors shrinks, the cost performance ratio is improved for the new generation microprocessors. For example, the price of one MOS transistor was 1 US dollar in 1968 and it is reduced to incredibly less than 1/10,000 of a cent nowadays [3]. The latest Intel’s microprocessor, integrated with more than 1 billion MOS transistors using the state-of-the-art 32 nm technology, can be operated at the astonishing 3.2 GHz or higher clock frequency.

Fig. 1.1. The feature size and number of MOS transistors integrated in Intel’s microprocessors vs. production year [2].

Integration of metallic source/drain contacts in MOSFET technology

It should be mentioned that the downscaling of conventional planar bulk MOSFETs did not meet harsh challenges in the past decades when the feature size of MOSFETs, i.e., gate length (Lg), was relatively large, i.e., ≥ 100 nm. The sustaining development of new processing tools, like lithography and anisotropic dry-etching equipment, could always satisfy the downscaling. However, as the MOSFETs technology enters into sub-100 nm era, ICs industry has to struggle with the higher and higher costs, as a result of the investment in advanced processing equipment required for the downscaling. Apart from the huge costs, there are some specific issues impeding the downscaling of the conventional planar bulk MOSFETs. First, due to the non-scalable permittivity of the gate oxide, the gate control over the channel is becoming weaker and weaker which demands the introduction of high-k materials. Second, short channel effects (SCEs), typically characterized by the subthreshold slope (SS), are inherently non-scalable. Third, as a result of the ever-decreasing S/D junction depths and the limitation of dopants solubility, the S/D parasitic resistance becomes intolerable in bulk MOSFETs as shown in Table I [4]. Taking all these challenges into account, therefore, it is becoming more and more difficult for conventional planar bulk MOSFETs to achieve the performance gain by simply downscaling the geometrical dimensions. In order to combat with these challenges, some solutions have been proposed. Among them, metallic S/D Schottky barrier MOSFET (SB-MOSFET) and SB-FinFET were proposed to allow the continued scaling of MOSFETs without degrading the performance, which also motivate this thesis work.

The focuses of this thesis are on both the material and processing integration issues of novel metallic S/D SB-MOSFETs. By using a metallic S/D and a SB-FinFET structure, the goal of controlling the short channel effects and reducing the parasitic series S/D resistance of MOSFET are achieved in this thesis. According to the finds in this thesis, metallic S/D SB- MOSFET presents a very promising devices architecture for future generations of CMOS technology.

In Chapter 2, the fundamentals of conventional planar bulk MOSFETs will be reviewed. Then the migration of MOSFETs structures from planar to FinFets [5] or trigate-MOSFETs [6] or gate-all-around (GAA) FETs [7] will be presented. The operation principles of SB- MOSFET will be discussed in the last part of this chapter.

Chapter 3 mainly involves the investigation on material aspect of Ni1-xPtx silicides (x=0∼1).

The necessities of the choice of the Ni1-xPtx silicides system is presented first. It is followed

Chapter 1. Introduction

by the study of the effects of carbon (C) and nitrogen (N) on the formation, morphological stability, and Schottky barrier height (SBH) modification by dopant segregation (DS) of NiSi, with reference to the results in Papers I and II. In order to figure out the mechanism of SBH tuning by DS, a systematic study of the variation of specific contact resistivity (ρc) of the PtSi/silicon interface induced by DS was carried out. The formation of interfacial dipole has been confirmed as the cause responsible for the modification of SBH. In addition, considering the scalability in the perspective extremely thin SOI devices, the systematic study of ultrathin Ni1-xPtx (x=0∼1) silicide films is also conducted, which is detailed in Paper III and IV.

Table I. ITRS predictions on maximum contact resistivity and S/D extension sheet resistance for bulk [4].

Year of production 2009 2010 2011 2012 2013 2014 2015

Technology node 47 41 35 31 28 25 22 (nm)

Physical gate 29 27 24 22 20 18 17 length (nm)

Contact maximum resistivity for bulk 1.6×10-7 1.38×10-7 8.0×10-8 4.0×10-8 2.0×10-8 1.0×10-8 8.0×10-9 (Ω⋅cm2)

Maximum S/D extension sheet 650 670 660 680 750 810 900 resistance (Ω/sq)

Since the material investigation on Ni1-xPtx silicides (x=0∼1) in Chapter 3 paves the way for their integration into SB-MOSFETs, Chapter 4 will be engaged in the study of devices, i.e.,

SB-MOSFETs and SB-FinFETs. Key issues facing the integration of Ni1-xPtx silicides (x=0∼1) into SB-MOSFETs will be summarized, and the approaches to solving the severe lateral encroachment of NiSi towards the channel will follow with reference to Paper V and VII. In

Integration of metallic source/drain contacts in MOSFET technology

addition, the compatibility of NiSi integration issues in SB-MOSFETs with standard Si processing is also addressed in Chapter 4. This chapter concludes with the fabrication and characterization of PtSi S/D SB-FinFETs with DS. The discussion on SB-FinFETs is facilitated by referring to the results in Paper VI and VII.

In Chapter 5, a summary along with future perspective concludes this thesis.

Chapter 1. Introduction

References

1. G. Moore, “Cramming more components onto integrated circuits,” Electronics 38(8), pp. 11-13, 1965. 2. http://www.intel.com/technology/mooreslaw/index.htm. 3. R. Hiremane, “From Moore’s law to Intel innovation-prediction to reality,” Technology@Intel magazine, pp. 1-9, 2005. 4. International Technology Roadmap for Semiconductors (ITRS), http://public.itrs.net/links/2009ITRS/Home2009.htm 5. X. J. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Cang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, C. Hu, “Sub-50 nm FinFET: PMOS,” IEDM Tech. Dig., pp. 67-70, 1999. 6. B. S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, R. Chau, “High performance fully-depleted tri-gate CMOS transistors,” IEEE Electron Device Lett., vol. 24, no. 4, pp. 263-265, Apr. 2003. 7. N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R. Kumar, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong, “High-performance fully depleted silicon nanowire (diameter≤ 5 nm) gate-all-around CMOS devices,” IEEE Electron device lett., vol. 27, no. 5, pp. 383-386.

Integration of metallic source/drain contacts in MOSFET technology

Chapter 2. Device Physics, Downscaling and Novel Device Architectures

Chapter 2. Devices Physics, Downscaling and Novel Device Architectures

The metal–oxide–semiconductor field-effect transistor (MOSFET) is a device used for switching electronic signals. The basic principle of MOSFET was first proposed by Julius Edgar Lilienfeld in 1925. Since its realization in 1959 [1], MOSFETs has been playing an indispensable role in microelectronics industry. Unique characteristics of MOSFETs, such as extremely high layout density, low standby power dissipation and great ease of process control compared to bipolar counterparts, make MOSFETs the prevailing device in ICs industry. Moreover, the revolutionary invention of complementary MOSFET (CMOS) technology in 1963 [2], a milestone in the history of ICs industry, formed the basis of the vast majority of all high density ICs like memories and microprocessors manufactured today. The downscaling of MOSFETs stimulates the vast growth of ICs for the last four decades. In this chapter, the operation principles of MOSFETs will be first presented, followed by the discussion of MOSFETs downscaling. Since this thesis focuses on the fabrication and characterization of SB-MOSFETS, this chapter will be concluded by the discussion of the operation fundamentals of this unique class of MOSFETs.

2.1 Fundamentals of MOSFETs

2.1.1 MOSFET structure

A long-channel n-type bulk MOSFET (n-MOSFET) fabricated at KTH is shown in Fig. 2.1. As seen, a MOSFET is a four-terminal device with the terminals designated as gate (G), source (S), drain (D), and substrate or body (B). For n-MOSFET, the substrate is usually lightly p-type and S/D regions are normally highly doped with n-type dopants (e.g., As, P) which offer low resistance and contact resistivity. Highly doped polycrystalline Si (poly-Si) is usually used as the gate electrode in an n-MOSFET which is insulated by a thin layer of gate oxide (SiO2) from the substrate. Usually, the SiO2 is formed by thermal oxidation of silicon acting as the energy barrier between gate electrode and the substrate. The surface

region under SiO2 between the source and drain is called channel region, the place for current conducting.

Integration of metallic source/drain contacts in MOSFET technology

SiO2 Gate

Channel Source Drain Body

Fig. 2.1. A typical long channel MOSFET fabricated at KTH.

2.1.2 I-V characteristics

Typical transfer and output characteristics of a long-channel n-MOSFET are shown in Fig. 2.2 (a) and (b), respectively. The equations to describe the I-V characteristics are shown as follows [3], [4].

Fig. 2.2. (a) Transfer and (b) output characteristics for an n-type MOSFET.

When Vg is immediately below the threshold voltage (Vt), a small electron diffusion current does not drop immediately to zero as Vg approaches zero. The n-MOSFET is thus operated in the “subthreshold region”. Subthreshold behavior is of particular importance in low-voltage, low-power devices since it describes how MOSFETs are switched off.

Chapter 2. Device Physics, Downscaling and Novel Device Architectures

The subthreshold current is:

qV()− V W gt −qVds g kT 2 mkT kT ICmds=−μ eff ox (1)() e (1) − e (2.1) Lqg

where m is usually called body effect coefficient and it is typically 1∼1.4 which is defined as:

εψqN /4 Ct3 m =+111Si A B ≈+dm =+ ox (2.2) CCWox ox dm

here Cdm is the maximum depletion-layer capacitance and Wdm is the depletion width.

The last term in (2.1) can be omitted when Vds is greater than a few kT/q. Ids is thus

independent of Vds,

W qV()g − Vt g kT 2 mkT ICmds=−μ eff ox (1)() e (2.3) Lqg

The off-current (Ioff), a component of the leakage current, usually represents Ids when Vg=0.

From (2.3), it can be easily concluded that Ioff will increase by about 10 times for every 100 mV reduction of Vt. As the MOSFET is downscaled, the roll-off of Vt enhances the undesired

increase of Ioff.

An important parameter of MOSFETs, subthreshold slope (SS), is defined as the following:

−1 ⎡⎤∂ ()log I mkT kT Ct3 SS =⎢⎥ds ≈=+=+2.3 2.3 (1dm ) 2.3(1 ox ) (2.4) ⎣⎦⎢⎥∂VqqCWg ox dm

A steep subthreshold slope or a small SS value is desired for “well-behaved” MOSFETs. As

seen in (2.4), a small SS value can be realized with thin tox and large Wdm.

When Vg > Vt, the channel region is inverted from p-type to n-type with a high density of electrons. As a result, a conducting path for electrons is formed between the source and drain.

If a positive Vds is applied at the drain end relative to the source, electrons will flow from source to drain thus forming an electrons current. The n-MOSFET is then operated at “on- state”.

Integration of metallic source/drain contacts in MOSFET technology

When Vds is small, the n-MOSFET is operated in linear (triode) region,

Wg Ids=−μ effCVVV ox() g t ds (2.5) Lg

When Vds continues to increase, Ids first enters the parabolic region and then saturates at Vds= Vdsat= (Vg-Vt)/m,

2 WVgg()− V t IIds== dssatμ eff C ox (2.6) Lmg

2.2 MOSFET downscaling

2.2.1 Short channel effects and scaling rules

Scaling down MOSFET dimension is a continuous trend since its inception. Smaller device size enables higher device density in an integrated circuit. A typical downscaled short- channel MOSFET of Lg= 45 nm fabricated at KTH is shown in Fig. 2.3. However, the downscaling has been constantly challenging by short channel effects (SCEs) which are usually characterized by the roll-off of Vt with shrinking Lg. The physical origin of SCEs is the charge sharing effect (CSE) and drain-induced barrier lowering (DIBL). A schematic presentation of these two factors contributing to the roll-off of Vt is demonstrated in Fig. 2.4.

An undesired consequence due to Vt roll-off is the substantial increase of subthreshold current together with deteriorative SS.

Fig. 2.3. A typical short channel MOSFET of Lg=45 nm fabricated at KTH.

Chapter 2. Device Physics, Downscaling and Novel Device Architectures

Fig. 2.4. Schematic presentation of the contribution to Vt roll-off for short-channel

MOSFETs [5].

In order to control the SCEs for scaled devices, scaling rules were therefore proposed. The classic scaling rule, known as “constant-field scaling”, was proposed by Dennard et al. in 1974 [6]. The essence of constant-field scaling is to scale the supply voltage and device dimensions (both horizontal and vertical) by the same factor k>1, so the electric field remains constant. As a result, the circuit speed is improved by a factor of k, and the power dissipation per circuit is reduced by a factor of k2. Although “constant-field scaling” rule works, the stringent demand on the reduction of supply voltage effaces its practical application since the non-scalability of Vt and ICs industry is reluctant to deviate from the standardized voltage levels of the previous technology generations. Hence, a more general scaling rule, proposed by Baccarani et al. in 1984 [7], has been proposed and followed. The essence of general scaling rule is to keep the shape of electric field pattern unaltered by multiplying the horizontal and vertical electric field by the same factor, α>1. Thus the 2-D effects, such as SCEs, do not worsen with device downscaling.

Integration of metallic source/drain contacts in MOSFET technology

2.2.2 Scaling issues

Several challenges that should be considered in MOSFET design are summarized as follows:

1. μeff: μeff, of course, should be as large as possible. Basically, μeff is inversely proportional to * the vertical electric field (Eeff), the effective mass of carriers (m ) and the doping level in the channel. With the downscaling, the vertical electric field increases which results in degraded

μeff. Strain engineering (compressive for holes and tensile for electrons) has been performed to improve μeff [8,9]. Replacement of the channel Si with high mobility materials such as Ge presents another possibility [10]. The doping level in the channel is required to be kept low thus improves μeff.

2. tox and Cox: tox has been scaled down to ∼1.5 nm and Cox is increased accordingly. As a result, the device performance is improved. However, a very thin SiO2 results in catastrophic gate leakage [11, 12] which is unacceptable for the reliability consideration of devices. High dielectric permittivity (high-k) gate materials are therefore introduced in order to alleviate the stringent downscaling of tox [13, 14].

3. NA and Vt: Vt is in principle non-scalable parameter because of the non-scalability of the thermal voltage kT/q. In order to control SCEs and set Vt properly, NA (mostly in the HALO or pocket region) should be increased. This increase, however, leads to two consequences.

One is the degraded μeff due to increased scattering. Another one is the significant dopant variation in the channel of small devices, which results in significant fluctuation of Vt [15].

4. ni and ψB: Band gap Eg of Si is non-scalable, so that ni is a non-scalable constant.

Therefore, the built-in potential, ψB, is also non-scalable. So do the depletion width and SCEs [4].

5. SCEs: SCEs are one of the most important concerns with downscaling. Knowing the physics of SCEs, the key to controlling SCEs is to weaken the drain electric field penetration and regain the control of gate over channel. The replacement of oxide with high-k gate dielectrics [13, 14] retrieves the power of gate over channel. Other options to control SCEs need the introduction of novel device architecture as discussed below.

Chapter 2. Device Physics, Downscaling and Novel Device Architectures

2.3 Introduction of novel device architectures

Advanced device structures, i.e., multi-gate MOSFETs such as FinFETs [16] in Fig. 2.5, Ω- FETs [17] and gate-all-around FETs [18], have also been employed to effectively control SCEs. The multi-gate MOSFETs have been studied extensively as the ultimate solution for extremely scaled devices. Instead of controlling the channel over one surface for planar devices, multi-gate devices control the channel from many surfaces, leading to greatly improved SCEs and device performance.

Gate nanowire

Drain “Fin” Source

Fig. 2.5. (a) Schematic drawing of a FinFET structure and (b) a top-view scanning electron

microscopy (SEM) image of FinFET fabricated at KTH.

Making devices on UTB-SOI substrates also presents a way to control SCEs [19, 20]. Another advantage adopting UTB-SOI substrates is the reduced extrinsic capacitance. With downscaling of MOSFETs, the intrinsic capacitance decreases; however, the non-scalable extrinsic capacitances are becoming more and more comparable to their intrinsic counterparts, which offsets the desired performance enhancement. With UTB-SOI substrates, the extrinsic parasitic capacitance is eliminated due to the excellent isolation from the bulk silicon, improving power consumption at matched performance. The circuit delay time, τ∼CV/I, is thus reduced, resulting in the improved switching speed for CMOS in digital circuits.

However, numerous challenges are expected with the integration of UTB-SOI MOSFETs for the desired high performance. Considering ordinary UTB-SOI MOSFETs with highly doped S/D, one of the most challenging problems is the parasitic series S/D resistance due to the

Integration of metallic source/drain contacts in MOSFET technology

ever-reducing top Si layer. How to reduce the parasitic resistance to a tolerable level is one of the pressing concerns. Normally, highly doping along with partial silicidation of the S/D presents one solution to reducing the otherwise huge parasitic series resistance. Combining with elevated S/D, the electric connection between the channel and S/D can be further improved [21, 22]. However, how to electrically activate the degenerately doped S/D to form a sharp p-n junction to the channel is challenging. Apart from the sharp p-n junction, the high doping level in order to achieve a low contact resistance is also important. High temperature is thus necessary for dopant activation, which unfortunately rules out the possibility to adopt high-k, metal gate and strained channel with the usual gate-first processing sequence.

Fig. 2.6. Schematic cross-section of a metallic S/D SB-MOSFET.

An attractive alternative is to use metallic S/D contacts [23, 24] to circumvent the high series resistance problem with conventional UTB-SOI MOSFETs. With this technology, the highly doped S/D regions are replaced with metallic S/D as shown in Fig. 2.6. Metal silicides are of particularly interest for the metallic S/D materials due to the established self-aligned silicidation process and the low resistivity. This metallic silicide S/D architecture provides an elegant solution to the high series resistance problem, since the contacts between connecting

Chapter 2. Device Physics, Downscaling and Novel Device Architectures

metal and metallic silicides provide very low contact resistivity (usually on the order of 10-8 Ω⋅cm2) and the silicide provides low sheet resistance. In addition, low thermal budget of metal silicide S/D also facilitates the integration of high-k, metal gate and strained channel.

In view of the process complexity and process capability in Electrum clean room lab, as well as the traditional background in silicides at KTH, metallic silicides (PtSi and NiSi) S/D SB- MOSFETs and SB-FinFETs are studied in this thesis, with a purpose of controlling SCEs and addressing the parasitic series source/drain resistance.

Since the phenomenon of carriers transport in SB-MOSFETs is so important, it is necessary to understand the operation principles of SB-MOSFETs. The forthcoming section will deal with it.

2.4 Operation principles of SB-MOSFETs

2.4.1 SB-MOSFETs structure

NiSi Poly-Si NiSi

Si-channel BOX

Fig. 2.7. Cross-sectional TEM micrograph of a NiSi S/D SB-MOSFET of L = 0.3 μm. g

Integration of metallic source/drain contacts in MOSFET technology

A cross-sectional TEM micrograph of a NiSi S/D SB-MOSFET fabricated on UTB-SOI is shown in Fig. 2.7. The major innovation of this device architecture is to replace the highly doped S/D with a metal typically silicide, i.e., NiSi or PtSi in this thesis. This silicide S/D structure provides a promising solution to the parasitic resistance challenge of extremely scaled bulk MOSFETs because of a low specific resistivity and low contact resistivity of silicides. This different nature of the contacts between S/D and the channel leads to fundamentally different operation principles for SB-MOSFETs as compared to conventional MOSFETs. For a conventional MOSFET, the current is limited by the channel conductance. While for a SB-MOSFET, the carrier injection through the Schottky barrier (SB) at the source is the current-limiting factor. For a high-performance SB-MOSFET, the low Schottky barrier height (SBH) as low as 0.1 eV is needed in order to outperform conventional

MOSFETs [25, 26]. Among most silicides, PtSi and rare-earth silicide such as ErSix and

YbSix have the lowest known SBHs to holes (0.15-0.27 eV) and electrons (0.27-0.36 eV), respectively. PtSi has therefore been used for p-type SB-MOSFETs [27], while ErSix [27] or

YbSix [28] for n-type SB-MOSFET. For NiSi in this thesis, due to Fermi-level pinning, the SBHs to both electrons and holes are large, i.e., 0.65 and 0.45 eV respectively. Therefore, the SBH engineering to tune the large SBHs of NiSi to low values becomes essential for the fabrication of high-performance NiSi S/D SB-MOSFETs. A promising and reproducible approach to engineer the SBH of NiSi is dopant segregation (DS) technique [29-31]. Regarding the details of the SBH modification by DS, it will be discussed in Chapter 3.

2.4.2 Operation principles

The basic operation principles of NiSi S/D SB-MOSFETs at both off- and on-state are schematically illustrated in Fig. 2.8. Due to the large SBHs of NiSi to both electrons and holes, NiSi S/D SB-MOSFETs can be operated as either n- or p-type device leading to the typical ambipolar behavior. Both the operations of n- and p-type devices are shown in Fig. 2.8. For simplicity, only the discussion of p-type SB-MOSFET is presented. All factors contributing to off-current (Ioff) and on-current (Ion) are also illustrated in Fig. 2.8.

Chapter 2. Device Physics, Downscaling and Novel Device Architectures

n-type p-type Off-state

V =-V V =0 ds dd g Vg=0 Vds=Vdd

On-state

Vg=-Vdd Vds=-Vdd

Vg=Vdd Vds=Vdd

Fig. 2.8. Schematic energy band diagrams to demonstrate the operation principles of SB-MOSFETs. Left panel: p-type SB-MOSFET. Right panel: n-type SB-MOSFET.

Integration of metallic source/drain contacts in MOSFET technology

OFF-STATE

As with any MOSFET technology, Ioff of SB-MOSFET is typically dominated by three components showing in Fig. 2.8. These three components are: gate-induced drain leakage

(IGIDL), junction leakage (Ij), and S/D thermionic emission leakage Ith.

Ioff=IGIDL+Ij+Ith (2.7)

The first term, IGIDL, is caused by the gate induced narrowing of SB at the drain, which results in the electrons tunneling through the relative tall but thin SB. The amount of electrons tunneling causing IGIDL is very sensitive to the SBH. Therefore, the substrate materials with lower band gaps such as germanium would suffer from significant IGIDL. IGIDL is also very sensitive to the SB width, which is controlled by the potential at the drain. The thickness of gate oxide and Vg, which determine the electric field and potential profile at the drain, affect

IGIDL as well.

Ij is a component caused by the reverse-biased Schottky diode at the drain, i.e., silicide/p-type substrate here. This component can be reduced significantly by optimizing the doping concentration in the substrate or using SOI substrate [23].

The most significant contributor to Ioff is Ith, which results from the source-to-drain thermionic emission of holes. Because of the presence of SB at the source, a SB-MOSFET has an intrinsic advantage in controlling Ith since the SB plays a roll of a pocket or HALO implant, without having to add any dopant to the channel region.

ON-STATE

When both Vg and Vds are biased at negative potential, the electric field is very large thus “pull up” the energy band at the source. As a result, the SB at the source is thinned considerably, and holes can tunnel through the SB thus forming field emission current (Ife). At the same time, thermionic emission of holes over the SB is also possible giving rise to thermionic emission current (Ith). Both Ife and Ith contribute to Ion.

Ion=Ith+Ife (2.8)

The thermionic emission current is [3]:

Chapter 2. Device Physics, Downscaling and Novel Device Architectures

⎛⎞qV *2−qφb kT IAATeeth =−⎜⎟1 (2.9) kT ⎝⎠

* where A is the device area, A is the Richardson constant, φb is the SBH, T is the absolute temperature and V is the applied bias. However, due to the complexity in obtaining the analytical expression of Ife, it is often simulated by means of numerical means.

At on-state, due to the high SBH of NiSi to holes, Ith is basically negligible. On the contrary,

Ife increases rapidly when Vg and Vds increase leading to greatly thinned SB width. The drive current of SB-MOSFETs with large SBHs is dominated by Ife. Hence, the SB-MOSFET is often referred to as a field-emission device at on-state.

The calculation of Ith is relatively simple and straightforward; however, an accurate estimate of Ife is very complex, and to some extent impossible, since many factors such as the tunneling probability and barrier shapes are tangled. Some simple analytical expressions have been proposed to estimate Ife [32, 33], but the accuracy needs to be evaluated. On the other hand, computational means are usually used to simulate Ife. Two popular techniques, Wenzel- Kramers-Brillouin (WKB) approximation and exact Airy function, to model tunneling probabilities have been usually adopted to simulate Ife [34-36]. Ife simulated by these techniques can be several orders of magnitude different from the results predicted by analytical expressions, especially at high electric field strength. The simulation also shows that Ife is very sensitive to electric field strength and φb at the source, recommending that a high electric field strength and low φb are necessary to obtain high Ife.

Since both Ith and Ife contribute to on-current, one may argue which component is the dominant contributor. Normally, when φb at the source terminal is large, Ith is relatively small since not so many electrons have enough energy to surmount the high SB. At the same time,

Ife increases significantly with thinning the SB width by increasing gate and drain potential.

Under such circumstances, Ife dominates the on-current. When φb is small at the source, there is still some debate concerning the dominant component of Ion. In most published papers, Ife is believed to be the dominant component [37-39]; however, in a simulation study of Vega

[34], it suggests that, for small φb, Ife does not always play a dominant role in the total on- current. Apparently there is still need of physics and models for understanding Ion of SB- MOSFETs.

Integration of metallic source/drain contacts in MOSFET technology

2.4.3 DIBL-like effect of SB-MOSFETs

Fig. 2.9 shows the typical Ids-Vg characteristics for a p-type SB-MOSFET of Lg=1 μm under different Vds. As seen, in the electrons branch, increasing Vds leads to an increased Ioff which is similar to the increased Ioff due to DIBL in a conventional MOSFET. However, the origin of this DIBL-like effect is not a result of barrier lowering and it actually occurs for both short- and long-channel SB-MOSFETs. The reason of this DIBL-like effect for a p-type SB- MOSFET can be explained using the energy band diagram shown in Fig. 2.10.

-6 10 V from -0.3 to -0.9 V ds 10-7

-8 10 (A)

ds I 10-9

10-10

10-11 -2 -1 0 1 2 V (V) g

Fig. 2.9. Measured Ids-Vg transfer characteristics of a NiSi S/D SB-MOSFET with

Lg=1 μm at different negative Vds.

At a set Vg and negative Vds, Ioff mainly arises from electron tunneling current through the SB at the drain. When Vg is kept unaltered while Vds becomes more negative, the SB width at the drain becomes thinner as shown in Fig. 2.10(b) thus more electrons can tunnel through the

SB into the channel. As a result, Ioff increases. Hence this DIBL-like effect is not a DIBL but a typical behavior of SB-MOSFETs.

Chapter 2. Device Physics, Downscaling and Novel Device Architectures

(b) (a)

Fig. 2.10. Energy band of a p-type SB-MOSFET at off-state with (a) small negative Vds, and

(b) a large negative Vds. DIBL-like behavior of SB-MOSFET is shown schematically.

2.4.4 SCEs of SB-MOSFETs

For short-channel SB-MOSFETs, the potential distribution along the channel is strongly affected by the drain bias. This modifies the potential distribution of the entire channel as described as follows. The depletion region at the drain penetrates deeper into the channel region with increasing Vds and influences the control of the channel charge by the gate. Under such circumstances, short-channel SB-MOSFETs demonstrate large SS and no saturation in the output characteristics (cf. Chapter 4). These phenomena are termed SCEs of SB- MOSFETs. SCEs of SB-MOSFETs are typically characterized by drain induced barrier thinning (DIBT) [40, 41] as shown in Fig. 2.11 for long- and short-channel SB-MOSFETs.

For a p-type SB-MOSFET at on-state, when Vds increases, a higher electric field penetrates into the channel leading to a thinned SB width. This in turn results in an increased hole tunneling current. For long-channel SB-MOSFETs, the increase of Vds almost has no effect on the thinning of SB width. However, for a short device, the increase of Vds gives rise to a thinned or narrowed SB width at the source. DIBT is a typical SCE of short-channel SB- MOSFETs.

Integration of metallic source/drain contacts in MOSFET technology

ΔVds ΔVds X XT Δ T

φb φb

Fig. 2.11. Energy band diagram of p-type SB-MOSFETs at on-state with different Vds showing that the DIBT effect for (a) long-channel device is negligible, and (b) short- channel device is prominent.

Chapter 2. Device Physics, Downscaling and Novel Device Architectures

References

1. D. Kahng and M. M. Atalla, DRC, Pittsburg (Filed 1960); US Patent “Electric field controlled semiconductor devices,” No. 3, 102, 230, 1963. 2. F. Wanlass and C. T. Sah, “Nanowatt logic using field-effect metal-oxide-semcondutor triodes,” Technical digest of the Int. solid-state circuit Conf., IEEE, pp. 32-33, 1963. 3. S. M. Sze, Physics of Semiconductor Devices, 2nd edition (Wiley, New York, 1981), Chapter 6. 4. Y. Taur and Tak H. Ning, Fundamentals of modern VLSI devices, Cambridge University Press, 1998. 5. B. G. Streetman and S. Banerjee, Solid state electronic devices, 5th edition (Prentice Hall, 2000), Chapter 6. 6. R. Dennard, F. Gaensslen, H. Yu, V. Rideout, E. Bassous, and A. Leblanc, “Design of ion-implanted MOSFETs with very small physical dimensions,” IEEE J. solid-state circuits, SC-9, pp. 256-268, 1974. 7. G. Baccarani, M. R. Wordeman, and R. H. Dennard, “Generalized scaling theory and its application to a ¼ micrometer MOSFET design,” IEEE Trans. Electron Devices, ED-31, pp. 452, 1984. 8. K. Uchida, R. Zednik, C.-H. Lu, H. Jagannathan, J. Mcvittie, P. C. Mcintyre and Y. Nishi, “Experimental study of biaxial and uniaxial strain effects on carrier mobility in bulk and ultrathin-body SOI MOSFETs,” IEDM Tech. Dig., pp. 229-232, 2004. 9. S. Datta, G. Dewey, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, R. Kotlyar, M. Metz, N. Zelick and R. Chau, “High Mobility Si/SiGe Strained channel MOS transistors with HfO2/TiN gate stack,” IEDM Tech. Dig.,pp. 653-656, 2003 10. H. Shang, M. Frank, E. Gusev, J. Chu, S. Bedell, K. Guarini, M. Ieong, “Germanium channel MOSFETs: opportunities and challenges,” IBM Journal of Research and Development, vol. 50, no. 4/5, pp. 377-386, 2006. 11. C. Hu, “Gate oxide scaling limits and projections,” IEDM Tech. Dig.,pp. 96-99, 1996. 12. J. H. Stathis and D. J. DiMaria, “Reliability projections of ultra-thin oxide at low voltage,” IEDM Tech. Dig.,pp. 167-170, 1998. 13. T.-J. King, “Gate material issues for high-k gate dielectrics,” IEEE SICS, Washington D. C., 2002.

Integration of metallic source/drain contacts in MOSFET technology

14. R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros and M. Metz, "High-k/metal-gate stack and its MOSFET characteristics," IEEE Electron Device Lett., vol. 25, no. 6, pp. 408-410, Jun. 2004. 15. International Technology Roadmap for Semiconductors (IRTS), 2006 update, http://public.itrs.net/. 16. X. J. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-Kyu. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor and C. M. Hu, “Sub 50-nm FinFet: PMOS,” IEDM Tech. Dig., pp. 67–70, 1999. 17. J. P. Colinge, ”Multi-gate MOSFETs,” Solid-state electronics, vol. 48, no. 6, pp. 897-905. 18. N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R. Kumar, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong, ”High-performance fully depleted silicon nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices,” IEEE Electron Device Lett., vol. 27, no. 5, pp. 383-386, May. 2006. 19. K. K. Young, “Short-channel effect in fully depleted SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 36, no. 2, pp. 399-402, Feb. 1989. 20. J. C. S. Woo, K. W. Terrill, and P. K. Vasudev, “Two-dimensional analytic modeling of very thin SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 37, no. 9, pp. 1999-2006, Sept. 1999. 21. A. M. Waite, N. S. Lloyd, P. Ashburn, A. G. R. Evans, T. Ernst, H. Achard, S. Deleonibus, Y. Wang, P. Hemment, “Raised source/drain (RSD) for 50 nm MOSFETs- effect of epitaxy layer thickness on short channel effect,” Proc. ESSDERC, pp. 223-226, 2003. 22. C. Mazure, J. Fitch, and C. Gunderson, “Facet engineered elevated source/drain by selective Si epitaxy for 0.35 micro MOSFETs,” IEDM Tech. Dig., pp. 853–856, 1992. 23. J. M. Larson, J. P. Snyder, “Overview and status of metal S/D Schottky-barrier MOSFET technology,” IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1048-1058, May. 2006. 24. C. Wang, J. P. Snyder, J. R. Tucker, “Sub-40 nm PtSi Schottky source/drain metal-oxide- semiconductor field-effect transistors,” Appl. Phys. Lett., vol. 74, no. 8, pp. 1174-1176, 1990. 25. S. Xiong, T. J. King, and J. Bokor, “A comparison study of symmetric ultrathinbody double-gate devices with metal S/D and doped S/D,” IEEE Trans. Electron Devices, vol.52, no. 8, pp. 1859-1867, 2005.

Chapter 2. Device Physics, Downscaling and Novel Device Architectures

26. M. Ieong, P. M. Solomon, S. E. Laux, H. P. Wong and D. Chidambarrao, “Comparison of raised and Schottky source/drain MOSFETs using a novel tunneling contact model,” IEDM Tech. Dig., pp. 733-736, 1998. 27. J .Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T.-J. King, C. M. Hu, ”Complementary silicide source/drain thin-body MOSFET for the 20 nm gate length regime,” IEDM Tech. Dig., pp. 57-60, 2000. 28. S. Zhu, J. Chen, M.-F. Li, S. J. Lee, J. Singh, C. X. Zhu, A. Du, C. H. Tung, A. Chin, D. L. Kwong, ”N-type Schottky barrier source/drain MOSFET using Ytterbium silicide,” IEEE Electron Device Lett., vol. 25, no. 8, pp. 565-3567, 2004. 29. M. Zhang, J. Knoch, Q. T. Zhao, S. Lenk, U. Breuer, S. Mantl, ”Schottky barrier height modulation using dopant segregation in Schottky-barrier SOI-MOSFETs,” Proc. ESSDERC, pp. 457-460, 2005. 30. H.-S. Wong, L. Chan, G. Samudra, and Y.-C. Yeo, “Sub-0.1 eV effective Schottky- barrier height for NiSi on n-type Si (100) using antimony segregation,” IEEE Electron Device Lett., vol. 28, no. 8, pp. 703-705, Aug. 2007. 31. Z.-J. Qiu, Z. Zhang, M. Östling and S.-L. Zhang, “A comparative study of two different schemes to dopant segregation at NiSi/Si and PtSi/Si interfaces for Schottky barrier height lowering,” IEEE Trans. Electron Devices, vol.55, no. 1, pp. 396-403, 2008. 32. R. Hattori, A. Nakae, and J. Shirafuji, “A new type of tunnel-effect transistor employing internal field emission of Schottky barrier junction,” Jpn. J. Appl. Phys., vol. 31, no. 10B, pp. L1467-L1469, Oct. 1992. 33. F. A. Padovani and R. Stratton, “Field and thermionic-field emission in Schottky barriers,” Solide State Electron., vol. 9, no. 7, pp. 695-707, Jul. 1966. 34. R. A. Vega, “On the modeling and design of Schottky field-effect transistors,” IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 866-874, Apr. 2006. 35. R. A. Vega, “Comparison study of tunneling models for Schottky field effect transistors and the effect of Schottky barrier lowering,” IEEE Trans. Electron Devices, vol. 53, no. 7, pp. 1593-1600, Jul. 2006. 36. B. Winstead and U. Ravaioli, “Simulation of Schottky barrier MOSFET’s with a coupled quantum injection/Monte Carlo technique,” IEEE Trans. Electron Devices, vol. 47, no. 6, pp. 1241-1246, Jun. 2000. 37. J .Knoch and J. Appenzeller, “Impact of the channel thickness on the performance of Schottky barrier metal-oxide-semiconductor field-effect-transistors,” Appl. Phys. Lett., vol. 81, no. 16, pp. 3082-3084, Oct. 2002.

Integration of metallic source/drain contacts in MOSFET technology

38. J. Guo and M. S. Lundstrom, “A computational study of thin-body, double-gate, Schottky barrier MOSFETs,” IEEE Trans. Electron Devices, vol. 49, no. 11, pp. 1897- 1902, Nov. 2002. 39. S. Xiong, T.-J. King, and J. Bokor, “A comparison study of symmetric ultrathin-body double-gate devices with metal source/drain and doped source drain,” IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 1859-1867, Aug. 2005. 40. M. Jang, J. H. Oh, S. Maeng, W. Cho, S. J. Lee, K. C. Kang, and K. Park, “Characteristics of erbium-silicided n-type Schottky barrier tunnel transistors,” Appl. Phys. Lett., vol. 83, no. 13, pp. 2611-2613, Sep. 2003. 41. M. Jang, Y. Kim, J. Shin, S. Lee, and K. Park, “A 50-nm-gate-length erbium-silicided n- type Schottky barrier metal-oxide-semiconductor field-effect transistor,” Appl. Phys. Lett., vol. 84, no. 5, pp. 741-743, Feb. 2004.

Chapter 3. Implementation of Ni1-xPtx (x=0∼1) Silicides

Owing to numerous advantages such as low specific resistivity, low contact resistance, good thermal stability and excellent process compatibility with standard Si technology, metal silicides, formed by the reaction of metals (e.g., Ti, Co, Pt, Ni or Ni/Pt, etc) with Si during thermal annealing, have since the invention been playing an indispensable role in CMOS technology as the contact and local interconnection materials in order to reduce the parasitic resistance of S/D and gate. Moreover, the innovative invention of self-aligned metal silicide (SALICIDE) process [1], paves the way for the integration of silicides into today’s electronic devices. SALICIDE process is also the key process for the fabrication of SB-MOSFETs in Chapter 4. In this chapter, some issues of the SALICIDE process and the choice of silicides for SB-MOSFETs discussed in Chapter 4 will be presented first. It will be then followed by the discussion about the effects of carbon (C) and nitrogen (N) on the formation and Schottky barrier height (SBH) of NiSi by dopant segregation (DS). The discussion will refer to the results in Paper I and II. Through a systematic study of the variation of specific contact resistivity (ρc), the dipole formation at the PtSi/Si interface is proved to be the cause of SBH tuning by DS. Besides, as the top Si layer of UTB-SOI substrates becomes thinner and thinner in order to improve devices performance [2, 3], so do silicide films. As a result, a preliminary work on ultrathin Ni1-xPtx silicides (x=0∼1) for the purpose of perspective devices formed on extremely thin SOI substrates (tSi∼10 nm) was carried out. Some interesting results leading to Paper III and IV are also shown in this chapter. It is worth noting that the material investigation in this chapter lays down the infrastructure of real devices, i.e., NiSi or PtSi S/D SB-MOSFETs, in Chapter 4.

3.1 SALICIDE process and choice of silicides for SB-MOSFETs

3.1.1 SALICIDE process

SALICIDE process is one of the key processes in the fabrication of modern CMOS. The simultaneous formation of the same kind of metal silicides in S/D and gate regions not only simplifies the processing significantly, but also improves the process reliability greatly by, for instance, avoiding direct patterning the silicides/Poly-Si stack. In some sense, the extensive adoption of metal silicides in microelectronics industry benefits from no other than SALICIDE process.

Integration of metallic source/drain contacts in MOSFET technology

A typical SALICIDE process is schematically shown in Fig. 3.1 and a simple description of this process is provided as what follows. After the MOSFET structure is formed and isolated by either STI or LOCOS, a layer of metal (e.g., Ti, Co, Pt, Ni or Ni/Pt) is deposited all over the whole device structure [Fig. 3.1 (a)]. Usually a one-step or two-step annealing either in furnace or in rapid thermal processing (RTP) chamber is performed to induce the formation of metal silicide in S/D and gate regions exposed to metal [Fig. 3.1 (b)]. Other parts of the whole structure such as spacers and isolation regions are not silicided since no Si is available in these regions. The un-reacted metal will be selectively removed by wet chemical solution leaving the final structure in Fig. 3.1 (c). For the two-step annealing SALICIDE process, a 2nd thermal treatment is needed at higher temperature to convert the metal-rich phase to another phase of better conductivity or stability. The significance or the beauty of SALICIDE process is the maskless feature. That is to say, without mask the silicide can be formed precisely in S/D and gate regions, or self-aligned. This is, actually, a great ease of both process complexities and cost in the fabrication of CMOS.

Although almost all metal elements in the periodic table can react with Si and form metal silicides, the choices of silicides are actually very limited according to the following requirements of silicides which can be used in microelectronic industry [4, 5]:

Low resistivity (limits contact alignment issues and reduce device resistance) Etch selectivity of the silicides vs. the metal (allows self-aligned process) Etch resistance in reactive ion etch (RIE) environment (allows opening of via holes) Acceptable diffusion barrier properties Low roughness (gives a minimal junction penetration) Preferably high resistance to oxidation Good morphological stability (films must retain their shape through the back-end-line processing) Minimal Si consumption (limited doped Si available) Satisfactory thermal and mechanical properties with reference to Si No detrimental contamination that will affect devices performance

Chapter 3. Implementation of Ni1-xPtx (x=0∼1) Silicides

Fig. 3.1. Schematic process flow of SALICIDE process showing (a) a layer of metal is deposited all over the device; (b) metal silicide is formed in S/D and gate regions during thermal annealing; (c) the final device structure after the removal of un-reacted metal.

Integration of metallic source/drain contacts in MOSFET technology

Taking all these criteria into account, the choices of silicides are in fact limited to TiSi2,

CoSi2, PtSi, and NiSi.

3.1.2 Choice of silicides for SB-MOSFETs

A summary of properties for common silicides is shown in Table I. it will be followed by the discussion of the evolution of silicides.

Table I. A summary of properties for different silicides [6-9]

Silicidation Melting Controlling Resistivity Schottky Moving Si Silicide temperature temperature mechanism barrier height species (μΩ-cm) consumption to n-Si ( eV) (oC) (oC) (oC)

TiSi2 15-25 750-900 1500±10 nucleation Si 0.904 0.60

Co2Si >180 ∼400 1320 diffusion Co 0.62 0.69

CoSi >180 400-600 1460 diffusion Si 0.91 0.68

nucleation

CoSi2 15-20 600-750 1326 Co, Si 1.04 0.64 diffusion

Pt2Si ∼40 ∼400 1100 diffusion Pt 0.43 0.85

PtSi 28-35 500-700 1229 diffusion Pt 0.67 0.88

Ni2Si ∼24 200-300 1306 diffusion Ni 0.61 0.70

NiSi 10-20 300-500 992 diffusion Ni 0.82 0.68

NiSi2 ∼34 ∼750 993 nucleation Ni 1.02 0.70

Chapter 3. Implementation of Ni1-xPtx (x=0∼1) Silicides

The Ti silicide was the first one to be widely implemented in the SALICIDE technology for CMOS devices. Ti SALICIDE process, compared to others, is much less sensitive to oxidation contamination at the Si surface because it can reduce suboxide and dissolve the oxygen by reacting Ti with oxygen. This unique capability of Ti SALICIDE process and other properties of as-formed TiSi2, such as low resistivity, high thermal stability, and low contact resistivity to both types of Si, lead to the common implementation of TiSi2 in microelectronics industry as the contact metallization as well as local interconnection material [10,11]. For TiSi2, there are two different crystallographic structures, i.e., the high- resistivity C49 phase (70-100 μΩ-cm) and the desired low-resistivity C54 phase. The phase transition from C49 to C54 is a nucleation-controlled process since the free energy change (driving force) is very small [12]. This leads to a low density of C54 nuclei within the C49 background [13] and consequently incomplete C49→C54 transformation. As a result, a drastically increased resistance with narrow gates occurs especially for the gates below 0.2 μm [6]. This effect is usually called “fine-line effect”. In order to combat with “fine-line effect” and augment the C54 nuclei density, the C49→C54 transformation temperature is required to increase from 750 to 900 oC. “Fine-line effect” and high temperature process impair the advantages and application of TiSi2 in the fabrication of state-of-the-art MOSFETs.

Owing to its lower resistivity and silicidation temperature compared to TiSi2, CoSi2 was therefore introduced as a replacement of TiSi2 below 0.2 μm technology nodes. However, some serious concerns about using CoSi2 limit the continued use of this material in future devices. These concerns are: (a) the sensitivity to contamination from oxygen, both at the surface and in the annealing atmosphere, makes the SALICIDE more complex and unreliable; (b) the rise in resistance with very narrow gates (∼50 nm) [14], which arises from the void formation within the narrow silicide lines [15]; (c) the large Si consumption during silicidation, which is especially unbearable and detrimental for the fabrication of very shallow junctions and very thin SOI devices [16]. Besides, since nucleation dominates the formation of CoSi2 from CoSi [17, 18], the interface between CoSi2 and Si is inherently rough which may cause significant degradation in contact resistance and devices performance.

Moreover, the difficulty in forming CoSi2 on SiGe-based substrates also limits the extensive use of CoSi2 [4, 6 and 19].

PtSi emerges to be advantageous for devices of gate length within sub-50 nm. Although PtSi was one of the first silicides studied for Schottky contact in CMOS technology [4], it was not

Integration of metallic source/drain contacts in MOSFET technology

commonly used like TiSi2, CoSi2 as contact metallization materials. PtSi possesses a high SBH of ∼ 0.9 eV to electrons. The high SBH to electrons makes it unfavorable for Ohmic contact to n-type substrate, whereas it is pretty desirable as the Schottky barrier S/D for p- type SB-MOSFETs since the SBH to holes is low (∼ 0.2 eV). In addition, other properties of

PtSi such as low formation temperature, low reactivity towards SiO2 and low Si consumption (in Table I), make it a competitive candidate in the application of p-type SB-MOSFETs as the S/D material. PtSi S/D SB-MOSFETs has been demonstrated with promising devices performance of both polarities recently [20-22]. In this thesis, the results of PtSi S/D SB- MOSFETs with As DS to transform devices characteristics from p-type to n-type are shown in Paper VI. Despite that PtSi has been successfully integrated into our devices, the Pt SALICIDE process is, in practice, a little complicated with respect to the two consecutive steps within it, i.e., a 1st silicide formation and a 2nd surface oxidation steps in order to protect as-formed PtSi from aggressive attacking of aqua regia [23]. Another important concern departing us from persisting on PtSi relates to the relatively large resistivity of it, i.e., 28-35 μΩ-cm.

NiSi

Fig. 3.2. A cross-sectional TEM micrograph of the pretty smooth interface of NiSi/Si.

Regarding the disadvantages existing for PtSi, it is, therefore, necessary to introduce NiSi. NiSi possesses numerous superior properties, such as low formation temperature (∼500 oC), low resistivity (10-15 μΩ-cm), and low Si consumption, which make it attractive for the

Chapter 3. Implementation of Ni1-xPtx (x=0∼1) Silicides

microelectronics industry [24]. Low formation temperature facilitates the integration of high- k and metal gate materials in the state-of-the-art devices. Low resistivity is needed for high performance devices nowadays. The low Si consumption is really an important concern for devices with ultra-shallow junctions, on SOI substrates where the amount of Si is limited in this thesis. Moreover, since Ni silicidation is a diffusion-controlled process, the interface between NiSi and Si is rather smooth (Fig. 3.2), which is also, desired for high performance devices. All these properties of NiSi make it our natural choice in this thesis.

3.2 Properties of Ni1-xPtx silicide (x=0)

3.2.1 Effects of C and N on the formation of Ni1-xPtx silicide (x=0)

One of the critical problems involving the use of NiSi, however, is the relatively poor morphological stability as a consequence of low melting point. Two phenomena are observed for the poor stability. One concern is the transformation of the low-resistivity NiSi to the o high-resistivity NiSi2 at ∼750 C in the presence of excess Si, since NiSi2 is thmodynamically stable with Si. Another concern is the morphological instability of NiSi films that start to agglomerate at 600 oC. The most commonly used method to improve it is to add additions like Pt, Pd, etc [25-27].

Recently, the incorporation of C in Si substrate prior to Ni deposition and subsequent silicidation has been shown to improve the morphological stability of NiSi [28]. In addition, the presence of C or N has been suggested to play a crucial role in controlling the interfacial reaction between Ni and Si [29-32]. As a result, in this thesis, we have tried to use C and N implantation to improve the thermal stability of NiSi. The C and N were implanted into Si substrates prior to the Ni metal deposition and silicidation. The effects of C and N on the formation of NiSi were investigated.

Different doses of C and N were implanted into Si substrate 20 nm below the surface and subsequent Ni silicidation were carried out. Judging from the sheet resistance variation of NiSi films with different doses of C and N vs. silicidation temperature, the presence of C and N indeed improve the morphological stability of NiSi films. As seen in Fig. 3.3, the sheet resistance keeps decreasing till 750 oC for films with C and N implantation, while starts to

Integration of metallic source/drain contacts in MOSFET technology

Ref. ) 1· 1014 cm-2 C 14 -2

/sqr. 5· 10 cm C

Ω 10 15 -2 ( 1· 10 cm C 5· 1015 cm-2 C

Sheet Resistance

400 500 600 700 800 900 Silicidation Temperature ( oC)

Fig. 3.3. Variation of sheet resistance with silicidation temperature with different C or N implantation doses.

o (a) Reference,750 C (b) 5×1015 cm-2 C, 750 oC

Fig. 3.4. Top-view SEM images of NiSi films formed at 750 oC showing (a) void formation in reference with neither C nor N, (b) spectacular surface for films 15 -2 15 -2 implanted with 5×10 cm C, and (c) with 5×10 cm N.

Chapter 3. Implementation of Ni1-xPtx (x=0∼1) Silicides

from 600 oC for the reference NiSi film as a result of the degradation of film integrity. In Fig. 3.4, the spectacularly improved morphology for NiSi films with C and N implantation compared to the reference film is evident by HR-SEM. However, the sheet resistance of NiSi films with C and N implantation is increased. The reason is partly due to the distributed C and N atoms in the silicide films and to the segregated C and N atoms at the NiSi/Si interface, and partly due to the decreased silicide film thickness. According to the secondary ion mass spectrum (SIMS), during the silicidation, part of the C and N distribute within the silicide films and part of them is driven to the interface. Regarding more extensive results in this section, they are presented in Paper I and II.

3.2.2 Effects of C and N on SBH of Ni1-xPtx silicide (x=0) by DS

Knowing that the incorporation of C and N improves the morphological stability of NiSi significantly, it is of nature to integrate them into the fabrication of SB-MOSFETs. However, another problem more related to the performance of SB-MOSFETs emerges. According to simulations [33], the SBHs at the source terminal should be as low as possible in order to improve the devices performance. The intrinsic SBHs of NiSi for both electrons and holes, unfortunately, are large, which limit the devices performance. In order to combat large SBHs, many solutions such as surface passivation, dopant segregation (DS) and alloying have been studied to reduce them [34-38]. Among them, DS is the most reproducible and compatible techniques with standard Si technology to tune the large SBHs to low values [36, 37]. As a result, DS is also the technique used in this thesis.

In our previous work, the SBHs tuning of NiSi was successful in the absence of C and N [36, 37] by DS. However, how C and N interact with dopants (i.e., B and As) thus affect the tuning of SBHs is unknown. Hence, it is of interest to investigate the possible interactions of C and N with B and As used for DS aiming at modification of the SBHs of NiSi in this thesis.

A silicide as diffusion source (SADS) scheme instead of a silicidation induced dopant segregation (SIDS) scheme was performed for DS due to the ease of processing. The key processing steps are summarized in Fig. 3.5. Cautions should be exercised for two issues regarding the experimental design. First, C and N cannot be implanted too deep into the substrate otherwise the Ni silicidation cannot reach the implanted regions. Second, the

Integration of metallic source/drain contacts in MOSFET technology

deposited Ni should be thick enough to consume the implanted Si regions during the silicidation.

The modification results of SBHs without the presence of C and N by DS are in good agreement with our previous results [36, 37]. Both C and N themselves are found to take part in the modification of SBHs but to different roles. The C implantation causes a substantial increase in SBHs for electrons (i.e., effective work function closer to the valance band) but the N implantation yields an observable decrease in SBHs for electrons (i.e., effective work function closer to the conduction band). Furthermore, with B and As DS, it is found that the presence of both C and N yields positive effects in helping reduce the effective SBHs to 0.1- 0.2 eV for both conduction polarities. The reasonable explanations and explicit experimental data on the SBHs tuning of NiSi with/without the presence of C and N can be found in Paper I and II.

Chapter 3. Implementation of Ni1-xPtx (x=0∼1) Silicides

Fig. 3.5. Schematic SADS process flow for the designed experiment in this thesis.

Integration of metallic source/drain contacts in MOSFET technology

3.3 Mechanism of SBH tuning by DS

Although the SBH has been modified by DS, the mechanism behind the SBH modification, however, is not very clear. During the course of studying the mechanism of DS on SBHs, either current-voltage (I-V) characteristics or capacitance-voltage (C-V) measurements have been used for extraction of the SBHs on Schottky diodes with the silicide as the contacting electrode. However, large reverse leakage currents occur when the SBH is below 0.6 eV defeating the credibility and accuracy of extraction with C-V method. Low-temperature I-V measurements are often necessary in order to reliably access low SBHs [35]. In this thesis work, an alternative approach on the basis of measurements of forward current at room temperature is introduced. This method relies on characterizing specific contact resistivity

(ρc) by monitoring its variation with DS. We will show that the use of this method leads to confirmation of the formation of an interfacial dipole as the dominating mechanism responsible for the modification of effective SBH induced by DS.

The key process steps are schematically summarized in Fig. 3.6. Cross-bridge Kelvin resistors (CBKR) of a range of different contact dimensions were designed for contact resistivity extraction [39]. SADS was chosen for DS, because of its ease of process control [36], [37] as compared to SIDS. Both p- and n-type Si (100) wafers were used to allow for studies of both conduction polarities. Device isolation was realized using LOCOS process with an 800-nm thick SiO2 to define the diffusion regions. High concentration doping in the diffusion regions was achieved by ion implantation of boron (at 50 keV) and phosphorus (at 140 keV), both at a dose of 1×1016 cm-2, into the n- and p-type substrate, respectively, followed by an extensive anneal at 1000 oC for 12 hours. According to numerical simulations using ISE TCAD [40], a 2-μm deep, uniform junction would be formed with a surface concentration of 7×1019 cm-3 for both types of diffusion regions. After deposition of a

Si3N4/SiO2 layer stack, square contact windows of various dimensions were defined. By stripping the Si3N4/SiO2 layer stack in the contact window, a 20-nm-thick platinum layer was deposited by means of electron-beam evaporation. A two-step rapid-thermal-processing (RTP) was employed to achieve self-aligned silicidation of the diffusion regions; first at 500 oC for o 30 s in N2 to form PtSi, and then at 600 C for 60 s in O2 in order to form a protective SiO2 layer for subsequent aqua regia etching [41]. Ion implantation of arsenic and born, both to a 1×1015 cm-2 dose, into the formed 40 nm-thick PtSi film was performed at 12 and 4 keV, respectively. Monte Carlo simulations showed that the implanted ions should be mainly

Chapter 3. Implementation of Ni1-xPtx (x=0∼1) Silicides

confined in the PtSi film and the shallow implantation would yield a concentration at the PtSi/silicon interface below 1×1015 cm-3. Dopant drive-in was then carried out for 30 s between 500 and 700 oC. To monitor dopant deactivation in the substrate [42], [43], identical drive-in anneal was performed for control wafers without arsenic or boron implantation into the PtSi. The metal contact and leads, composed of a TiW/Al layer stack, was defined by deposition and subsequent dry etching. The fabrication process ended with forming gas annealing (FGA) at 400 oC for 30 minutes. Four-point probe measurements on the CBKR structures were performed using Agilent 4156A parameter analyzer.

(a) Substrate implantation (b)

Segregated dopants

Fig. 3.6. Schematic process flow for the fabrication of CBKR. (a) LOCOS for isolation followed by ion implantation of phosphorus or boron, both at 1×1016 cm-2 to form diffusion regions (b) Diffusion and activation of phosphorus and boron, followed by deposition of Si3N4/SiO2 layer stack. (c) Self-aligned formation of PtSi followed by ion implantation of boron or arsenic to the PtSi film on n- or p-type diffusion layer, respectively, both at 1×1015 cm-2. (d) Drive-in anneal for dopant segregation at the PtSi/Si interface.

Integration of metallic source/drain contacts in MOSFET technology

The measured CBKR values are shown in Fig. 3.7, (a) for p-type diffusion region with arsenic DS and (b) for n-type diffusion region with boron DS. The extracted ρc data are summarized in Table II. Two major observations are made. First, DS leads to an increase in

ρc for both systems with boron out-diffusion from PtSi on n-type diffusion region and arsenic out-diffusion from PtSi on p-type diffusion region. Second, the increase in ρc is temperature- dependent, but it quickly becomes saturated at high drive-in annealing temperatures. Deactivation of substrate doping in the diffusion regions during low temperature processing, i.e., silicide formation and subsequent SADS for DS, can be ruled out as the cause for observed increase in ρc, since similar anneals as in Fig. 3.7 of reference samples without boron or arsenic implantation into the PtSi did not lead to conclusive changes in ρc.

2 Table II. Results of ρc (in Ω-cm ) extracted using the CBKRs (Fig. 3.7) after different drive- in anneals for DS at PtSi/silicon interface.

Drive-in temperature (oC) Arsenic DS, p-type diffusion Boron DS, n-type diffusion

Reference 1.2×10-7 2.3×10-6

500 6.6×10-7 3.2×10-6

600 7.5×10-7 3.2×10-6

700 7.5×10-7 3.2×10-6

The observed increase in ρc in Fig. 3.7 can be anticipated due to the use of dopants of opposite polarity to the substrate doping in the diffusion regions. However, the saturation with the increase immediately rules out compensation doping of the diffusion regions near the PtSi/silicon interface as responsible for the increase in ρc. More out-diffusion of dopants of opposite polarity should occur at higher drive-in annealing temperatures leading to more compensation doping (or even reverting the type of doping) in the interface region. Since this non-saturation behavior is absent in the experiment, the formation of an interfacial dipole that induces an increase in effective SBH is thus concluded as the cause responsible for the increase in ρc. This conclusion supports our earlier discussions in [36], [37] where interaction

Chapter 3. Implementation of Ni1-xPtx (x=0∼1) Silicides

of dopants with point defects and subsequent dopant diffusion are considered insignificant, and hence the formation of an interfacial dipole is more likely to be the cause for the modification of effective SBH.

(a)Boron dopant segregation (b)Arsenic dopant segregation 100 No Drive in (Reference) No Drive in (Reference) ) ) o o Ω

Ω 500 C Drive in 500 C Drive in ( ( o o c c 100 600 C Drive in 600 C Drive in o 700 C Drive in 700 oC Drive in ρ ρ ρ c = c = 3. 10 6.6 c = 7 ρ 2· · .5 c = 1 -6 1 -7 · 2. 0 0 1 -7 3· Ω 0 - Ω 10 6 cm 2 cm 2 Ω Ω cm 2 cm 2 10 1 -7 2 ρ = 1.2·10 Ω cm c Contact Resistance, R

10 Contact Resistance, R 2 (μ ) 10 Contact Area m 2 Contact Area (μm )

Fig. 3.7. Measured data for CBKRs on (a) p- and (b) n-type diffusion regions, with arsenic and boron doping, respectively.

A couple of differences are found between the two types of doping. First, a more significant increase in ρc is evident for the arsenic DS on the p-type diffusion region than for the boron DS on the p-type diffusion region. This difference is easily understood since the SBH of PtSi without DS lies close to the valance band with qφbp≈0.2 eV and qφbn=0.93 eV [36], [37].

Hence, more room is available for reduction of qφbn than of qφbp. Second, calculations using

⎡ ⎤ the relationship 4 m*ε s φb as well as known physical parameters yielded the largest ρc ∝ exp⎢ ⎥ ⎣⎢ h N ⎦⎥ o change of qφbp by 0.1 eV for the arsenic DS on the p-type diffusion region at 600-700 C.

Similarly, the largest change of qφbn by 0.03 eV for the boron DS on the n-type diffusion region was calculated. These changes in SBHs are about 8 times smaller than those extracted using Schottky diodes made of PtSi formed on lightly doped substrates using C-V method [36], [37]. This difference is attributed to the difference in the strength of electric field due to space charge that is determined by the doping concentration in the substrate. According to [44], [45], the effective SBH is determined by the electric field at the metal-semiconductor

Integration of metallic source/drain contacts in MOSFET technology

interface. This electric field comprises two major components, one due to interfacial dipole and one due to space charge. These two electric field components are in opposition as shown schematically in Fig. 3.8. For the lightly doped substrates (1015 cm-3) used in the Schottky diodes [36], [37], the maximum electric field produced by ionized dopants is around 104 V/cm. For the heavily doped diffusion regions (7×1019 cm-3) used in the present work, the corresponding electric field is above 106 V/cm. If the segregated dopants at the silicide/silicon interface have a concentration of 1012 cm-2 which is about 0.1 at.% of a monolayer roughly corresponding to the bulk doping concentration of 7×1019 cm-3, the resulting electric field due to interfacial dipole is 105 V/cm. Therefore, the high electric field as a result of high doping concentration in the diffusion regions tends to shadow the effect of DS on the effective SBH.

(b) (a) Electric field due to space charge φbn Electric field due to interfacial dipole Metal Fermi level Fermi level Electric field due to Metal interfacial dipole

φbp Electric field due to space charge

Fig. 3.8. Schematic presentation of the energy band structure in the vicinity of the PtSi/silicon interface.

Chapter 3. Implementation of Ni1-xPtx (x=0∼1) Silicides

Heavy doping of the diffusion regions of the CBKRs has been chosen in the present work in order to avoid current crowding effects and recourse to complex extraction procedure [46], [47]. With lightly doped diffusion regions, a further risk is large uncertainties as a result of extracting a small quantity out of large quantities. Although use of lightly doped diffusion regions would allow for a direct comparison with the diode results, the analysis above clearly demonstrates the validity of the contact resistivity method in assessing how the Schottky barrier could be modified by means of DS as well as in confirming the formation of interfacial dipole as the responsible mechanism for the modification.

3.4 Ultrathin Ni1-xPtx silicides (x=0∼1)

As mentioned before, thin NiSi films often suffer from poor morphological stability and start to agglomerate at 600 oC as a consequence of the low melting point of NiSi at 992 oC. In order to combat the poor morphological stability, the addition of C and N aforementioned presents a potential solution. Besides, adding Pt to NiSi leading to the formation of the ternary monosilicide alloy Ni1-xPtxSi has been shown to be an effective solution [25-27]. The presence of Pt also prohibits the formation of the undesired NiSi2 as a result of a better phase stability of Ni1-xPtxSi than NiSi due to the mixing between Ni and Pt as well as a better stability of PtSi [11]. Up to date, most investigations on Ni1-xPtx (x=0∼1) silicides concern relatively thick films >10 nm (∼40-nm-thick NiSi films in section 3.2). For such films, a general trend, dictated by thermodynamics, prevails with thinner films agglomerating morphologically at lower temperatures. Furthermore, for CMOS devices fabricated on SOI substrates, the continuous dimensional down-scaling requires thinner Si layers than 5 nm in order to attain the predicted device/circuit performance [48]. Accordingly, the maximum thickness of Ni1-xPtxSi silicide films is reduced to sub-10 nm. Investigation on ultrathin silicide films, therefore, presents the preliminary step towards their integration in ultrathin SOI devices.

In this thesis, ultrathin Ni1-xPtx (x=0∼1) silicide films formed on Si (100) substrate were thoroughly studied. It is found that Pt-silicide (x=1) films of all thicknesses show normal behavior of morphological stability, as the resulting polycrystalline PtSi films always agglomerates at low temperatures for thinner films. Surprisingly, the Ni-silicide films exhibit

Integration of metallic source/drain contacts in MOSFET technology

two different morphological stability characteristics depending on the deposited thickness of

Ni (tNi). For tNi≥4 nm, polycrystalline NiSi films form and agglomerate at lower temperatures for thinner films like PtSi films; however, for tNi<4 nm, epitaxially aligned Ni-silicide films readily grow and exhibit extraordinary morphological stability up to 800 oC (Fig. 3.9a).

Adding Pt into Ni also improves the morphological stability of Ni1-xPtx silicide films.

In Fig. 3.9, cross-sectional and top-view TEM images of the ultrathin Ni-silicide film with o tNi=2 nm formed at 750 C are shown. Almost perfect epitaxially aligned Ni-silicide layer is observed [Fig. 3.9 (a)] and no obvious grain boundaries can be observed in Fig. 3.9 (b) which suggests either the grain size is very big or no grain boundaries at all.

5.4 nm NiSi2-y

Fig. 3.9. (a) Cross-sectional and (b) top-view TEM micrographs of the ultrathin Ni- o silicide film with tNi=2 nm formed at 750 C.

In an effort to identify the phase and interface morphology of this ultrathin Ni-silicide film with tNi=2 nm, the selective area electron diffraction (SAED) data along the [013] and [011] zone axes are also depicted in Fig. 3.10(a) and (b), respectively. The results strongly suggest the epitaxially aligned Ni silicide films to have the same fcc structure as Si. Among various phases of Ni-silicide, NiSi2 has fcc structure which naturally leads us to believe that this epitaxially aligned Ni silicide is NiSi2. However, with respect to the thickness ration of as- formed Ni silicide film [5.4 nm in Fig. 3.9(a)] to tNi (2 nm), 2.7, a problem emerges with the identification of NiSi2 phase. This ratio is far below the volume expansion factor 3.62 for Ni conversion to stoichiometric NiSi2 [5], and it further leads to NiSi1.6 by assuming this phase has the same lattice parameter as NiSi2.

Chapter 3. Implementation of Ni1-xPtx (x=0∼1) Silicides

(a) (b)

(c)

tNi=2 nm

tNi=5 nm

Fig. 3.10. SAED data together with their HR-TEM images along the zone axis (a) o [013] and (b) [011] for the epitaxially aligned Ni silicide films formed at 500 C with o tNi=2 nm, (c) EDS analysis of two silicide films formed at 500 C with tNi= 2 nm (upper panel) and tNi= 5 nm (lower panel).

Integration of metallic source/drain contacts in MOSFET technology

The EDS analysis for two silicide films, one with tNi= 5 nm and one with tNi= 2 nm is shown in Fig. 3.10(c). For the Ni-silicide film with tNi=5 nm, the formula of NiSi is evident by the atomic percentage of Ni and Si, 51% and 49% respectively. For the ultrathin Ni-silicide film with tNi= 2 nm, the formula is calculated to NiSi1.8 from the atom percentage of Ni and Si, 36% and 64% respectively. Due to the discrepancy in identifying this phase using two ways, we designate it as NiSi2-y (0

The extraordinary morphological stability of ultrathin NiSi2-y films with tNi< 4 nm, therefore, is attributed to the formation of epitaxially aligned NiSi2-y. More results about the characterization and theoretical explanation for the observed thickness and composition dependence of phase formation and morphology stability are shown in Paper III.

90 Ni

) 80 Pt Ni Pt -cm 70 0.96 0.04

μΩ Ni Pt ( 60 0.92 0.08 Ni Pt 0.86 0.14 50 40

Resistivity 30 20 10 0 5 10 15 20 25 30 35 40 45 Silicide thickness (nm)

Fig. 3.11. Variation in film resistivity with silicide film thickness for five different Ni Pt silicide films (x=0, 0.04, 0.08, 0.14 and 1). 1-x x

Chapter 3. Implementation of Ni1-xPtx (x=0∼1) Silicides

Apart from those results, the thickness reduction in the deposited metal films has also led to strongly varied resistivity values for the silicide films, as depicted in Fig. 3.11. For thicker films, the resistivity of NiSi films keeps fairly unaltered, 16 μΩ-cm in good agreement with the reported values [49]. Alloying with Pt leads to the resistivity increase which is due to the alloying scattering. In addition, a drastic increase in resistivity is observed when the film thickness is reduced to a certain thickness for four Ni1-xPtx silicide films (x=0, 0.04, 0.08, and 0.14). The aggressive resistivity increase for these silicide films is mainly caused by surface scattering effects although the phase change from the low-resistivity Ni(Pt)Si to the high- resistivity Ni(Pt)Si2 phase may also contribute. However, for PtSi films of all thickness, no drastic resistivity increase occurs and the expected increase of resistivity is basically attributed to the surface scattering.

In Paper III, we provide a reasonable explanation for the formation of epitaxially aligned Ni- silicide films with tNi< 4 nm. This explanation of surface-triggered epitaxial phase formation is mainly based on thermodynamics. In Paper IV, extensive HR-TEM studies are correlated to sheet resistance data shown in Paper III in order to shed more light on the kinetics and morphology of the epitaxial NiSi2-y.

Integration of metallic source/drain contacts in MOSFET technology

References

1. C. K. Lau, Y. C. See, D. B. Scott, J. M. Bridges, S. M. Perna, and R. D. Davies, “Titanium disilicide self-aligned source/drain + gate technology,” IEDM Tech. Dig., pp. 714-717, 1982. 2. Y. -K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J. Bokor and C. Hu, “Ultrathin-body SOI MOSFET for deep-sub-tenth micron era,” IEEE Electron device Lett., vol. 21, no. 5, pp. 254-255, 2000. 3. C. S. Woo, K. W. Terrill, and P. K. Vasudev, “Two-dimensional analytic modeling of very thin SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 37, no. 9, pp. 1999-2006, 1990. 4. S.-L. Zhang and M. Östling, ”Metal silicides in CMOS technology: past, present and future trends,” Critical reviews in solid state and materials science, vol. 28, no. 1, pp. 1- 129. 5. C. Lavoie, F. M. d’Heurle, and S.-L. Zhang, in Handbook of Semiconductor Manufacturing Technology, 2nd Edition, edited by Y. Nishi and R. Doering (Taylor & Francis CRC Press, 2007), Chapter 10. 6. H. Iwai, T. Ohguro, S.-I. Ohmi, “NiSi silicide technology for scaled CMOS,” Microelectronics Eng., vol. 60, no. 1-2, pp. 157-169, 2002. 7. Properties of metal silicides, edited by K. Maex and M. Van. Rossum (INSPEC, 1995). 8. M.-A. Nicolet and S. S. Lau, in chapter 6, “Formation and characterization of transition- metal silicids,” VLSI electronics microstructure science, edited by N. G. Einspruch and G. B. Larrabee, ACADEMIC PRESS, 1983. 9. E. H. Rhoderick and R. H. William, “Metal-semiconductor contact,” in Monographs in electrical and electronic engineering, Oxford, U. K, Clarendon, 1988. 10. F. M. d’Heurle, “Silicide interfaces in silicon technology,” J. Electron. Mater., vol. 27, no. 11, pp. 1138-1147, 1998. 11. S.-L. Zhang and U. Smith, “Self-aligned silicides for Ohmic contacts in complementary

metal-oxide-semiconductor technology: TiSi2, CoSi2, and NiSi,” J. Vac. Sci. Tchnol., A, vol. 22, no. 4, pp. 1361-1370, 2004. 12. F. M. d’Heurle, “Nucleation of a new phase from the interaction of two adjacent phases: some silicides,” J. Mater. Res., vol.3, no. 1, pp. 167-195, 1988.

Chapter 3. Implementation of Ni1-xPtx (x=0∼1) Silicides

13. J. A. Kittl, Q.-Z. Hong and M. R. Breedijk, “Scaled CMOS technologies with low sheet resistance at 0.06 μm gate lengths,” IEEE Electron device Lett., vol. 19, no. 5, pp. 151- 153, 1998. 14. J. A. Kittl, A. Lauwers, O. Chamirian, M. Van Dal, A. Akheyar, M. De Potter, R. Lindsay, and K. Maex, “Ni- and Co- based silicides for advanced CMOS applications,” Microelectronics Eng., vol. 70, no. 2-4, pp. 158-165, 2003. 15. R. Chau, J. Kavalieros, B. Roberds, R. Schenker, D. Lionberger, D. Barlage, B. Doyle, R. Arghavani, A. Murthy, and G. Dewey, "30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays," IEDM Tech. Dig., pp. 45-48, 2000. 16. A. Lauwers, M. De potter, O. Chamirian, R. Lindasy, C. Demeurisse, C. Vrancken, and K. Maex, ”Silicides for 100 nm-node and beyond: Co-silicide, Co(Ni)-silicide and Ni- silicide,” Microelectronics Eng., vol. 64, no. 1-2, pp. 131-142, 2002. 17. J. P. Gambino, and E. G. Colgan, “Silicides and ohmic contacts,” Mater. Chem. Phys., vol. 52, no. 2, pp.99-146, 1998. 18. R. Anderson, J. Baglin, J. Dempsey, W. Hammer, d’Heurle, and S. Petersson, ”Nucleation-controlled thin-film interactions: some silicides,” Appl. Phys. Lett., vol. 35, no. 3, pp. 285-287.

19. C. Detavernier, T. R. L. Van Meirhaeghe, F. Cardon, and K. Maex, “CoSi2 nucleation in the presence of Ge,” Thin Solid films, vol. 384, no. 2, pp. 243-250, 2001. 20. C. Wang, J. P. Snyder, and J. R. Tucker, “Sub-40 nm PtSi Schottky source/drain metal- oxide-semiconductor field-effect transistor,” Appl. Phys. Lett., vol. 74, no. 8, pp. 1174- 1176, 1999. 21. M. Fritze, C. L. Chen, S. Calawa, D. Yost, B. Wheeler, P. Wyatt, C. L. Keast, J. P.

Snyder, and J. Larson, “High-speed Schottky-barrier pMOSFET with fT= 280 GHz,” IEEE Electron device Lett., vol. 25, no. 4, pp. 220-222, 2004. 22. Z. Zhang, Z.-J. Qiu, P.-E. Hellström, G. Malm, J. Olsson, J. Lu, M. Östling, and S.-L. Zhang, “SB-MOSFETs in UTB-SOI featuring PtSi source/drain with dopant segregation,” IEEE Electron device Lett., vol. 29, no. 1, pp. 125-127, 2008. 23. Z. Zhang, S.-L. Zhang, M. Östling and J. Lu, “Robust, scalable self-aligned platinum silicide process,” Appl. Phys. Lett., vol. 88, no. 14, pp. 142114-1-142114-3, 2006. 24. C. Lavoie, F. M. d’Heurle, C. Detavernier and C. Cabral. Jr, “Towards implementation of a nickel silicide process for CMOS technologies,” Microelectronics Eng., vol. 70, no. 2-4, pp. 144-157, 2003.

Integration of metallic source/drain contacts in MOSFET technology

25. D. Mangelinck, J. Y. Dai, J. S. Pan, and S. K. Lahiri, ”Enhancement of thermal stability of NiSi films on (100) Si and (111) Si by Pt addition,” Appl. Phys. Lett., vol. 75, no. 12, pp. 1736-1738, 1999.

26. J. F. Liu, J. Y. Feng, and J. Zhu, “Film thickness dependence of the NiSi-to-NiSi2 transition ptemperature in the Ni/Pt/Si(100) system,” Appl. Phys. Lett., vol. 80, no. 2, pp. 270-272, 2002. 27. C. Lavoie, C. Detavernier, C. Cabral, Jr., F. M. d’Heurle, A. J. Kellock, J. Jordan-Sweet and J. M. E. Harper, “Effects of additive elements on the phase formation and morphological stability of nickel monosilicide films,” Microelectronics Eng., vol. 83, no. 11-12, pp. 2042-2054, 2006. 28. R. T.-P. Lee, L.-T. Yang, T.-Y. Liow, K.-M. Tan, A. E.-J. Lim, K.-W. Ang, D. M. Y. Lai, K. M. Hoe, G.-Q. Lo, G. S. Samudra, D.-Z. Chi, and Y.-C. Yeo, “Nickel-silicide: Carbon contact technology for N-channel MOSFETs with silicon-carbon source/drain,” IEEE Electron Device Lett., vol. 29, no. 1, pp. 89-92, 2008. 29. P. Kalra, N. Vora, P. Majhi, P. Y. Hung, H.-H. Tseng, R. Jammy, and T.-J. King Liu, “Modified NiSi/Si Schottky barrier height by nitrogen implantation,” Electrochem. Solid- State Lett., vol.12, no. 1, pp. H1-H3, 2009. 30. T. Ohguro, S. Nakamura, E. Morifuji, M. Ono, T. Yoshitomi, M. Saito, H. S. Momose, and H. Iwai, “Nitrogen-doped nickel monosilicide technique for deep submicron CMOS salicide,” Tech. Dig. Int. Electron Devices Meet., pp. 453–456, 1995. 31. L. W. Cheng, S. L. Cheng, J. Y. Chen, L. J. Chen, and B. Y. Tsui, “Effects of nitrogen ion implantation on the formation of nickel silicide contacts on shallow junctions,” Thin solid films, vol. 355-356, pp. 412-416, 1999. 32. K. Yamamoto, S. Sakashita, Y. Sato, M. Inoue, M. Anma, T. Oosuka, and J. Yugami, “Phase and composition control of Ni fully silicided gates by nitrogen ion implantation and double Ni silicidation,” Jpn. J. Appl. Phys., vol. 47, no. 4, pp. 2398-2401, 2008. 33. S. Xiong, T. J. King, and J. Bokor, “A comparison study of symmetric ultrathinbody double-gate devices with metal S/D and doped S/D,” IEEE Trans. Electron Devices, vol.52, no. 8, pp. 1859-1867, 2005. 34. M. Tao, D. Udeshi, N. Basit, E. Maldonado, and W. P. Kirk, “Removal of dangling bonds and surface states on silicon (001) with a monolayer of selenium,” Appl. Phys. Lett., vol. 82, no. 10, pp. 1559-1561, 2003.

Chapter 3. Implementation of Ni1-xPtx (x=0∼1) Silicides

35. Q. T. Zhao, U. Breuer, E. Rije, St. Lenk, and S. Mantle, “Tuning of NiSi/Si Schottky barrier heights by sulfur segregation during Ni silicidation,” Appl. Phys. Lett., vol. 86, no. 6, pp. 062108-1-062108-3, 2005. 36. Z. Zhang, Z.-J. Qiu, R. Liu, M. Östling and S.-L. Zhang,”Schottky barrier height tuning by means of ion implantation into pre-formed silicide films followed by drive-in annealing,” IEEE Electron device Lett., vol. 28, no. 7, pp. 565-568, 2008. 37. Z.-J. Qiu, Z. Zhang, M. Östling and S.-L. Zhang, “A comparative study of two different schemes to dopant segregation at NiSi/Si and PtSi/Si interfaces for Schottky barrier height lowering,” IEEE Trans. Electron Devices, vol.55, no. 1, pp. 396-403, 2008. 38. L. E. Terry and J. Saltich, “Schottky barrier heights of nickel-platinum silicide contacts on n-type Si,” Appl. Phys. Lett., vol.28, no. 4, pp. 229-231, Feb. 1976. 39. W. M. Loh, S. E. Swirhun, E. Crabbé, K. Saraswat, and R. M. Swanson, “An accurate method to extract specific contact resistivity using cross-bridge Kelvin resistors,” IEEE Electron Device Lett., vol. EDL-6, no.9, pp. 441-443, Sep. 1995. 40. ISE-TCAD, Integrated System Engineering AG, Zürich, Switzerland. 41. Z. Zhang, S.-L. Zhang, M. Östling, and J. Lu, “Robust, scalable self-aligned platinum silicide process,” Appl. Phys. Lett., vol. 88, no. 14, pp. 142114-1-142114-3, 2006. 42. M. Aboy, L. Pelaz, L. A. Marques, P. Lopez, J. Barbolla, V. C. Venezia, R. Duffy, and P. B. Griffin, “The role of silicon interstitials in the deactivation and reactivation of high concentration boron profiles,” Mater. Sci. Eng. B, vol. 114-115, pp. 193-197, 2004. 43. L. Romano, A. M. Piro, V. Privitera, E. Rimini, G. Fortunato, B. G. Svensson, M. Foad, and M. G. Grimaldi, “Mechanism of de-activation and clustering of B in Si at extremely high concentration,” Nucl. Instr. and Meth. B, vol. 253, no. 1-2, pp. 50-54, 2006. 44. J. M. Shannon, “Reducing the effective height of a Schottky barrier using low-energy ion implantation,” Appl. Phys. Lett., vol. 24, no.8, pp. 369-371, 1974. 45. J. M. Shannon, “Increasing the effective height of a Schottky barrier using low-energy ion implantation,” Appl. Phys. Lett., vol. 25, no.1, pp. 75-77, 1974. 46. W. M. Loh, S. E. Swirhun, T. A. Schreyer, R. M. Swanson, and K. C. Saraswat, “Modeling and measurement of contact resistances,” IEEE Trans. on Electron Devices, vol. ED-34, no.3, pp. 512-524, Mar. 1987. 47. R. L. Gillenwater, M. J. Hafich, and G. Y. Robinson, “The effect of lateral current spreading on the specific contact resistivity in D-resistor Kelvin devices,” IEEE Trans. on Electron Devices, vol. ED-34, no. 3, pp. 537-543, Mar. 1987.

Integration of metallic source/drain contacts in MOSFET technology

48. International Technology Roadmap for Semiconductors, 2008 Update ， (http://public.itrs.net). 49. Z. Zhang, S.-L. Zhang, B. Yang, Y. Zhu, S. M. Rossnagel, S. Gaudet, A. J. Kellock, J. J. Sweet and C. Lavoie, ”Morphological stability and specific resistivity of sub-10 nm silicide films of Ni1-xPtx on Si substrate,” Appl. Phys. Lett., vol.96, no. 7, pp. 071915-1- 071915-3, 2010.

Chapter 4. SB-MOSFETs: Fabrication and Characterization

Chapter 4. SB-MOSFETs: fabrication and characterization

Following the investigation on the material aspects of Ni1-xPtx (x=0∼1) silicides aiming at the integration in nanoscaled SB-MOSFETs in the preceding chapters as well as in the associated papers appended at the end, this chapter will focus on the integration of Ni1-xPtx (x=0∼1) S/D towards competitive SB-MOSFETs. First, the key issues and corresponding solutions related to the process integration of Ni1-xPtx (x=0∼1) S/D SB-MOSFETs formed on UTB-SOI substrates will be presented. It will be followed by the compatibility of NiSi integration issues with standard Si processing. This chapter is concluded by the fabrication and characterization of Ni1-xPtx silicide S/D SB-MOSFETs and SB-FinFETs, with reference to Papers V, VI, and VII.

4.1 Key issues related to integration and solutions

A successful fabrication of Ni1-xPtx (x=0∼1) silicides S/D SB-MOSFETs is, in fact, challenged by numerous issues at KTH. To summarize, three key issues are of vital importance, which are, methods for nanoscaled gate fabrication, the control of severe lateral encroachment of NiSi towards the channel, and high Schottky barrier heights of NiSi for both n and p channels.

4.1.1 Methods for nanowire fabrication

The nanowire of MOSFETs can be defined by conventional optical lithography with advanced equipment combined with pattern reduction technique [1] or immersion lithography [2] as done in the industry, EBL [3,4], or sidewall transfer lithography (STL) [5-12]. STL technology possesses some unique features compared to other technologies in fabricating nanowires. For instance, the STL technology automatically yields twin-nanowires if unless otherwise is desired at the same time. Furthermore, the nanowire fabricated by STL technology shows much better uniformity in comparison with those fabricated by EBL or dimensional reduction by ashing. Based on these advantages of STL technology and the equipment limitation in our clean room lab, the STL process is employed for the fabrication of nanoscaled SB-MOSFETs in this thesis work. An improved STL process has been developed at KTH [12] which is schematically depicted in Fig. 4.1.

Integration of metallic source/drain contacts in MOSFET technology

Cross-section Top-view

(a) Starting layer stack with Si nd (a) substrate, SiO2, poly-Si, 2 TEOS hard mask, α-Si supporting st sacrificial layer and 1 SiNx hard mask.

(b) st (b) Pattern and etch 1 SiNx hard mask, strip resist and etch α-Si down

to TEOS to form sidewall support.

st (c) (c) Remove 1 SiNx hard mask and deposit 55-nm-thick SiNx to define the gate length.

(d) Anisotropic etch of SiN to form (d) x rectangular SiNx sidewall nano- rings supported by α-Si.

(e) (e) Selective wet removal of supporting α-Si layer leaving free-

stand SiNx nano-rings.

(f) Define contacting leads and pads (f) with an additional resist mask

followed by oxide dry etch and nd poly-Si etch with 2 TEOS hard mask.

Fig. 4.1. Schematic presentation of the improved STL technology developed at KTH which is employed for massive fabrication of nanoscaled gates in this thesis.

Chapter 4. SB-MOSFETs: Fabrication and Characterization

This improved STL technology relies on: (1) a good thickness and step coverage control of the deposition of various thin films, (2) good anisotropic dry-etching to create vertical sidewall supports of α-Si, (3) excellent dry- and wet-etch selectivity of one material with respect to other materials, and (4) complete removal of the etch residuals, especially the wet removal of α-Si supporting layer. Regarding the processing details, they are shown in [10-12]. Compared to our previous STL technology using SiGe instead of α-Si as supporting layer [11, 12], the line edge roughness (LER) of nanowires fabricated by this improved STL technology is improved significantly. Fig. 4.2 shows the HR-SEM micrographs of two nanowires, one about 60 nm in width fabricated using the previous STL process [Fig. 4.2 (a)], and another one about 25 nm in width fabricated by the improved STL technology [Fig. 4.2(b)]. As seen, the Si nanowire fabricated by the improved STL technology is rather smooth and the LER is smaller compared to that one fabricated by old STL process.

(a) Previous STL process (b) Improved STL process

Fig. 4.2. Top-view HR-SEM micrographs of (a) a nanowire fabricated by previous STL process using SiGe as the supporting layer, and (b) a nanowire fabricated by improved STL process using α-Si as the supporting layer.

Integration of metallic source/drain contacts in MOSFET technology

4.1.2 Severe lateral encroachment of NiSi

The rapid diffusion of Ni has led to the so-called “reversed fine line effect” where the lower resistance is found in narrow dimensions [13-16]. The extra Ni atoms above the spacers or on the shallow trench isolation that are within the diffusion distance can increase the amount of reaction close to the Si line edges, which results in the thicker silicide on the edges of narrow Si lines. It is apparent that this small percentage for large dimension structures can become significant in narrow lines. Even though the extra Ni atoms bring an additional benefit for narrow gate lines, it can, however, become catastrophic for nanoscaled MOSFETs due to the severe lateral encroachment of NiSi towards the channel, especially for the fully depleted devices formed on SOI structure where the available Si is limited [17]. Electrical shorts and significant gate leakage of devices caused by the severe lateral encroachment of NiSi have been frequently reported in various papers [18, 19]. Therefore, the effective control of the lateral encroachment of NiSi is vital for the fabrication of NiSi S/D SB-MOSFETs formed on UTB-SOI substrates in this thesis work.

We have investigated many approaches in order to control the severe lateral encroachment of NiSi. One of those approaches is based on the control of Ni diffusion through the grain boundaries since the grain boundary diffusion of Ni has been reported to be indeed very rapid and significant [20]. The idea behind the following experiment setup is to control the grain boundary diffusion of Ni through strictly limiting the number of NiSi grains thus the density of grain boundaries in the nanowires. The width of nanowire channel is designed as 20 nm, since within such a narrow nanowire only one or few NiSi grains can be accommodated dependent on the grain size. In order to verify this idea quickly, a simplified process derived from STL process to fabricate test devices with nanowire channel, was developed as shown schematically in Fig. 4.3. Some processing details are worth noting. The thicknesses of TEOS supporting layer and α-Si are 40 and 20 nm, respectively. That is to say, the height and width of α-Si nanowire channel are 40 and 20 nm accordingly. The SiNx “fake gate” is 15-nm in thickness and the gate length varies from 0.3 to 50 μm. Moreover, the thickness of Ni for SALICIDE is 20 nm, which is sufficient to consume all Si exposed to Ni in the α-Si nanowire. Ni SALICIDE process is carried out at 500 oC/30 s. HR-SEM micrographs of a test device of “fake gate” length Lg=0.3 μm fabricated by this simplified STL process are shown in Fig. 4.4.

Chapter 4. SB-MOSFETs: Fabrication and Characterization

Cross-section Top-view

(a) (a) Starting layer stack with Si

substrate, SiO2, SiNx and TEOS supporting layer.

(b) (b) Pattern and etch TEOS to form sidewall support.

(d) (d) Pattern contacting leads and pads and anisotropic etch to form rectangular α-Si nanowire rings supported by TEOS.

(e) (e) Deposit 15-nm-thick SiNx and pattern “fake SiNx gate” with an additional mask, and then perform Ni SALICIDE process.

Fig. 4.3. Schematic presentation of a simplified STL process to fabricate test devices with a nanowire channel of 20 nm in width.

Integration of metallic source/drain contacts in MOSFET technology

Contacting pad TEOS supporting layer

SiNx Contacting pad

NiSi nanowire

Fake gate

Fig. 4.4. HR-SEM micrographs of a test device with nanowire channels of 20 nm in width

fabricated by a simplified STL process in this thesis. The “fake SiNx gate” length is 0.3 μm.

By putting probes on two contacting pads in Fig. 4.4, a simple I-V characterization was performed for the devices of “fake gate” length Lg=0.3 μm. If the nanowire devices were shorted as a result of severe lateral encroachment of NiSi, the I-V characteristics should be linear giving rise to a finite resistance, otherwise infinite resistance for non-shorted devices. Unfortunately, an electrical mapping of 50 devices showed that all of them were shorted electrically. Hence, it can be concluded that the idea by limiting the grain boundary diffusion did not work; there could be other diffusion paths for Ni that led to severe lateral encroachment of NiSi even for nanowires of 20 nm in width.

Apart from this failed approach, other three different Ni SALICIDE schemes were also employed in order to control the lateral encroachment of NiSi in this thesis work. These schemes were: (i) thickness control of Ni (tNi), (ii) Ni-Pt alloying, (iii) two-step annealing

Chapter 4. SB-MOSFETs: Fabrication and Characterization

with reference to Paper V. It must be pointed out that all these three schemes were conducted with real UTB-SOI (tSi=20 nm) devices of poly-Si gate length Lg=55 nm as shown in Fig. 4.5, instead of on test devices as shown in Fig. 4.4. Wafers with fabricated devices were sliced into a lot of pieces to test these four different Ni SALICIDE schemes which will be discussed briefly below.

(a) (b) Source pad (tSi=20 nm)

Poly-Si nanowire Poly-Si gate pad

Drain pad (tSi=20 nm)

Fig. 4.5. (a) top-view SEM image of a UTB-SOI SB-MOSFET with measurement pads, (b) the enlarged SEM image showing the gate length is 55 nm.

(i) Ni thickness control. The pieces were loaded into a sputter deposition chamber for a series of Ni depositions to different thicknesses tNi=3, 5, 6, 7, 10, and 15 nm calibrated using Rutherford backscattering spectroscopy (RBS). This was followed by annealing at 500 oC for 10 s in a rapid thermal processing (RTP) chamber. The unreacted Ni was removed in the o mixture of H2SO4 and H2O2 solution (Piranha) at 120 C for 10 min.

(ii) Two-step annealing. For this series of small pieces, a 10-nm-thick Ni film was sputter deposited. Immediately after the deposition, the 1st annealing was performed in situ in the deposition chamber without breaking the vacuum, at 100, 150, 200, 250 and 300 oC all for 1 min. After the un-reacted Ni was removed in Piranha, the 2nd annealing was carried out at 500 oC for 10 s to transform the metal-rich Ni-silicide phase to NiSi. For comparison, some samples only underwent the 1st annealing.

(iii) Ni1-xPtx alloys. Here, the Ni1-xPtx alloy films sputter deposited on the small pieces were all 10 nm, but of three different compositions with x=0.05, 0.15 and 0.3. The alloy

Integration of metallic source/drain contacts in MOSFET technology

thickness and composition were also calibrated using RBS. The annealing was again carried out in the RTP chamber at 500 oC for 10 s. The removal of un-reacted Ni-Pt alloys was performed by combining the Piranha solution for 10 min and then in diluted aqua regia o (4H2O:3HNO3:1HCl) at 75 C for 40 s.

As seen in Fig. 4.5 (a), after the SALICIDE process, the devices could be evaluated electrically at the silicide level by placing three probes on source, drain and gate pads. This measurement provided a qualitative assessment of the silicide lateral encroachment by counting the number of devices that became electrical short between the source and drain electrodes.

All these three Ni SALICIDE schemes can give rise to an effective control of lateral encroachment during Ni-silicidation. More experimental results of the first three schemes are shown in Paper V and VII.

Chapter 4. SB-MOSFETs: Fabrication and Characterization

4.1.3 SBH modification of NiSi

One of the key parameters with a SB-MOSFET is the SBH of the SB S/D junction. The sum of electrons SBH (φbn) and holes SBH (φbp) should approximately be equal to the energy bandgap of Si (Eg), i.e., φbn+φbp≈Eg. At “on-state”, a low SBH for electrons/holes at the source terminal is required to improve carrier injection. At “off-state”, the SBH for holes/electrons is thus high yielding low Ioff. Theoretical studies have revealed that an extremely low SBH as ∼0.1 eV is required for SB-MOSFETs to outperform conventional MOSFETs with p-n junctions of heavily doped S/D [21, 22]. However, due to the Fermi-level pinning, the SBHs of most silicides are large either for electrons or for holes. As a result, both n-and p-type SB-MOSFETs with intrinsic Schottky S/D usually suffer from the low drive current and a large leakage attributed to the drain-to-substrate reverse-biased current [23]. Furthermore, for the ease of CMOS fabrication, the single silicide for both n- and p-type SB- MOSFETs is highly desired. Since no single silicide can meet the low SBHs for both conduction polarities, complementary silicides, e.g., ErSix or YbSix for n-type SB-MOSFETs [24,25] and PtSi for p-type SB-MOSFETs [26,27], have been investigated in despite of the processing complexity. In this thesis work, NiSi was chosen for the fabrication of both n- and p-type SB-MOSFETs. However, as its work-function lies close to the middle of the Si bandgap, the NiSi/Si contact is characterized by a large SBH to both electrons and holes resulting in degraded drive current of the SB-MOSFETs. The SBH engineering was thus needed for NiSi S/D SB-MOSFETs. In chapter 3, we have adopted SADS scheme to modify the SBH of NiSi and both φbn and φbp have been successfully tuned to ∼0.1-0.2 eV, which paves the way towards the high performance NiSi S/D SB-MOSFETs in this chapter.

4.2 NiSi integration with Si technology

Even though the three major issues in section 4.1 have been solved for the NiSi integration in SB-MOSFETs, the capability of NiSi with standard Si processing is also essential, since NiSi films will be exposed to ion implantation (I/I) and various chemicals during devices fabrication at KTH. In this section, we will deal with these capability issues of NiSi with standard Si processing at KTH.

Integration of metallic source/drain contacts in MOSFET technology

4.2.1 Ion implantation damage and recovery

As we adopt SADS scheme to induce DS thus tuning SBHs of NiSi (in Chapter 3), B and As are implanted into as-formed NiSi thin films. The NiSi thin films are then severely damaged by ion bombardment. The degree of damage depends on ion mass as well as implantation dose and energy. Subsequent drive-in annealing to induce the DS at NiSi/Si interface will lead to a substantial structural recovery of NiSi films. The sheet resistance (Rsh) variation of as-formed Ni-silicide films implanted by 1×1015 cm-2 B with drive-in annealing temperature is illustrated in Fig. 4.6.

5 nm NiSi + 1E15 cm-2 B I/I 2-y -2

) 11 nm NiSi+ 1E15 cm B I/I 16 nm NiSi+ 1E15 cm-2 B I/I -2

/sqr. 22 nm NiSi+ 1E15 cm B I/I Ω ( 100

sheet resistance 10

As400 I/I 450 500 550 600 650 700 750 800 Drive-in annealing temperature ( oC)

Fig. 4.6. Variation in sheet resistance of Ni-silicide films after B I/I with drive-in annealing temperature. For thicker Ni-silicide films, i.e., 11-22 nm, NiSi is identified.

For the ultrathin Ni-silicide film, i.e., 5 nm, NiSi2-y is identified [28].

As seen, Rsh of all Ni silicide films after I/I (as I/I) increase by a magnitude of 2-3 times as a o result of the damage caused by B I/I. Upon drive-in annealing at 450 to 800 C, Rsh first decreases due to the structural recovery of films and then increase because of the agglomeration at high temperature. For Ni silicide films of 11-22 nm thick, polycrystalline NiSi was identified in Paper III. The drive-in annealing behavior of them is quite similar to that for NiSi films during silicidation annealing. That is to say, Rsh starts to increase above 500 oC drive-in annealing temperature and this occurs at lower temperature for thinner films, i.e., 700 and 600 oC for NiSi films of 22 and 11 nm thick respectively. For the extremely thin

Chapter 4. SB-MOSFETs: Fabrication and Characterization

Ni silicide film of ~5 nm thick, surface-energy triggered formation of epitaxial NiSi2-y was concluded in Paper III. The drive-in annealing behavior of it is also similar to that for NiSi2-y film during silicidation annealing. The extraordinary morphological stability of NiSi2-y film with drive-in annealing temperature benefits from the formation of epitaxial NiSi2-y. In this thesis, we use the Ni SALICIDE scheme (i) in section 4.1, i.e., tNi=5 nm, to control the lateral encroachment of NiSi during the fabrication of NiSi S/D SB-MOSFETs, the resulted thickness of NiSi is 11 nm. Hence, the optimized drive-in annealing temperature is 550 oC after ion implantation according to Fig. 4.6.

4.2.2 Etching of NiSi

In the standard Si processing and the device fabrication flow at KTH, NiSi is usually covered by a layer of LTO after Ni SALICIDE process. A mask is then employed to define small contacting holes followed by anisotropic dry-etching to open them. NiSi is thus exposed to dry-etching chemicals, typically CHF3-CF4-Ar plasma at KTH. An excellent etching resistance of NiSi films to dry-etching plasma is important since too much NiSi thickness loss is undesired. The NiSi thickness loss vs. dry-etching time in the CHF3-CF4-Ar plasma is shown in Fig. 4.7. As shown, the etch rate is very slow indicating the excellent resistance of NiSi to this etch.

22 CHF :CF :Ar= 15sccm:5sccm:50sccm 3 4 20 350W, 150mT SiO dry etch recipe 18 2 16 14 12

10 8 6 4 NiSi thickness loss (Angstrom) 2 0 0 102030405060 Dry etch time (s)

Fig. 4.7. NiSi thickness loss vs. etch time using SiO dry-etch recipe. 2

Integration of metallic source/drain contacts in MOSFET technology

According to our previous experience, the CHF3-CF4-Ar plasma should, however, never see NiSi films otherwise the contact resistivity between Al/TiW and NiSi would increase significantly or at least show a large variation within a wafer. In order to circumvent this problem, a delicate dry-etching recipe has been developed to etch most LTO and deliberately leave a thin layer of LTO in the contacting holes untouched, as shown in Fig. 4.8(a). The remaining LTO layer is then removed in 1% HF solution. The etching time is usually 1∼2 min to make sure that all LTO is removed in the small contacting holes. Therefore, it is necessary to determine the etch rate of NiSi in 1% HF solution as well. Fig. 4.8(b) depicts the NiSi thickness loss vs. etch time in 1% HF solution. More specifically, in this thesis, since NiSi films undergo I/I and subsequent drive-in annealing to modify the SBHs, the etch rate for them is also shown in Fig. 4.8(b). Although NiSi films with I/I recover after drive-in annealing, the etch rate of them is still larger than that of NiSi films without I/I. After 1 min, the NiSi thickness losses reach 7 and 10 nm for NiSi without and with I/I, respectively, which are affordable for thicker NiSi films [29] but definitely not for thinner ones. For NiSi S/D SB-MOSFETs formed on UTB-SOI substrates with resulting ultrathin NiSi films in this thesis, too much NiSi thickness loss in 1% HF is unbearable which is required to be minimized.

(a) (b)

Contact hole 1E15 cm-2 B I/I+500 oC/30 s drive-in annelaing 100 Without B I/I NiSi SiO2 80

40 2000 Å 20 NiSi lossthickness (Angstrom) 0 100 Å 0 102030405060 1% HF etch time (s)

Fig. 4.8. (a) a schematic presentation of the contact hole structure, and (b) NiSi thickness loss vs. etch time in 1% HF solution.

Chapter 4. SB-MOSFETs: Fabrication and Characterization

4.2.3 SiNx-SiO2 double layer

In the previous section, since the exact thickness of LTO remaining after dry-etching in small contacting holes is unknown, the etch time in 1% HF is uncertain. Therefore, adequate over- etch time is needed to guarantee the clearance of LTO, which unfortunately results in too much NiSi thickness loss. This problem can be solved by using a SiNx/SiO2 double layer structure as shown in Fig. 4.9. The thickness of SiO2 and SiNx is 20 nm and 80 nm, respectively, both deposited by PECVD. After defining small contacting holes, SiNx layer is anisotropically etched through and the dry etching stops at SiO2 layer by endpoint control automatically. Hence, the remaining PECVD SiO2 layer in the contacting holes is approximately 200 Å, which can be removed by 1% HF within a very short time, i.e., 25 s, as a result of the fast etching of PECVD SiO2 in 1% HF. If by any chance, there is still some over-etching of NiSi, the thickness loss is actually very limited within such a short time. In this thesis work, this double layer structure is adopted, and the contact resistivity between TiW/Al and NiSi, as low as 2×10-8 Ω-cm2, was achieved.

NiSi SiO2

SiNx

800 Å

200 Å 100 Å

Fig. 4.9. A schematic presentation of a SiNx/SiO2 double layer structure in order to minimize the NiSi thickness loss in 1% HF solution.

Integration of metallic source/drain contacts in MOSFET technology

4.3 SB-MOSFETs on UTB-SOI

After resolving numerous processing issues and problems, the final NiSi S/D SB- MOSFETs are successfully demonstrated:

Thinning SOI to 20-nm thick

Formation of MESA structure 3-nm-thick gate oxide growth and 100-nm-thick IDP poly-Si deposition

Defining nanoscaled gate of Lg=55 nm by STL process

Formation of 15-nm-thick SiO /Si N slim spacers 2 3 4 o Ni SALICIDE process (500 C)

As I/I into as-formed NiSi for n-type devices: dose 1×1015 cm-2

B I/I into as-formed NiSi for p-type devices: dose 1×1015 cm-2

o Drive-in annealing at 550 C/2 min

PECVD SiO2/SiNx deposition and contact hole

Al/TiW metallization

Forming-gas annealing

Fig. 4.10. Process flow for the fabrication of NiSi S/D SB-MOSFETs in this thesis.

The major process steps for the process flow to fabricate NiSi S/D SB-MOSFETs on UTB-SOI substrates are summarized in Fig. 4.10. Lightly doped p-type SOI wafers with a 150-nm-thick Si on top of a 400-nm-thick buried oxide (BOX) were used as the starting material. The surface Si was thinned down to about 20 nm by several cycles of thermal oxidation and subsequent SiO2 removal in dilute HF solution. After definition of isolated active areas in the ultrathin Si, a 3-nm-thick gate oxide was grown by means of dry oxidation at 750 oC. This was followed by the deposition of a 120-nm-thick in situ phosphorous doped poly-Si as the gate electrode material. An I-line stepper was employed to define gate lengths

Chapter 4. SB-MOSFETs: Fabrication and Characterization

Lg≥0.3 μm. The improved STL technology was used to fabricate devices of Lg=55 nm [10-

12]. Slim gate spacers composed of a 5-nm-thick SiO2 and a 10-nm-thick Si3N4 were formed in order to make it easy for control of NiSi lateral growth. Careful control of Ni SALICIDE o process was performed by controlling tNi=5 nm at 500 C/10 s. Boron and As were then implanted into the NiSi for the p- and n-MOSFETs, respectively, both to a dose of 1x1015 cm- 2. The implantation energy was 1 keV for B and 2 keV for As. Drive-in annealing was carried out in the rapid thermal processing (RTP) chamber at 550 oC for 2 min resulting in B and As DS at the NiSi/Si interface. Control devices without dopant implantation were also processed. The device fabrication was completed with Al metallization followed by forming gas annealing at 400 oC for 30 min. The cross-sectional HR-TEM micrograph of a fabricated NiSi S/D SB-MOSFET is shown in Fig. 4.11.

NiSi Gate oxide Poly-Si NiSi NiSi

Si channel

BOX

Fig. 4.11. Cross-sectional TEM micrograph of the central part of a fabricated NiSi S/D

SB-MOSFET with a 55 nm-gate defined by means of the improved STL technology.

Integration of metallic source/drain contacts in MOSFET technology

In Paper V, a systematic investigation of different Ni SALICIDE schemes towards a controllable NiSi-based metallic S/D SB-MOSFETs is presented. As and B dopant segregation by means of SADS at drive-in annealing temperature 550 oC was found efficient for both polarities of devices of Lg=55 nm, as shown in Fig. 4.12. As seen from the Ids-Vg plots [Fig. 4.12(a) and 4.12(c)], both devices with dopant segregation show typical n- and p- type MOSFETs behaviors compared to the ambipolar behavior of devices without dopant segregation. The SB-MOSFETs characteristics of both n- and p-type devices are obviously observed by the exponential behavior of Ids-Vds plots [Fig. 4.12(b) and 4.12(d)].

3 10 SS=164 mV/dec 1000 2 V from 0 to 3 V, step=0.5 V 10 (a) (b) g 101 V =1.2 V d c 800

0 e ) ) 10 d / -1 m m V 10 μ μ m 600 -2 10 6 A/ A/

2 μ -3 (a)

μ 1 (

( 10 = 400 -4 S ds I ds 10 S I -5 10 V =0.1 V -6 d 200 10 As DS 10-7 No As DS 10-8 0 -2 -1 0 1 2 0.0 0.5 1.0 1.5 2.0 V (V) V (V) G ds

2 V from 0 to -2.5 V, step=-0.5 V 10 (c) 600 g (d) 1 SS=175 mV/dec 10 S ) 0 S 500 10 = m 1 ) -1 3 V =-1.2 V μ d 10 4 m -2 m 400 μ A/ 10 V μ -3 / A/ (

e μ 300 c -4 ( ds

I 10

-5 ds

I 200 10 V =-0.1 V 10-6 d -7 100 10 with B DS -8 10 No B DS 0 -2 -1 0 1 2 -2.0 -1.5 -1.0 -0.5 0.0 V (V) V (V) G ds

Fig. 4.12.Transfer Ids-Vg characteristics for NiSi S/D SB-MOSFETs of Lg=55 nm with and without DS, for (a) n-type and (b) p-type devices. Their corresponding Ids-Vds output characteristics are shown in (b) and (d) respectively.

Chapter 4. SB-MOSFETs: Fabrication and Characterization

However, the device design is not optimized in this thesis due to the equipment limitation. This non-optimized device design not only has led to severe short channel effects, but also has resulted in relatively low drive current (Ion) and large subthreshold slope as showing in Fig. 4.12. In order to further improve the device performance, a high-k gate dielectric with much smaller effective oxide thickness is required. Moreover, the large source and drain series resistance (RSD) also lead to low Ion. In Fig. 4.13, the total resistance (RTOT) versus Lg is shown. A linear fitting can be made and extrapolated to Lg=0 in order to get RSD for both devices with As (Fig. 4.13a) and B DS. RSD of n- and p-type devices are ∼1.8 and ∼3 kΩ⋅μm respectively. RSD consists of TiW/NiSi contact resistance (RC), sheet resistance of NiSi

(RNiSi), and Schottky barrier resistance (RSB). Based on the results of RC and RNiSi obtained from the test structures, RSB is the dominating factor accounting for 80-90 % of RSD. The still large SBHs are probably the reason for the high RSB since the drive-in annealing temperature is rather low in this thesis.

16 As DS B DS 6 NiSi S/D SB-MOSFETs 14 NiSi S/D SB-MOSFETs ) )

m 12 m Ωμ

Ωμ 10 k 4

k (

( 8 TOT TOT R

R 6 2 4

0 200 400 600 800 1000 2 L (nm) 0 200 400 600 800 1000 g L (nm) g

Fig. 4.13. RTOT versus Lg for (a) n-type with As Ds and (b) p-type with B DS NiSi S/D SB-MOSFETs. |Vd|=100 mV, VG=VT±1.5 V for n- and p-type devices respectively.

Integration of metallic source/drain contacts in MOSFET technology

In Table I, a compilation of NiSi S/D SB-MOSFETs is summarized. According to this table, gate-all-around or FinFET combines with DS should be introduced to control the SCEs and improve the devices performance.

Table I. A complilation of device performance of NiSi S/D SB-MOSFETs. FH: Fin height; FW: Fin width; NW: Nanowire.

L t V I I SS DIBL S/D Channel g ox d on off I /I Ref. (nm) (nm) (V) (μA/μm) (μA/μm) on off (mV/dec) (mV/V) N- nanowire SBNWM NiSi 90 9 1.2 399 5.2 x10-3 2.3x105 ∼60 13 ∼6 nm OS [30] P- nanowire SBNWM NiSi 90 9 -1.2 513 5.2 x10-3 1.5x105 ∼60 10 ∼6 nm OS FinFET, FH N- NiSi =50nm, 15 1.3 1 1000 5x10-2 2x104 ∼65 - SBMOS DS FW=15 nm [31] FinFET, FH P- NiSi =50nm, 15 1.3 -1 500 8x10-2 6.3x103 ∼80 - SBMOS DS FW=15 nm FinFET, FH N- NiSi =40nm, 49 4 1 167 8.4x10-6 2x107 94 - SBMOS DS FW=60 nm [32] FinFET, FH P- NiSi =40nm, 49 4 -1 84 1.7x10-7 5x108 71 - SBMOS DS FW=60 nm P- NiSi nanowire SBNWM 50 6 -1 319 ∼10-4 ∼105 ∼90 - [33] DS ∼10 nm OS UTB- N- NiSi SOI 55 3 1.2 342 9.8x10-3 3.5x104 164 251 SBMOS DS tsi=20 nm this UTB- work P- NiSi SOI 55 3 -1.2 204 8.7x10-3 2.3x104 175 243 SBMOS DS tsi=20 nm

Chapter 4. SB-MOSFETs: Fabrication and Characterization

4.4 SB-FinFETs fabrication

In this thesis, motivated by the successful demonstration of SB-MOSFETs on UTB-SOI substrate, the fabrication of SB-FinFET was also carried out. The process for fabricating SB- FinFETs is rather similar to that for SB-MOSFETs on UTB-SOI substrate, except using the STL technology twice, i.e., the first one for the definition of the Fin and the second one for the definition of the gates. In addition, the NiSi S/D is replaced by PtSi S/D. The schematic presentation of fabricating SB-FinFET is skipped in this section. Since p-type SB-FinFET was successfully fabricated in [34] at KTH, this section will deal with the fabrication of n- type SB-FinFET. As was implanted into as-formed PtSi films and then followed by 700 oC/30 s drive-in annealing to induce DS. Control samples without As DS were also processed at the same time. In Fig. 4.14(a), a HR-SEM micrograph of fabricated SB-FinFET is shown along with an enlarged micrograph of both Fin and gate in Fig. 4.14(b). As seen, the fabricated device has two Fins (channel) in parallel. The cross-sectional TEM micrograph of the channel-Fin structure is shown in Fig. 4.14(c) and (d) along A-A’ and B-B’ directions respectively. From the SEM and TEM pictures, the following data regarding FinFET in this thesis are obtained: the gate length is about 90 nm, the dimension of Fin are 25 nm in width and 30 nm in height respectively.

The As DS is found to be very effective for n-type SB-FinFET compared to the devices without As DS. Devices without DS show a typical p-type SB-FinFET behavior due to a small SBH of PtSi to holes. With As DS, the typical n-type characteristics for both SB- FinFET and SB-MOSFET on UTB-SOI substrate are achieved. Moreover, the SB-FinFET shows a better control of SCE in comparison with SB-MOSFET on UTB-SOI as expected. Regarding to more detailed results, they are shown in Paper VI. In Paper VII, an overview of metallic source/drain (MSD) Schottky-barrier (SB) MOSFET technology is provided. This technology offers several benefits for scaling CMOS, i.e., extremely low S/D series resistance, sharp junctions from S/D to channel and low temperature processing. A successful implementation of this technology needs to overcome new obstacles such as Schottky barrier height (SBH) engineering and careful control of SALICIDE process. Device design factors such as S/D to gate underlap, Si film thickness and oxide thickness affect devices performance owing to their effects on the SB width. Recently, we have invested a lot of efforts on Pt- and Ni-silicide MSD SB-MOSFETs and achieved some promising results in Paper V, VI and VII.

Integration of metallic source/drain contacts in MOSFET technology

Poly-gate (a) (b) Poly-gate A Si-Fin B

Si-Fins

B’ A’

(d) (c)

B B’

A A’

Fig. 4.14. (a) and (b) Top-view micrographs of a fabricated SB-FinFET. Cross- sectional TEM micrographs of (c) the Fin-channel underneath the gate, and (d) Extended Fin-channel nanowire.

Chapter 4. SB-MOSFETs: Fabrication and Characterization

References 1. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C. Yang, C. Tabery, C. Ho, Q. Xiang, T.- J. King, J. Bokor, C. Hu, M. Lin, D. Kyser, “FinFET scaling to 10 nm gate length,” IEDM Tech. Dig., pp. 251-254, 2002. 2. K. Ishimaru, “45 nm/32 nm CMOS-Challenge and perspective,” Solid-state electronics,vol. 52, no. 9, pp. 1266-1273. 3. B. Tsui, and C. Lin, “A novel 25-nm modified Schottky-barrier FinFET with high performance,” IEEE Electron device Lett., vol. 25, no.6, pp. 430-432, 2004. 4. D. Hisamoto, W. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, C. Hu, “FinFET-a self-aligned double-gate MOSFET scalable to 20 nm,” IEEE Trans. Electron Devices, vol. 47, no. 12, pp.2320-2325, 2000. 5. A. Kaneko, A. Yagishita, K. Yahashi, T. Kubota, M. Omura, K. Matsuo, I. Mizushima, K. Okano, H. Kawasaki, S. Inaba, T. Izumida, T. Kanemura, N. Aoki, K. Ishimaru, H. Ishiuchi, K. Suguro, K. Eguchi, Y. Tsunashima, “Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15 nm FinFET with elevated source/drain extension,” IEDM Tech. Dig., pp. 844-847, 2005. 6. Y. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King, J. Bokor and C. Hu, ”Sub-20 nm CMOS FinFET technologies, ” IEDM Tech. Dig., pp. 421-424, 2001. 7. Y. Choi, L. Chang, P. Ranade, J. Lee, D. Ha, S. Balasubramanian, A. Agarwal, M. Ameen, T.-J. King, and J. Bokor, “FinFET process refinement for improved mobility and gate work function engineering,” IEDM Tech. Dig., pp. 259-262, 2002. 8. Y. Choi, T.-J. King, and C. Hu, “Nanoscale CMOS spacer FinFET for the terabit era,” IEEE Electron device Lett., vol. 23, no. 1, pp. 25-27, 2002. 9. W. Xiong, G. Gebara, J. Zaman, M. Gostkowski, B. Nguyen, G. Smith, D. Lewis, C. Cleavelin, R. Wise, S. Yu, M. Pas, T.-J. King, and J. Colinge, “Improvement of FinFET electrical characteristics by hydrogen annealing,” IEEE Electron device Lett., vol. 25, no. 8, pp. 541-543, 2004. 10. Z. Zhang, P.-E. Hellström, J. Lu, M. Östling and S.-L. Zhang, ”A novel self-aligned process for platinum silicide nanowires,” Microelectronics Eng., vol. 83, no. 11-12, pp. 2107-2111, 2006. 11. J. Hållstedt, P.-E. Hellström, Z. Zhang, B. G. Malm, J. Edholm, J. Lu, S.-L. Zhang, H. H. Radamson, and M. Östling, “a robust spacer gate process for deca-nanometer high- frequency MOSFETs,” Microelectronics Eng.,vol. 83, no. 3, pp. 434-439, 2006.

Integration of metallic source/drain contacts in MOSFET technology

12. V. Gudmundsson, P.-E. Hellström, J. Luo, J. Lu, S.-L. Zhang, and M. Östling, ”Fully depleted UTB and trigate N-channel MOSFETs featuring low-temperature PtSi Schottky-barrier contacts with dopant segregation,” IEEE Electron device Lett., vol. 30, no. 5, pp. 541-543, 2009. 13. J. P. Lu, D. Miles, J. Zhao, A. Gurba, Y. Xu, C. Lin, M. Hewson, J. Ruan, L. Tsung, R. Kuan, T. Grider, D. Mercer, and C. Montgomery, “A novel nicke SALICIDE process technology for CMOS devices with sub-40 nm physical gate length,” IEDM Tech. Dig., pp. 371-374, 2002. 14. Q. Xiang, C. Woo, E. Paton, J. Foster, B. Yu, and M. R. Lin, “Deep sub-100 nm CMOS with ultra low gate sheet resistance by NiSi,” in VLSI Tech. Dig., 2000, pp. 76–77. 15. R. Chau, J. Kavalieros, B. Doyle, A. Muthy, N. Paulsen, D. Lionberger, D. Barlage, R. Arghavani, B. Roberds and M. Doczy, “A 50 nm depleted-substrate CMOS transistor (DST),” in VLSI Tech. Dig., 2001, pp. 621–624. 16. H. Iwai, T. Ohguro, S.-I. Ohmi, “NiSi silicide technology for scaled CMOS,” Microelectronics Eng., vol. 60, no. 1-2, pp. 157-169, 2002. 17. J. Seger, P.-E. Hellström, J. Lu, B. G. Malm, M.von. Haartman, M. Östling, and S.-L. Zhang, “Lateral encroachment of Ni-silicides in the source/drain regions on ultrathin silicon-on-insulator,” Appl. Phys. Lett., vol. 86, no. 25, pp. 253507/1-3, Jun. 2005. 18. T. Yamaguchi, K. Kashihara, T. Okudaira, T. Tsutsumi, K. Maekawa, N. Murata, J. Tsuchimoto, K. Asai, and M. Yoneda, “Anomalous gate-edge leakage current in nMOSFETs caused by encroached growth of nickel silicide and its suppression by confinement of silicidation region using advanced Si+ ion-implantation technique,” IEEE Trans. Electron Devices, vol.56, no. 2, pp. 206-213, Feb. 2009. 19. T. Yamaguchi, K. Kashihara, S. Kudo, T. Okudaira, T. Tsutsumi, K. Maekawa, K. Asai, and M. Kojima, ”Anomalous nickel silicide encroachment in n-cahnnel metal-oxide- semiconductor field-effect transistors on Si (110) substrates and its suppression by Si+ ion-implantation technique,” Jpn, J. Appl. Phys., vol. 48, pp. 066513-1-066513-6, 2009. 20. J. C. Ciccariello, S. Poize, and P. Gas, “Lattice and grain boundary self-diffusion in Ni2Si: comparison with thin-film formation,” J. Appl. Phys., vol. 67, no. 7, pp. 3315- 3322, 1990. 21. S. Xiong, T. J. King, and J. Bokor, “A comparison study of symmetric ultrathinbody double-gate devices with metal S/D and doped S/D,” IEEE Trans. Electron Devices, vol.52, no. 8, pp. 1859-1867, 2005.

Chapter 4. SB-MOSFETs: Fabrication and Characterization

22. M. Ieong, P. M. Solomon, S. E. Laux, H. P. Wong and D. Chidambarrao, “Comparison of raised and Schottky source/drain MOSFETs using a novel tunneling contact model,” IEDM Tech. Dig., pp. 3733-736, 1998. 23. R. A. Vega, “On the modeling and design of Schottky field-effect transistors,” IEEE Trans. Electron Devices, vol.53, no. 4, pp. 866-874, 2006. 24. J .Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T.-J. King, C. M. Hu, ”Complementary silicide source/drain thin-body MOSFET for the 20 nm gate length regime,” IEDM Tech. Dig., pp. 57-60, 2000. 25. M. Jang, Y. Kim, J. Shin, S. Lee, and K. Park, “A 50-nm-gate-length erbium-silicided n- type Schottky barrier metal-oxide-semiconductor field-effect transistor,” Appl. Phys. Lett., vol. 84, no. 5, pp. 741-743, 2004. 26. J. P. Snyder, C. R. Helms, and Y. Nishi,”Experimental investigation of a PtSi source and drain field emission transistor,” Appl. Phys. Lett., vol. 67, no. 10, pp. 1420-1422, 1995. 27. Z. Zhang, Z.-J. Qiu, P.-E. Hellström, G. Malm, J. Olsson, J. Lu, M. Östling, and S.-L. Zhang, ”SB-MOSFETs in UTB-SOI featuring PtSi source/drain with dopant segregation,” IEEE Electron device Lett., vol. 29, no. 1, pp. 125-127, 2008. 28. J. Luo, Z. J. Qiu, C. L. Zha, Z. Zhang, D. P. Wu, J. Lu, J. Åkerman, M. Östling, L. Hultman, and S.-L. Zhang, ”Surface-energy triggered phase formation and epitaxy in nanometer-thick Ni1-xPtx silicide films,” Appl. Phys. Lett., vol. 96, no. 3, pp. 031911-1- 031911-3, 2010. 29. J. Seger, “Interaction of Ni with SiGe for electrical contacts in CMOS technology,” Phd thesis, pp. 37-38, Stockholm, 2005. 30. E. J. Tan, K. L. Pey, N. Singh, G. Q. Lo, D. Z. Chi, Y. K. Chin, L. J. Tang, P. S. Lee, C. K. F. Ho, “Nickel-silicide Schottky junction CMOS transistors with gate-all-around nanowire channels,” IEEE Electron device Lett., vol. 29, no. 8, pp. 902-905, 2008. 31. A. Kaneko, A. Yagishita, K. Kubota, M. Omura, K. Matsuo, I. Mizushima, K. Okano, H. Kawasaki, T. Izumida, T. Kanemura, N. Aoki, A. Kinoshita, J. Koga, S. Inaba, K. Ishimaru, Y. Toyoshima, H. Ishiuchi, K. Suguro, K. Eguchi, and Y. Tsunashima, “High- performance FinFET with dopant-segregated Schottky source/drain,” IEDM Tech. Dig., pp. 893-896, 2006. 32. C. P. Lin and B. Y. Tsui, “Characteristics of modified-Schottky-barrier (MSB) FinFETs,” in proc. VLSI-TSA, pp. 118-119, 2005.

Integration of metallic source/drain contacts in MOSFET technology

33. Y. K. Chin, K.L. Pey, N. Singh, G. Q. Lo, K. H. Tan, C.Y. Ong, and L. H. Tan, “Dopant segregated Schottky silicon-nanowire MOSFETs with gate-all-around channels,” IEEE Electron device Lett., vol. 30, no. 8, pp. 843-845, 2009. 34. Z. Zhang, J. Lu, Z. J. Qiu, P.-E. Hellström, M. Östling, S.-L. Zhang, ”Performance fluctuation of FinFETs with Schottky barrier source/drain,” IEEE Electron device Lett., vol. 29, no. 5, pp. 506-508, 2008.

Chapter 5. Summary, Conclusions and Future Perspective

As the CMOS devices are aggressively downscaled to sub-30 nanometers technology nodes, new materials and device architectures are required in order to control the ever deteriorating short channel effects and improve devices performance. The Schottky barrier source/drain contact technology has been discussed as the most promising solution to reducing the parasitic series source/drain resistance thus boosting the device performance. The present thesis has a focus on examining the technological challenges towards the integration of PtSi and NiSi source/drain in SB-MOSFETs. For this purpose, the sidewall transfer lithography technology was used for routine fabrication of sub-60 nm nanowires in a controllable and reproducible manner. A controllable Ni SALICIDE process dedicated to the formation of NiSi metallic source/drain without severe lateral encroachment has been developed. The major results of this thesis work are summarized below:

An experimental study of dopant segregation at NiSi/Si interface has led to a substantial SBH modification. The present thesis explores dopant segregation using B and As for the NiSi/Si contact system. The effects of C and N implantation into Si substrate prior to the NiSi formation are examined, and it is found that the presence of C yields positive effects in helping reduce the effective SBH to 0.1-0.2 eV for both conduction polarities. The achieved results of low SBH for both polarities inspire the application of NiSi metallic source/drain into future CMOS technology. Moreover, through a systematic study of the

variation of ρc of the silicide/silicon interface induced by DS, the formation of interfacial dipole as the cause responsible for the modification of SBH have been confirmed.

The ultrathin Ni1-xPtx (x=0∼1) silicide films have been studied for perspective ultrathin SOI devices. It is found that Pt-silicide films of all thicknesses show normal behavior of morphological stability, i.e., thinner films start to agglomerate at lower temperatures as the resulting polycrystalline PtSi films always agglomerate at low temperatures for thinner films. Surprisingly, the Ni-silicide films exhibit two different morphological

stability characteristics depending on the deposited thickness of Ni (tNi). For tNi≥4 nm, polycrystalline NiSi films form and agglomerate at lower temperatures for thinner films

like PtSi films. However, for tNi<4 nm, epitaxially aligned Ni-silicide films readily grow and exhibit extraordinary morphological stability up to 800 oC. This extraordinary

Integration of metallic source/drain contacts in MOSFET technology

morphological stability of ultrathin Ni1-xPtx silicide films makes dopant segregation more scalable for SB-MOSFETs formed on ultrathin SOI substrates.

A simplified STL process has been developed to fabricate nanowire device with “fake gates”. This nanowire device with “fake gates” is used to verify the idea of controlling NiSi lateral encroachment by limiting the number of NiSi grains. Three different Ni SALICIDE schemes to control the lateral encroachment have been examined systematically and it is found that all these three schemes can lead to an effective control of lateral encroachment during Ni SALICIDE.

Finally, after solving numerous processing challenges with the integration of Ni1-xPtx

(x=0∼1) silicides in SB-MOSFETs, NiSi S/D SB-MOSFETs of Lg=55 nm formed on UTB-SOI substrates were successfully fabricated. Moreover, the SB-FinFETs featuring with PtSi S/D were also fabricated. Through DS with appropriate dopants using the SADS process, i.e., B for p-type SB-MOSFETs and As for n-type devices, both types of high-performance SB-MOSFETs and SB-FinFETs have been achieved in this thesis.

These achievements at KTH place Ni1-xPtx (x=0∼1) silicides SB-MOSFETs and SB- FinFET as competitive candidates for future CMOS technology

Whatever the future CMOS solutions may look like, source/drain contact issues will continue to pose challenges. Looking down the road, there is still much work to do after this thesis work. Two interesting topics deserve further investigation.

The scalability of DS is needed to be investigated in order to tune the SBHs of both NiSi and PtSi films of few nm thicknesses. Meanwhile, since the contacting is of utmost importance in future CMOS, decreasing specific contact resistivity by DS is an interesting topic to be studied.

Since the study on ultrathin Ni1-xPtx silicide films shows very interesting results, the

realization of NiSi2-y epitaxial source/drain SB-MOSFETs with DS is required to be investigated further on.