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MOSFET Technology Scaling, Leakage Current, and Other Topics Chapter 7 MOSFET Technology Scaling, Leakage Current and Other Topics 7.1 Technology Scaling Small is Beautiful YEAR 1992 1995 1997 1999 2001 2004 2007 2010 Technology 0.5 0.35 0.25 0.18 0.13 90 65 45 Generation µµµm µµµm µµµm µµµm µµµm nm nm nm • New technology node every three years or so. Defined by minimum metal line width. • All feature sizes, e.g. gate length, are ~70% of previous node. • Reduction of circuit size by 2 good for cost. Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-1 International Technology Roadmap for Semiconductors, 1999 Edition Year of Shipment 1999 2002 2005 2008 2011 2014 DRAM metal half pitch 180 130 100 70 50 35 (nm) MPU physical Lg (nm) 140 85 65 45 32 22 Tox (nm) 1.5-1.8 1.5-1.9 1-1.5 0.8-1.2 0.6-0.8 0.5-0.6 VDD 1.5-1.8 1.2-1.5 0.9-1.2 0.6-0.9 0.5-0.6 0.3-0.6 µµµ µµµ Ion,HP ( A/ m) 750/350 750/350 750/350 750/350 750/350 750/350 µµµ Ioff,HP (nA/ m) 5 10 20 40 60 160 µµµ µµµ Ion,LP ( A/ m) 490/230 490/230 490/230 490/230 490/230 490/230 µµµ Ioff,LP (pA/ m) 7 10 20 40 80 160 No known solutions •Vdd is reduced at each node to contain power consumption in spite of rising transistor density and frequency •Tox is reduced to raise I on for speed consideration Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-2 Excerpt of 2003 ITRS Scaling to 2016 Year of Production 2004 2007 2010 2013 2016 Technology Node (nm) 90 65 45 32 22 HP physical Lg (nm) 37 25 18 13 9 EOT(nm) (HP/LSTP) 1.2/2.1 0.9/1.6 0.7/1.3 0.6/1.1 0.5/1.0 Vdd (HP/LSTP) 1.2/1.2 1.1/1.1 1.1/1.0 1.0/0.9 0.9/0.8 Ion/W,HP (mA/mm) 1100 1510 1900 2050 2400 Ioff/W,HP (mA/mm) 0.05 0.07 0.1 0.3 0.5 Ion/W,LSTP (mA/mm) 440 510 760 880 860 Ioff/W,LSTP (mA/mm) 1e-5 1e-5 6e-5 8e-5 1e-4 • HP: High Performance Logic • LSTP: Low Standby Power Technology Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-3 7.2 Subthreshold Current • The leakage current that flows at V g<V t is called the subthreshold current. ) m µ Intel, T. Ghani et al., IEDM 2003 A/ 90nm technology. µ µ µ µ ( Gate length: 45nm for ds I NMOS, 50nm for PMOS Vgs • The current at Vgs =0 and Vds =Vdd is called Ioff. Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-4 ∝ • Subthreshold current ns (surface inversion carrier concentration) ∝ qϕs/kT • ns e ϕ S Ef Ef, Ec Vgs ϕ • s varies with V g through a capacitor network Vg dϕ C 1 s = oxe = Cox + η ψ dV g Coxe Cdep S C dep ϕ η In subthreshold, s = constant +V g/ Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-5 Subthreshold Leakage Current ϕ q(constant +V /η ) / kT qV /ηηηkT ∝ ∝ q s / kT ∝ gs ∝ gs Ids ns e e e ηηη V ∝ qV gs / kT G Ids e Cox ϕ s Cdep C η = 1 + dep Coxe ηηη • Subthreshold current changes 10x for ·60mV change in V g. Reminder: 60mV is (ln10)·kT/q •Subthreshold swing, S : the change in Vgs corresponding to 10x change in subthreshold current. S = ηηη·60mV, typically 80-100mV Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-6 Subthreshold Leakage Current • Practical definition of V t : the Vgs at which I ds = 100nA W/L W q ()V −V /ηkT W ()V −V / S => I (nA ) ≈ 100 e g t = 100 10 g t subthresho ld L L Log (I ds ) V =V ds dd W −−− V /S 100 W/L(nA) Ioff (nA) = 100 10 t L is determined only by V t and Ioff subthreshold swing. Vt Vgs Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-7 Subthreshold Swing (S) • Smaller S is desirable (lower Ioff for a given V t). Minimum possible value of S is 60mV/dec. ≈ Cdep ’ • How do we lower swing? S = 60 mV ⋅∆1+ « Coxe • Thinner Tox => larger Coxe • Lower substrate doping => smaller Cdep • Lower temperature • Limitations • Thinner Tox oxide breakdown reliability or oxide leakage current • Lower substrate doping doping is not a free parameter but set by V t. Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-8 7.3 V t Roll-off • Vt roll-off: V t decreases with decreasing L g. • It determines the minimum acceptable Lg because Ioff is too large if Vt becomes too small. K. Goto et al., (Fujitsu) IEDM 2003 65nm technology. EOT=1.2nm, Vdd =1V • Question: Why data is plotted against Lg, not L? Answer: L is difficult to measure. Lg is. Also, Lg is the quantity that manufacturing engineers can control directly. Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-9 Why Does V t Decrease with L? Potential Barrier Concept Long Channel Short Channel Vgs =0V Vgs =0V V =0V g Ec N+ Source Vds N+ Drain V =V Vg=V t gs t-long Vgs =V t-short ~0.2V • When L is small, smaller V g is needed to reduce the barrier to 0.2V, i.e. V t is smaller. •Vt roll-off is greater for shorter L Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-10 Energy-Band Diagram from Source to Drain • L dependence source/channel long channel barrier Vds short channel •V dependence ds log(I ds ) long channel Vds Vds =0 V =V Vds =Vdd ds dd short channel Vgs Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-11 Vt Roll-off -- Capacitance Network Model Vds helps Vgs to invert the surface, therefore Vgs Cd V = V − −V ⋅ t t long ds C T V oxe ox Coxe ds C = − ()+ ⋅ d Vt Vt −long Vds 4.0 n+ X C Wdep j oxe Cd Due to built-in potential between N - P-Sub channel and N + drain & source • 2-D Poisson Eq. solution shows that As the channel length is Cd is an exponential function of L. reduced, drain to channel − distance is reduced; = − ( + )⋅ L l/ d Vt Vt −long Vds 4.0 e therefore Cd increases ≈ 3 where ld Tox Wdep X j Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-12 Vertical dimensions (Tox , Wdep , Xj) must be scaled to support L reduction − = − ( + )⋅ L l/ d Vt Vt −long Vds 4.0 e ≈ 3 where ld Tox Wdep X j Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-13 7.4 Reducing the Gate Insulator Thickness and Toxe • Oxide thickness has been reduced over the years from 300nm to 1.2nm. • Why reduce oxide thickness? – Larger C ox to raise I on – Reduce subthreshold swing – Control V t roll-off • Thinner is better. However, if the oxide is too thin – Breakdown due to high electric field – Leakage current Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-14 Tunneling Leakage Current • For SiO 2 films thinner than 1.5nm, tunneling leakage current has become the limiting factor. • HfO 2 has several orders lower leakage for the same EOT. Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-15 Replacing SiO 2 with HfO 2---High-k Dielectric (After W. Tsai et al., IEDM’03) • HfO 2 has a relative dielectric constant (k) of ~24, six times large than that of SiO 2. • For the same EOT, the HfO 2 film presents a much thicker (albeit a lower) tunneling barrier to the electrons and holes. • Toxe can be further reduced by introducing metal-gate technology since the poly-depletion effect is eliminated. Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-16 Challenges of High-K Technology • The challenges of high-k dielectrics are – chemical reactions between them and the silicon substrate and gate, – lower surface mobility than the Si/SiO 2 system – too low a V t for P-channel MOSFET (as if there is positive charge in the high-k dielectric). • A thin SiO 2 interfacial layer may be inserted between Si-substrate and high-k film. Question: How can Tinv be reduced? (Answer is in Sec. 7.4 text) Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-17 7.5 How to Reduce Wdep •Wdep can be reduced by increasing Nsub qN 2ε 2φ 2ε 2φ = + φ + sub s B = + φ + s B Vt Vfb 2 B Vfb 2 B Cox Cox Wdep – If Nsub is increased, C ox should be increased in order to keep V t the same. –Wdep can be reduced in proportion to Tox . • Or use retrograde doping with very thin lightly doped surface layer – Also, less impurity scattering in the inversion layer => higher mobility Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-18 7.6 Shallow Junction Technology contact metal dielectric spacer gate oxide channel shallow junction N+ source or drain extension • The shallow junction extension helps to control V t roll-off. • Shallow junction and light doping combine to produce an undesirable parasitic resistance that reduces the precious I on. • Theoretically, metal S/D can be used as a very shallow “junction”.
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