Chapter 7 MOSFET Technology Scaling, Leakage Current and Other Topics 7.1 Technology Scaling Small is Beautiful

YEAR 1992 1995 1997 1999 2001 2004 2007 2010

Technology 0.5 0.35 0.25 0.18 0.13 90 65 45 Generation µµµm µµµm µµµm µµµm µµµm nm nm nm

• New technology node every three years or so. Defined by minimum metal line width. • All feature sizes, e.g. gate length, are ~70% of previous node. • Reduction of circuit size by 2 good for cost.

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-1 International Technology Roadmap for Semiconductors, 1999 Edition

Year of Shipment 1999 2002 2005 2008 2011 2014 DRAM metal half pitch 180 130 100 70 50 35 (nm)

MPU physical Lg (nm) 140 85 65 45 32 22

Tox (nm) 1.5-1.8 1.5-1.9 1-1.5 0.8-1.2 0.6-0.8 0.5-0.6

VDD 1.5-1.8 1.2-1.5 0.9-1.2 0.6-0.9 0.5-0.6 0.3-0.6 µµµ µµµ Ion,HP ( A/ m) 750/350 750/350 750/350 750/350 750/350 750/350 µµµ Ioff,HP (nA/ m) 5 10 20 40 60 160 µµµ µµµ Ion,LP ( A/ m) 490/230 490/230 490/230 490/230 490/230 490/230 µµµ Ioff,LP (pA/ m) 7 10 20 40 80 160

No known solutions

•Vdd is reduced at each node to contain power consumption in spite of rising density and frequency

•Tox is reduced to raise I on for speed consideration

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-2 Excerpt of 2003 ITRS Scaling to 2016

Year of Production 2004 2007 2010 2013 2016

Technology Node (nm) 90 65 45 32 22

HP physical Lg (nm) 37 25 18 13 9

EOT(nm) (HP/LSTP) 1.2/2.1 0.9/1.6 0.7/1.3 0.6/1.1 0.5/1.0

Vdd (HP/LSTP) 1.2/1.2 1.1/1.1 1.1/1.0 1.0/0.9 0.9/0.8

Ion/W,HP (mA/mm) 1100 1510 1900 2050 2400

Ioff/W,HP (mA/mm) 0.05 0.07 0.1 0.3 0.5

Ion/W,LSTP (mA/mm) 440 510 760 880 860

Ioff/W,LSTP (mA/mm) 1e-5 1e-5 6e-5 8e-5 1e-4

• HP: High Performance Logic • LSTP: Low Standby Power Technology

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-3 7.2 Subthreshold Current

• The leakage current that flows at V g

µ Intel, T. Ghani et al., IEDM 2003

A/ 90nm technology. µ µ µ µ ( Gate length: 45nm for ds

I NMOS, 50nm for PMOS

Vgs

• The current at Vgs =0 and Vds =Vdd is called Ioff.

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-4 ∝ • Subthreshold current ns (surface inversion carrier concentration) ∝ qϕs/kT • ns e

ϕ S

Ef Ef, Ec

Vgs

ϕ • s varies with V g through a network

Vg dϕ C 1 s = oxe = Cox + η ψ dVg Coxe Cdep S C dep ϕ η In subthreshold, s = constant +V g/

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-5 Subthreshold Leakage Current

ϕ q(constant +V /η ) / kT qV /ηηηkT ∝ ∝ q s / kT ∝ gs ∝ gs Ids ns e e e

ηηη V ∝ qVgs / kT G Ids e Cox ϕ s Cdep C η = 1 + dep Coxe ηηη • Subthreshold current changes 10x for ·60mV change in V g. Reminder: 60mV is (ln10)·kT/q

•Subthreshold swing, S : the change in Vgs corresponding to 10x change in subthreshold current. S = ηηη·60mV, typically 80-100mV

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-6 Subthreshold Leakage Current

• Practical definition of V t : the Vgs at which I ds = 100nA W/L

W q ()V −V /ηkT W ()V −V / S => I (nA) ≈ 100 e g t = 100 10 g t subthreshold L L

Log (I ds )

V =V ds dd W −−− V /S 100 W/L(nA) Ioff (nA) =100 10 t L

is determined only by V t and

Ioff subthreshold swing.

Vt Vgs

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-7 Subthreshold Swing (S)

• Smaller S is desirable (lower Ioff for a given V t). Minimum possible value of S is 60mV/dec.

≈ Cdep ’ • How do we lower swing? S = 60 mV ⋅∆1+ ÷ « Coxe ◊ • Thinner Tox => larger Coxe • Lower substrate => smaller Cdep • Lower temperature

• Limitations

• Thinner Tox oxide breakdown reliability or oxide leakage current • Lower substrate doping doping is not a free parameter

but set by V t.

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-8 7.3 V t Roll-off

• Vt roll-off: V t decreases with decreasing L g. • It determines the minimum acceptable Lg because Ioff is too large if Vt becomes too small.

K. Goto et al., (Fujitsu) IEDM 2003 65nm technology. EOT=1.2nm, Vdd =1V

• Question: Why data is plotted against Lg, not L?

Answer: L is difficult to measure. Lg is. Also, Lg is the quantity that manufacturing engineers can control directly.

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-9 Why Does V t Decrease with L? Potential Barrier Concept

Long Channel Short Channel

Vgs =0V Vgs =0V

V =0V g Ec

N+ Source Vds

N+ Drain V =V Vg=V t gs t-long Vgs =V t-short ~0.2V

• When L is small, smaller V g is needed to reduce the barrier to 0.2V, i.e. V t is smaller.

•Vt roll-off is greater for shorter L

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-10 Energy-Band Diagram from Source to Drain

• L dependence

source/channel long channel barrier

Vds

short channel •V dependence ds log(I ds ) long channel

Vds Vds =0

V =V Vds =Vdd ds dd short channel Vgs

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-11 Vt Roll-off -- Capacitance Network Model

Vds helps Vgs to invert the surface, therefore Vgs Cd V = V − −V ⋅ t t long ds C T V oxe ox Coxe ds C = − ()+ ⋅ d Vt Vt −long Vds 4.0 n+ X C Wdep j oxe Cd Due to built-in potential between N - P-Sub channel and N + drain & source

• 2-D Poisson Eq. solution shows that As the channel length is Cd is an exponential function of L. reduced, drain to channel − distance is reduced; = − ( + )⋅ L l/ d Vt Vt −long Vds 4.0 e therefore Cd increases ≈ 3 where ld ToxWdep X j

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-12 Vertical dimensions (Tox , Wdep , Xj) must be scaled to support L reduction

− = − ( + )⋅ L l/ d Vt Vt −long Vds 4.0 e

≈ 3 where ld ToxWdep X j

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-13 7.4 Reducing the Gate Thickness and Toxe

• Oxide thickness has been reduced over the years from 300nm to 1.2nm. • Why reduce oxide thickness?

– Larger C ox to raise I on – Reduce subthreshold swing

– Control V t roll-off • Thinner is better. However, if the oxide is too thin – Breakdown due to high electric field – Leakage current

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-14 Tunneling Leakage Current

• For SiO 2 films thinner than 1.5nm, tunneling leakage current has become the limiting factor.

• HfO 2 has several orders lower leakage for the same EOT.

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-15 Replacing SiO 2 with HfO 2---High-k

(After W. Tsai et al., IEDM’03)

• HfO 2 has a relative dielectric constant (k) of ~24, six times large than that of SiO 2. • For the same EOT, the HfO 2 film presents a much thicker (albeit a lower) tunneling barrier to the electrons and holes. • Toxe can be further reduced by introducing metal-gate technology since the poly-depletion effect is eliminated.

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-16 Challenges of High-K Technology • The challenges of high-k are – chemical reactions between them and the silicon substrate and gate,

– lower surface mobility than the Si/SiO 2 system – too low a V t for P-channel MOSFET (as if there is positive charge in the high-k dielectric).

• A thin SiO 2 interfacial layer may be inserted between Si-substrate and high-k film.

Question: How can Tinv be reduced? (Answer is in Sec. 7.4 text)

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-17 7.5 How to Reduce Wdep

•Wdep can be reduced by increasing Nsub qN 2ε 2φ 2ε 2φ = + φ + sub s B = + φ + s B Vt Vfb 2 B Vfb 2 B Cox CoxWdep

– If Nsub is increased, C ox should be increased in order to keep V t the same. –Wdep can be reduced in proportion to Tox . • Or use retrograde doping with very thin lightly doped surface layer – Also, less impurity scattering in the inversion layer => higher mobility

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-18 7.6 Shallow Junction Technology contact metal dielectric spacer

channel

shallow junction N+ source or drain extension

• The shallow junction extension helps to control V t roll-off. • Shallow junction and light doping combine to produce an undesirable parasitic resistance that reduces the precious I on. • Theoretically, metal S/D can be used as a very shallow “junction”.

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-19 7.7 Trade-off between I on and Ioff

NMOS PMOS

Intel, T. Ghani et al., IEDM 2003 • Higher I on goes hand-in-hand with larger Ioff -- think L, Vt, Tox, Vdd.

• Figure shows spread in I on (and Ioff ) produced by intentional variation in Lg and unintentional manufacturing variances in Lg and other parameters.

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-20 Circuit Techniques to Relax the Conflict

between I on and Ioff

• Substrate (well) bias – Only some circuit blocks need to operate at high speed.

– Can use reverse well bias to raise the V t for the rest. – This techniques can also reduce the chip-to-chip and block-to-block variations with intelligent control circuitry.

• Multiple V t or Vdd – Lower V t or higher Vdd are used only in the blocks that need speed • Alternative MOSFET structures.

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-21 7.8 More Scalable Device Structures

• Vertical Scaling is important. For example, reducing Tox gives the gate excellent control of Si surface potential. • But, the drain could still have more control than the gate along another leakage current path that is some distance below the Si surface. (Right figure.)

Vgs

T V S D ox Cg ds Cd N+ Cg Cd

P-Sub leakage path

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-22 2-D Potential Profile

• The drain voltage can pull the potential barrier down and allow leakage current to flow along a submerged path.

Drain

Gate Source

Substrate

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-23 Ultra-Thin-Body (UTB) MOSFET • MOSFET built on very thin silicon film on an insulator (SiO 2). • Since the silicon film is very thin, perhaps less than 10nm, no leakage path is very far from the gate.

Electron Micrograph of UTB MOSFET

Gate Gate

N+ N+ Source Drain

SiO Si TSi = 3 nm SiO 2 2

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-24 New Structure I--Ultra-Thin-Body MOSFET • The subthreshold leakage is reduced as the silicon film is made thinner.

-3 Tox =1.5nm, Nsub =1e15cm , Vdd =1V, Vgs =0

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-25 Preparation of Silicon-on-Insulator (SOI) Substrate

• Initial Silicon wafer A and B • Oxidize wafer A to grow SiO2 • Implant hydrogen into wafer A • Place wafer A, upside down, over wafer B. • A low temperature annealing causes the two wafers to fuse together. • Apply another annealing step to for H2 bubbles and split wafer A. • Polish the surface and the SOI wafer is ready for use. • Wafer A can be reused.

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-26 Cross-Section of SOI Circuits

Si Buried Oxide • Due to the high cost of SOI wafers, only some microprocessors, which command high prices and compete on speed, have embraced this technology. • In order to benefit from the UTB concept, Si film thickness must be agreesively reduced to ~ Lg/4

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-27 New Struture II--Multi-Gate MOSFET and FinFET • The second way of eliminating deep leakage paths is to provide gate control from more than one side of the channel. • The Si film is very thin so that no leakage path is far from one of the gates. • Because there are more than one gates, the structure may be called multi-gate MOSFET .

Gate 1 Vg

SourceSi Drain TSi

Tox Gate 2 double-gate MOSFET

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-28 FinFET

• One multi-gate structure, called FinFET, is particularly attractive for its simplicity of fabrication. • Called FinFET because its silicon body resembles the back fin of a fish. • The channel consists of the two vertical Source surfaces and the top surface of the fin. Gate Drain

L Question: What is the channel width, W? g Answer: The sum of twice the fin height and the Source width of the fin.

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-29 FinFET Process Flow

Si Fin Resist

BOX Poly SOI Substrate Fin Patterning Poly Gate Deposition/Litho

NiSi Si 3N4 Spacer

Gate Etch S/D Implant + RTA Spacer Formation Silicidation

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-30 Variations of FinFET

G

Lg G G S S S D D D

Tsi Oxide Buried Tall Short Nanowire FinFET FinFET FinFET • Tall FinFET has the advantage of providing a large W and therefore large I on while occupying a small footprint. • Short FinFET has the advantage of less challenging lithography and etching. • Nanowire FinFET gives the gate even more control over the silicon wire by surrounding it.

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-31 Tall FinFET with Lg=10nm

NiSi Poly-Si 220Å SiO2 cap

Lg=10nm Si Fin

BOX

B. Yu et al. , IEDM 2002

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-32 Nanowire FinFET

5nm Gate Length F. Yang et al., 2004 VLSI Tech Symp.

G S

D Lg = 5 nm

G S

D

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-33 Device Simulation and Process Simulation • Device Simulation – Commercially available computer simulation tools can solve all the equations presented in this book simultaneously with few or no approximations. – Device simulation provides quick feedback about device design before long and expensive fabrication. • Process Simulation – Inputs to process simulation: lithography mask pattern, implantation dose and energy, temperatures and times for oxidization and annealing steps, etc. – The process simulator generates a 2-D or 3-D structures with all the deposited or grown and etched thin films and doped regions. – This output may be fed into a device simulator as input together with applied voltages.

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-34 Example of Device Simulation--- Density of Inversion Charge in the Cross-Section of a FinFET Body

D

G

S

C.-H. Lin et al., 2005 SRC TECHCON Tall FinFET Short FinFET

• The inversion layer has a significant thickness (Tinv ). • There are more more subthreshold inversion electrons at the corners.

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-35 I-V of a Nanowire “Multi-Gate” MOSFET Gate Drain

Source C.-H. Lin et al., 2005 SRC TECHCON

1.4x10 -5 Mid-gap gate Dessis 3-D simulation 1E-3 R=12.5nm V =1V -5 model ds 1.2x10 V =2V T =1.5nm GS 1E-5 ox Mid-gap gate L=1 µm -5 R=2.5nm 1.0x10 R=2.5nm 1E-7 T =1.5nm ox -6 8.0x10 L=1 µm 1E-9

V =1.5V -6 GS 1E-11 6.0x10

-6 1E-13 4.0x10 Dessis 3-D simulation

Drain Current (A) -6 V =1V 1E-15 model DrainCurrent (A) 2.0x10 GS

1E-17 0.0 0.0 0.5 1.0 1.5 2.0 0.0 0.5 1.0 1.5 2.0 Gate Voltage (V) Drain Voltage (V)

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-36 Example of Process Simulation • FinFET Process

The small figures only show 1/4 of the complete FinFET- -the quarter farthest from the viewer.

Manual, Taurus Process, Synoposys Inc.

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-37 7.9 Output Conductance

•Idsat does NOT saturate in the saturation region, especially in short channel devices!

• The slope of the I ds -Vds curve in the saturation region is called the output conductance (g ds ), 0.4 L = 0.15 µm dIdsat V = 2.5V ≡ gs gds Vt = 0.4 V 0.3 dVds m) V = 2.0V

µ gs 0.2 • A smaller g ds is desirable for a (mA/ V = 1.5V gs ds large voltage gain, which is I 0.1 V = 1.0V beneficial to analog and digital gs circuit applications. 0.0 0 1 2 2.5 Vds (V)

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-38 Example of an Amplifier • The bias voltages are chosen such that the transistor operates in the saturation region. A small signal input, vin , is applied. = ⋅ν + ⋅ν ids gmsa t gs gds ds Vdd = ⋅ν + ⋅ν gmsa t in gds out R = −ν ⋅ ννν ids out / R ννν out in − g NMOS ν = msat ×ν out + in (gds /1 R)

• The voltage gain is gmsat /(gds + 1/R).

• A smaller gds is desirable for large voltage gain.

• Maximum available gain is gmsat /g ds

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-39 What Parameters Determine the gds ? dI dI dV ≡ dsat = dsat ⋅ t gds dVds dVt dVds

− dI − dI dVds L / ld ds at = ds at = −g and = e msat dV dVt dVgs ds L / l (From Eq. 7.3.3 , V =V − −V ⋅e d) Idsat is a function of Vgs -Vt t t long ds

− = × L / ld gds gmsat e g Max voltage gain (R → ∞) = msat = eL / ld gds

•A larger L or smaller ld , i.e. smaller Tox, Wdep, Xj, can increase the maximum voltage gain.

•The cause is “Vt dependence on Vds ”in short channel .

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-40 Channel Length Modulation

• For large L and Vds close to Vdsat , another mechanism may be the dominant contributor to g ds . That is channel length modulation .

• A voltage drop, Vds -Vdsat , is dissipated over a finite distance next to drain, causing the “channel length”to decrease. More with increasing

Vds . l ⋅I V >V g = d ds at d dsat ds ()− L Vds Vdsat L

≈ 3 V =V Id ToxWdep X j c dsat

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-41 7.10 MOSFET Modeling for Circuit Simulation

• For circuit simulation, are modeled with analytical equations. • Device model is the link between technology/manufacturing and design/product. The other link is design rules. • Circuits are designed A. through circuit simulations or B. using cell libraries that have been carefully designed beforehand using circuit simulations. • BSIM (Berkeley Short-channel IGFET Model) is the world’s first industry standard MOSFET model. It contains all the equations presented in these chapters.

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-42 Examples of BSIM Model Results

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-43 Example of BSIM Model Results

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-44 Example of BSIM Model Results

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 7-45