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Leakage Current: Moore’S Law Meets Static Power COVER FEATURE Leakage Current: Moore’s Law Meets Static Power Microprocessor design has traditionally focused on dynamic power consumption as a limiting factor in system integration. As feature sizes shrink below 0.1 micron, static power is posing new low-power design challenges. Nam Sung ower consumption is now the major tech- power. However, the power they consume has Kim nical problem facing the semiconductor increased dramatically with increases in device Todd Austin industry. In comments on this problem at speed and chip density. the 2002 International Electron Devices The research community has recognized the sig- David P Meeting, Intel chairman Andrew Grove nificance of this increase for some time. Figure 1 Blaauw cited off-state current leakage in particular as a lim- shows total chip dynamic and static power con- Trevor iting factor in future microprocessor integration.1 sumption trends based on 2002 statistics normal- Off-state leakage is static power, current that ized to the 2001 International Technology Road- Mudge 2 University of leaks through transistors even when they are turned map for Semiconductors. The ITRS projects a Michigan, off. It is one of two principal sources of power dis- decrease in dynamic power per device over time. Ann Arbor sipation in today’s microprocessors. The other is However, if we assume a doubling of on-chip dynamic power, which arises from the repeated devices every two years, total dynamic power will Krisztián capacitance charge and discharge on the output of increase on a per-chip basis. Packaging and cooling Flautner the hundreds of millions of gates in today’s chips. costs as well as the limited power capacity of bat- ARM Ltd. Until very recently, only dynamic power has been teries make this trend unsustainable. a significant source of power consumption, and Figure 1 also shows exponential increases pro- Jie S. Hu Moore’s law has helped to control it. Shrinking jected for the two principal components of static processor technology has allowed and, below 100 power consumption: Mary Jane nanometers, actually required reducing the supply Irwin voltage. Dynamic power is proportional to the • subthreshold leakage, a weak inversion current Mahmut square of supply voltage, so reducing the voltage across the device; and Kandemir significantly reduces power consumption. • gate leakage, a tunneling current through the Unfortunately, smaller geometries exacerbate leak- gate oxide insulation. Vijaykrishnan age, so static power begins to dominate the power Narayanan consumption equation in microprocessor design. The ITRS expects the rate of these increases to level Pennsylvania State out in 2005 but to remain substantial nonetheless. University PROCESS TRENDS Even today, total power dissipation from chip leak- Historically, complementary metal-oxide semi- age is approaching the total from dynamic power, conductor technology has dissipated much less and the projected increases in off-state subthreshold power than earlier technologies such as transistor- leakage show it exceeding total dynamic power transistor and emitter-coupled logic. In fact, when consumption as technology drops below the 65-nm not switching, CMOS transistors lost negligible feature size. 68 Computer Published by the IEEE Computer Society 0018-9162/03/$17.00 © 2003 IEEE 100 300 Gate length 250 1 Dynamic If they reach mainstream production, emerging power 200 techniques to moderate the gate-oxide tunneling effect—primarily by using high-k dielectrics to bet- Possible trajectory ter insulate the gate from the channel—could bring 0.01 if high-k dielectrics 150 gate leakage under control by 2010. reach mainstream Sub- production As leakage current becomes the major contribu- threshold tor to power consumption, the industry must leakage 100 Physical gate length (nm) reconsider the power equation that limits system 0.0001 performance, chip size, and cost. 50 Normalized total chip power dissipation Gate-oxide POWER BASICS leakage Five equations model the power-performance 0.0000001 0 19901995 20002005 2010 2015 2020 tradeoffs for CMOS logic circuits. We present them here in simplifications that capture the basics for logic designers, architects, and system builders. The first Figure 1. Total chip three are common in the low-power literature.3 The 0.5) will reduce the operating frequency by more dynamic and static last two model subthreshold and gate-oxide leakage. than half (fnorm ≈ 0.3). power dissipation Operating frequency and voltage Overall power consumption trends based on the International The first relation shows the dependency of oper- The third equation defines overall power con- Technology ating frequency on supply voltage: sumption as the sum of dynamic and static power: Roadmap for α 2 Semiconductors. f ∝ (V − Vth) / V (1) P = ACV f + VIleak (3) The two power plots for static power where V is the transistor’s supply voltage, Vth is its The first term is the dynamic power lost from represent the 2002 threshold or switching voltage, and the exponent charging and discharging the processor’s capaci- ITRS projections α is an experimentally derived constant that, for tive loads: A is the fraction of gates actively switch- normalized to current technology, is approximately 1.3. ing and C is the total capacitance load of all gates. those for 2001. We can use this relation to develop an equation The second term models the static power lost due The dynamic power relating frequency and supply voltage. First, con- to leakage current, Ileak. increase assumes a sider an operating voltage Vnorm and frequency We have ignored power lost to the momentary doubling of on-chip fnorm, which are normalized to the maximum oper- short circuit at a gate’s output whenever the gate devices every two ating voltage Vmax and frequency fmax. Then switches. The loss is relatively small; it contributes years. approximate a linear relationship of frequency to to dynamic power loss, and the equation’s first term voltage with the following equation: can absorb it, if necessary. When dynamic power is the dominant source of Vnorm =β1 +β2 ⋅ fnorm (2) power consumption—as it has been and as it remains today in many less aggressive fabrication where the constants β1 = Vth / Vmax and β2 = 1 −β1. technologies—we can approximate Equation 3 From Equation 1 we see that f = 0 corresponds to with just the first term. Its V2 factor suggests reduc- Vnorm = Vth / Vmax, which for today’s technology is ing supply voltage as the most effective way to approximately 0.3. The simple relationship that decrease power consumption. In fact, halving the Equation 2 expresses closely matches recent indus- voltage will reduce the power consumption by a trial data.4 factor of four. But Equation 2 shows that halving Note that fmax corresponds to Vmax and that, as the voltage will reduce the processor’s maximum the relation in Equation 1 specifies, the frequency operating frequency by more than half. drops to zero when V is reduced to Vth. Equation To compensate for this performance loss, we can 2 also indicates that reducing the operating fre- use either parallel or pipelined implementations. If quency by a particular percentage from fmax will the implementation runs the original serial com- reduce the operating voltage by a smaller percent- putation as two parallel subtasks or as two age. For instance, if we assume β1 = 0.3, reducing pipelined subtasks, the dynamic power consump- the frequency by 50 percent (fnorm = 0.5) will reduce tion can decrease by more than a factor of two the operating voltage by 35 percent (Vnorm = 0.65). compared to the serial case. Of course, the reduc- Conversely, reducing the voltage by half (Vnorm = tion depends on significant parallelism being pre- December 2003 69 sent in the computation, but many important Tox will reduce gate leakage. Unfortunately, it also code classes approximate this condition, degrades the transistor’s effectiveness because Tox Pipelining including digital signal processing and image must decrease proportionally with process scaling is the low-power processing. to avoid short channel effects. Therefore, increas- architectural ing Tox is not an option. The research community Leakage current is instead pursuing the development of high-k solution. But how useful are parallelism and pipelin- dielectric gate insulators. ing for reducing power when static power As with subthreshold leakage, a die’s combined consumption becomes a major component? gate width is a convenient measure of total oxide As noted, leakage current, the source of sta- leakage. tic power consumption, is a combination of sub- threshold and gate-oxide leakage: Ileak = Isub + Iox. Low-power architectural options Subthreshold power leakage. An equation that Because subthreshold and oxide leakage both Anantha Chandrakasan, William Bowhill, and depend on total gate width or, approximately, gate Frank Fox5 present shows how subthreshold leak- count, a pipelined implementation’s contribution age current depends on threshold voltage and sup- to leakage is comparable to the simple serial case, ply voltage: apart from the extra gates that latches introduce to separate the pipe stages. Pipelined implementations (4) can run at a lower voltage, which can reduce power consumption for both dynamic and static power K1and n are experimentally derived, W is the gate compared to the serial case. width, and Vθ in the exponents is the thermal volt- Parallel implementations can also run at a lower age. At room temperature, Vθ is about 25 mV; it voltage, but only by roughly doubling the amount increases linearly as temperature increases. If Isub of hardware. Thus, depending on some of the equa- grows enough to build up heat, Vθ will also start to tions’ experimental constants, the parallel case rise, further increasing Isub and possibly causing could leak more power than the serial case—even thermal runaway. to the point of offsetting any savings in dynamic Equation 4 suggests two ways to reduce Isub. power. First, we could turn off the supply voltage—that is, Pipelining is therefore the low-power solution.
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