First International Symposium on Nano-manufacturing, April 24-26, 2003

Future Challenges and Needs for Nano- Electronics from Manufacturing View Point

Yoshio Nishi Stanford Nanofabrication Facility Department of Electrical Engineering Stanford University Stanford, California 94305-4070 nishiy@stanford “Manufacturing”

• To make by hand or esp., by machinery, often on a large scale • To work (wool, steel, etc.) into usable form • To produce (something) in a way regarded as mechanical • To make up (excuse, evidence, etc)

Webster's New World Dictionary of the American Language 1958: 1st Integrated Circuit Jack S. Kilby 1960: First MOSFET by D. Kahng and M. Atalla 1959: 1st Planar Integrated Circuit Robert N. Noyce 6 ? m NMOS LSI in 1974 Passivation (PSG)

Al interconnects ILD (Interlayer Dielectrics)

Si substrate (SiO2 + BPSG)

Field SiO magnification 2

Layers Materials Poly Si gate electrode Si substrate Si, SiO2 BPSG Gate SiO2 Field oxide PSG Gate oxide Al Poly Si gate electrode Atoms Source / Drain Source/Drain diffusion Si, O, Al, Interlayer dielectrics P, B Aluminum interconnects Passivation (H, N, Cl) Year of introduction Transistors 4004 1971 2,250 8008 1972 2,500 8080 1974 5,000 8086 1978 29,000 286 1982 120,000 386™ processor 1985 275,000 486™ DX processor 1989 1,180,000 Pentium® processor 1993 3,100,000 Pentium II processor 1997 7,500,000 Pentium III processor 1999 24,000,000 Pentium 4 processor 2000 42,000,000 1900 1950 1960 1970 2000 Vacuum Transistor IC LSI ULSI Tube

10 cm cm mm 10 ? m 100 nm -3 -5 10-7m 10-1m 10-2m 10 m 10 m In 100 years, the feature size reduced by one million times What conditions made sequential growth of IC manufacturing? • Planar technology for precise control of positions in two dimensional plane • Ion implantation for vertical control of impurity profiles • Film deposition and etching enabling vertical scaling • CD control within 10% of minimum geometry • Clean technology resulting in defect density control for over 85% yield for 109devices on chip. • Every new technology node enabled 30-50% cost reduction per bit or gate over previous node • Highly controlled environment for credible statistical data acquisitions MovingMoving PowerPower toto thethe PersonPerson MainframeMainframe 11 MIPMIP 1010 MIPSMIPS 100100 MIPSMIPS 10001000 MIPSMIPS

MinicomputerMinicomputer

WorkstationWorkstation

PCPC

LaptopLaptop

HandheldHandheld

DSPDSP SystemsSystems

19601960 19701970 19801980 19901990 20002000 Enabling BipolarBipolar NMOSNMOS CMOSCMOS SubmicronSubmicron CMOSCMOS DecananoDecanano CMOSCMOS Enabling TTLTTL CISCCISC MPU MPU RISCRISC MPU MPU SpeechSpeech I/OI/O UbiquitousUbiquitous DSP Imaging I/O Communications TechnologyTechnology CompilersCompilers SCSC MemoryMemory DSP Imaging I/O Communications Networks LANLAN GlobalGlobal && MobileMobile AccessAccess Networks Graphics Connectivity Mobile Digital Video Databases Graphics Connectivity Mobile Digital Video Databases SymbolicSymbolic VisualizationVisualization VirtualVirtual RealityReality MegabitMegabit MemoriesMemories GigabitGigabit Memories Memories ComputingComputing LowLow--costcost DSPDSP SuperSuper DSPDSP VLIWVLIW Microprocessors Trend

2008 (Intel) Past: 1972 (Intel) Today: 2002 (Intel) Lg sub-25 nm Lg 10,000 nm Lg sub-70 nm Tox 0.7 nm Tox 1200 nm Tox 1.4 nm f 30 GHz f 0.00075 GHz f 2.53 GHz P several 10 W P 10 kW (75 kHz) N 1.8B

Heat Generation

2002? 10W/cm2 Hot Plate 2006? 100W/cm2 Nuclear Reactor 2010? 1000W/cm2 Rocket Nozzle 2016? 10000W/cm2 Sun Surface P. P. Gelsinger, “Microprocessor for the New Millennium: Challenges, Opportunities, and New Frontiers,” Dig. Tech. 2001 ISSCC, San Francisco, pp.22-23, February, 2001 % of Semiconductor Revenue 35% PC 30%

25%

20% Communications 15% 1996 1997 1998 1999 2000 2001 Estimate In 2000, for the first time, semiconductor revenues in communication exceeded revenues in PC sector. Source: Dataquest Personal Internet Products PDA

Cable DSL 2G/2.5G PDAs3G Cellular I-Video IP Modem Modem Cellular Phone Phone Phone Phone

Bluetooth Enabled Products

Digital Still Digital PDA Network Still Camera Camcorder Camera Camera Home Networking

DAB Digital Internet Digital Video Radio TV Audio Player Recorder/Server iSTB Technology has made systems more personal

Internet DSP & PC Analog Micro- processor MANY per 1 per Person! Person Minicomputer TTL/Logic 1 per Department

Mainframe 1 per Transistors Company

1960s 1970s 1980s 1990s 2000s 2010s Technology in the Internet Age SOC Integration Strategy for Cell Phones Memory Embedded Non-Volatile Memory Memory Digital CMOS Memory Analog/ Digital Baseband Analog Processor CMOS Analog Digital Power Power Power Single Mgmt Mgmt Chip Cell Phone Radio Radio Radio BiCMOS Mixed Signal Radio Digital Radio Passives Passives

Today 200? Technology Innovations for Analog and implications to manufacturing Dennis Buss, 2001 ISSCC

?? PolyPoly resistors:resistors: +1+1 maskmask

?? Isolation:Isolation: +1+1 maskmask

?? DualDual--gategate CMOS:CMOS: +3+3 masksmasks

?? HighHigh--densitydensity capacitors:capacitors: +1+1 maskmask

?? Characterization/modeling:Characterization/modeling: –– MatchingMatching –– TemperatureTemperature dependencedependence –– NonNon--linearitylinearity –– NoiseNoise Technology In The Internet Era Analog SOC Integration: #1 Problem

• Reduced dynamic range: KT/C noise • Reduced head room

5V 5V 5V 5 • High current required for fixed power functions 4 • Low drive current in switches 3.3V 3 2.5V

2 1.8V Voltage 1.5V 1.2V 1.0V 1

1.0 0.8 0.6 0.35 0.25 0.18 0.13 0.11 0.09 Gate Length (? m) What does “Internet Age” imply for silicon-based ICs and Beyond?

Moore’s Law Scaling principle Law of Economics Moore’s Law and Scaling • The basic MOSFET structure has not changed, but the structural details and materials have changed for transistor, isolation, and interconnect. • Scaling uncovers problems that could be ignored previously. • For each generation, available materials and equipment generally set the practical limits (litho is just one example). • Improvements in materials and equipment as well as circuit cleverness may permit successful

implementation of designs that were previously 19 rejected. Mobile, low cost Lg Production Low power Development (for production) 30 nm High performance 20 nm Research (Tr confirmed) 6 nm 3 nm Challenge 2 nm (Unknown ) 1 nm 0.6 nm Ultimate limit Technology Drivers which contributed technology and Manufacturing with Large production volume Strong pull for technology ROI for R&D investment ?DRAM for • most of front-end processings • lithography • packaging for low cost/small form factor • fab engineering ?High Performance Logic / MPU for • transistor performance • multi-level interconnect • design tools • high pin count packaging

22 Mobile communication and computing in the Internet Age provide ever increasing challenges, i.e. – ultra-low power consumption – digital and analog integration including RF – cost sensitivity As a new technology driver – conflicting requirement for digital and analog for supply voltage – on-chip noise management issue 23 How far can we go with scaled CMOS for IC manufacturing,i.e. with top down manufacturing methodology? Simplified Cross-Section of MOSFET Transistor Structure

Spacer Gate electrode, poly

Upper interfacial region High-k Gate Lg Dielectric Stack Bulk high-k film

Lower interfacial region Source Drain Si Substrate (or SOI with Si thickness ? 1/3 Lg)

P.M. Zeitzoff, R.W. Murto and H.R. Huff, Solid State Technology, July 2002 On going efforts to extend the life of silicon based CMOS

• High K gate stack with metal gate • Channel mobility improvement • SOI • Ultra shallow source and drain junction • Low K/Cu for interconnect • Continuous shrink with lithography evolutions Ultimate limits? ITRS Roadmap (at introduction) 102

101 MPU Min. V supply 100 Lg Junction depth 10-1

10-2 Gate oxide thickness 10 nm Wave length of electron m), Voltage(V)

? 3 nm Direct-tunneling limit in SiO 10-3 2 0.3 nmDistance between Si atoms Size ( 10-4

10-5 ULTIMATE 1970 1990 2010 2030 2050 LIMIT Year 10.000 Gate Lengths from IEDM Paper Titles IEDM Titles NMOS IEDM Average CMOS 94 SIA & Fit 1.000 2001 ITRS MPU SubMicron CMOS

0.100

DecaNanoElectronics Super Scaled CMOS 0.010

Stated Gate Length (microns) Single Electron Devices NanoElectronics Nanotubes Resonant Tunneling 0.001 1960 1970 1980 1990 2000 2010 Year of Publication (or First Production) High Resolution TEM showing 0.03 ? m Channel Length

Polysilicon Gate

4 layers of Si atoms 1.1nm SiO2 consumed inversion charge to create two decades 1.1nm SiO2 Source in 10 nm electron Drain mean free path 4 nm 30 nm Channel Length 78 columns of Si atoms donor atom acceptor atom Needs for Metal Gate Electrodes

• Elimination of poly silicon depletion for smaller EOT • Work function engineering for elimination of channel implant in order to minimize impurity scattering in the channel as well as avoid stochastic fluctuation of the threshold voltage of MOSFET. • Needs atomic/molecular level of understandings of “interface structure” relevant to “work function” in multi-layer structure Needs for high K dielectrics

• Larger K without frequency dispersion • Minimum channel carrier mobility degradation • Allow metal electrode for work function engineering • Stable during process integration environment • Thickness controllability, Manufacturability • Yan et al. (APL 79 [11] 2001) used micro-contact printing of alkylhalosilane self-assembled mono- layers on SiO2 to define ALD-deactivated pattern

• ZnO ALD of circular dots (Tsubs = 125?C)

•Reported near-complete deactivation of SAM-coated oxide surface Needs for smaller geometries

• 248nm • 193nm • 157nm • Charged beams • EUV • Nanoimprint/soft imprint Without manufacturing cost increase per gate or bit Amortization of Mask Cost (130-nm)

1000

100

10 Cost per Chip [$]

1 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08 Chips Produced A real opportunity for a nano-manufacturing paradigm which is “small-lot friendly” ! Robert Doering, May 12,2002 Subset of 2001 ITRS

YEAR 2001 2004 2007 2010 2013 2016 General (nm) 130 90 65 45 32 22 lithography DRAM Memory size (Gb) .512 1 4 8 32 64 Chip size (mm2) 127 93 183 181 239 238 MPU Gate length, (nm) 65/90 37/53 25/35 18/25 13/18 9/13 physical/printed Equivalent oxide (nm) 2.5 1.9 1.5 1.2 0.8 0.6 tox Gate delay (ps) 11 6.9 5.7 3.7 2.6 2.4 Transistor/chip (106) 97 193 386 773 1546 3092

VDD::High perf (V) 1.1 1 0.7 0.6 0.5 0.4 Low power 1.2 1.1 0.9 0.8 0.7 0.6 Power:High perf (W) 130 160 190 218 251 288 Low power 2.4 3.2 3.5 3.0 3.0 3.0

Number of wiring 7 8 9 9 9 10 levels In fact silicon based CMOS is already in the world of “nanoelectronics” What’s beyond scaling, the world of “nanoelectronics”? • Electrostatic improvement of MOSFET FINFET, Vertical MOS, FDSOI • Improvement through materials for MOSFET high K gate, low-K ILD, gate metal work function, higher mobility channel, Ge channel, Schottky S/D • New functional materials ferroelectric memory, MRAM, Ovonic/polymer memory, single electron/quantum dots memory • Non-silicon 3D solution, nanowire, nanotube • MEMS/NEMS integration • Optical interconnect/on-chip receiver Will Future Nanoelectronics Technologies Complement or Replace CMOS ?

Source: 2001 ITRS Double-Gate Transistor Structures top gate 100 nm Double Gate G SOI S D IBM ‘97

source bottom gate drain

Schematic Gate Cross-Section

SiO2 S G D

SiO SiO FinFET Simplified view of SiO2 SiO2 FinFET Source Drain (one typetype of of double--gategate BOX MOSFET) T-J. King and C. Hu, UC/Berkeley Top View and Mark Bohr, ECS Meeting PV Key advantage: relatively 2001-2, Spring, 2001 conventional processing, Fin largely compatible with Drain current techniques Source

Poly Gate Technology in the Internet Age Embedded Memory Technology

SRAM FLASH DRAM FRAM MRAM OUM Mask Adder to High Perf Logic Process 0 - 2 6 - 8 6 - 8 2 3 - 4 3 - 4

Standby Power High NV High NV NV NV

Random Access Yes No Yes Yes Yes Yes

Area (mm2) for 1Mbit @ 90 nm 1.35 0.35 0.4 0.6 0.6 0.4 node The Ideal MOS Transistor Challenges Facing a Pervasive Replacement of “Ultimate Scaled CMOS”

• Cost of less than 0.5 micro-cents per logic gate • Greater than 4x108 logic gates per cm2 • Greater than 1010 “minimum-size switches” per cm2 (e.g., SRAM transistors) • Cost of less than 50 nano-cents per bit of memory • Greater than 30 Gbits of memory per cm2 • Intrinsic switching speed greater than 5 THz • Power consumption of less than 6 µW per MOP/sec • Reliability of greater than 105 hours (~ 10 years) operating lifetime • SER of less than a few thousand FITs per Mbit in terrestrial environment • Capable of “mass production” (e.g., > 1 million units /day) • Ability to integrate logic, analog, RF, memory (high-speed, high-density, nonvolatile, etc.) Robert Doering, May 12, 2002 Opportunity for nano-scale devices

• Proof of concept • Manufacturability demonstrations reproducibility under controlled environment controllability of every parameters, positioning capability with accuracy, • Reliability Acceleration mechanism for possible failures based upon thorough understanding of physics and chemistry behind • Cost of ownership (COO) competitiveness What conditions made sequential growth of IC manufacturing? • Planar technology for precise control of positions in two dimensional plane • Ion implantation for vertical control of impurity profiles • Film deposition and etching enabling vertical scaling • CD control within 10% of minimum geometry • Clean technology resulting in defect density control for over 85% yield for 109devices on chip. • Every new technology node enabled 30-50% cost reduction per bit or gate over previous node with right technology driver • Highly controlled environment for credible statistical data acquisitions New era beyond microelectronics

• Aggressive introduction of new materials • New device structures based upon new materials, as well as new phenomena • Research under controlled environment with capability integration • New characterization capability coupled with adequate modeling and simulation capability Needs for Paradigm Changes

• System/architecture level consideration from early stage of device research, Connection between top-down and bottom up approaches • Horizontal geometry control, CD and overlay: Limited and costly Should it be horizontal? • Vertical geometry control: more precise, e.g. atomic layer deposition Can we build devices vertically? Careful introduction of bottom-up approach? Summary

• Internet Era drives much more variety of nanoelectronics technology than the previous eras which will serve as “system level driver”. • Silicon-based CMOS technology will remain as the basic platform in the foreseeable future with nanoelectronics devices with new materials and new electrostatic improvements as far as manufacturing cost per function decreases. • Top down manufacturing methodology faces tough challenges in terms of further manufacturability improvement • New functionality/new devices introduced via nanotechnology/ nanoelectronics will have opportunity if they can be embedded to silicon platform coupled with design paradigm changes. • Environment with a variety of materials and processes handling capability coupled with strong characterization capability is a key enabling infrastructure. 47