Vmos) for Smart Sensors and Extension to a Novel Neu-Gaas (Vgaas) Paradigm (Invited)

Neu-MOS (vMOS) for Smart Sensors and Extension to a Novel Neu-GaAs (vGaAs) Paradigm (Invited)

D. Abbott, S.F. Al-Sarawi, B. Gonzalez*, J. Lopez*, J. Austin-Crowe+ and K. Eshraghian+ The Centre for High Performance Integrated Technologies and Systems (CHiPTec) Department of Electrical and Electronic Engineering The University of Adelaide, Adelaide SA 5001 Email: dabbott Qeleceng .adelaide. edu. au, alsarawiQeleceng .adelaide. edu. au Phone: +61 8 8303 5748 Fax: +61 8 8303 4360 *University of Las Palmas, Spain +Edith Cowan University, Australia

Abstract tionality/area [2] while still maintaining low cost via the use of standard CMOS fabrication. In addition The neu-MOS (vMOS) transistor is a new device that to neural networks the application areas were vMOS enables the design of conventional digital and analog will have use are motion detectors [3, 4, 51, mono- circuits, in standard CMOS, with a factor of 5-10 de- lithic imaging/compression [6],spatial light modula- crease gate count. Furthermore, vMOS circuit char- tors (SLMs) and optical neural arrays [7]. acteristics are insensitive to transistor parameter vari- For instance the same gate can perform the func- ations but instead rely on coupling capacitor ratios. tion of AND, OR and XOR depending on the state of In this paper, we demonstrate this principle with re- an input control signal [8]. This new paradigm of ‘soft’ sults from fabricated controlled gain amplifiers. This hardware is referred to as flexware. Consequently, new technology is ideal for smart sensors where a high vMOS has been successfully employed in a number of functionality per pixel area and good matching be- digital architectures with a dramatic saving in silicon tween pixels is required. Moreover, we discuss the ad- area. It has been reported that the area of a vMOS vantages of smart sensors in GaAs technology and the multiplier with full-adders decreases to about 65% of viability of developing a vGaAs paradigm. the area of CMOS, and the delay of a vMOS multiplier with (7,3) parallel counters decreases to about 70% of the delay of its CMOS equivalent [a]. 1 Introduction An important feature to note is that a vMOS implementation only requires a conventional double The neu-MOS (vMOS) transistor, recently discovered polysilicon CMOS process and therefore is a readily ac- by Shibata and Ohmi [l]in 1991, simply uses capaci- cessible technology. Consequently, vMOS is a low-cost tively coupled inputs onto a floating gate. The resulting output is simply a weighted sum of the inputs, method for increasing the functionality per unit silicon due to the capacitive input network, followed by a area. Other schemes to increase functionality/area are thresholding operation. The behaviour of the tran- generally esoteric and expensive [9]. In the literature, most vMOS circuits have em- sistor resembles, very well, that of a biological neuron ployed digital inputs however a few groups have where the turn-on of the transistor is parallelled by [lo], explored analog techniques [ll, 121. In this the firing of a neuron. In this respect, the device is vMOS paper new analog circuits built using vMOS transis- called a neuron MOSFET or a neu-MOS (vMOS) for tor are discussed. Section 2 will discuss briefly the short. The structure, the symbol and the capacitance representation of the vMOS transistor are shown in key design parameters for the vMOS transistor. Sec- tion 3 will discuss the design of controlled gain am- Fig. 1.a-c. vMOS circuits operate with mixed mode analog/digital functions and can even perform Boolean plifier circuits in which gain is controlled by capacitor logical operations that are dynamically reconfigurable. ratio rather than depending on process parameters. The use of vMOS circuits will greatly increase func- The smart sensor paradigm requires process-

397 0-7803-5008-1/98/$10.0001998 IEEE. The product of y and VDD represents the maxi- mum floating-gate voltage obtained when all input gates are at VDD.In the above equation CO P-substrate 7 can vary depending on the operating condition of the transistor. However, it can be approxi- mated by the gate oxide capacitance when the device is ‘ON’ and can be regarded as a constant as long as the channel is formed [14]. The value of y can be maximised by increasing CL==lCi compared to CO. However, this would increase the size of the circuit and it should be considered as a trade-off.

e Threshold Voltage Seen from the Floating Gate, V;, The second key design parameter is V;,, which is the threshold voltage of the transistor seen Figure 1: (a) The basic structure of an n-vMOS tran- from the floating gate. V;, represents the bound- sistor, (b) its electronic symbol. (c) Capacitance rep- ary between the ‘ON’ and ‘OFF’ states of the resentation of the vMOS, where CO is the sum of all transistor. So, for the transistor to turn ‘ON’, the parasitic capacitances from the floating gate to the the following condition should be satisfied substrate including the floating gate to source. ing to take place at every pixel. With increasing de- Equation 2 states that when the linear weighted mands on at-pixel processing, such as in mobile video sum of all input signals exceeds a certain thresh- communications (eg. the IM3PC paradigm [13]), and old value V+H,the transistor turns ‘ON.’ VG, is with good pixel-to-pixel matching required for mini- one of the main design parameters of the vMOS mal fixed-pattern-noise, the vMOS technology offers transistor. an ideal solution. With vMOS, greater processing functionality at each pixel becomes possible and bet- 0 Floating Gate Offset Voltage, q5~ ter matching is achieved as vMOS relies on controlled A shift or an offset on the floating gate volt- capacitor ratios, thus reducing problems due to tran- age can be a result of two separate effects. The sistor parameter spreads. Furthermore, we shall dis- first is due to an initial charge on the floating cuss the advantages of using GaAs for smart sensors gate that is trapped on the floating gate during and hence, for the first time, we will comment on the the fabrication process. The magnitude of such feasibility of a novel vGaAs paradigm. shift can be as large as f200 mV [12]. A num- Due to the greater functionality per unit area, ber of methods can be used to reduce this effect. available in vGaAs, interconnect lengths are also greatly The first is to shine UV light on the transistor reduced as a ‘by-product of this methodology. Hence, while all terminals are grounded. This will ex- vMOS is very promising as a low power technology cite some electrons to energy states above the which is attractive for smart sensors in mobile appli- conduction band of the oxide layer, resulting in cations. an increase in the oxide layer conductance, al- lowing the discharge of the floating gate until its potential is the same as ground [12]. The 2 Key Design Parameters for the second method is to inject some charge carri- vMOS Transistor ers to the floating gate. ie. programming the floating gate using Fowler-Nordheim tunnelling This section will identify some of the main key design effect [15]. The third method is to electronically parameters that can be used in designing analog and initialise the floating gate charge by connecting digital circuitry using vMOS transistor. the floating gate to a predefined voltage. Such method is actually used in [16, 17,181to initialise 0 Floating-Gate Gain Factor, y the floating gate potential. The first design parameter to be considered is The second effect that might cause shift in the the floating-gate gain factor, y, which is defined floating gate potential is the gate to drain ca- as pacitance, CSd,as a result of feedback from the drain to vMOS floating gate. This capacitance will have effect when the vMOS transistor is operating in the linear region of operation [14]. The

398 effect of such capacitance can be reduced by using minimum size vMOS transistor and maximis- ing the ratio of E:=, CiK to CgdVds. Where vds is the drain to source voltage of the vMOS transistor.

3 Controlled Gain Amplifiers This section describes the design of a controlled gain amplifier using vMOS transistor, where the gain of the amplifier is controlled through capacitor ratio instead of transistor size ratio. The amplifier design is based on the linear grounded resistor discussed in [l]. Later in this section, another approach to the amplifier design using a ‘neuron-inverter’ (vCMOS inverter) will be discussed. It will be shown that both approaches give the same results. The first approach is to use two grounded resistors, one using n-vMOS, while the other using p- vMOS and connected as shown in Fig. 2.a. The gain of the amplifier circuit can be found analytically by writing the current equations of the n- and p-vMOS transistors as follows

are n- and p-MOS drain currents; are n- and p-MOS gain factors; is the ratio of the input coupling capacitance of transistor type k, Ci,, , to the total capacitances at that transistor, CTOT~. Figure 2: (a) A controlled gain amplifier circuit de- Cin . ie. win, = and = e CTO;, ’ signed using linear grounded resistors. (b) The sim- is ratio of the output to input coupling ulated input-output characteristics of the controlled capacitance of transistor type k, CO,,to gain amplifier shown in (a). the total capacitance at that transistor, - CTOTk. ie. WO, - cTo”T, and WO,= COP . CTOT, ’ wo/2and v,, = Vdd/2,to is the output voltage on the’amplifier; is the initial voltage at the floating gate; ---Cin v0- COKn (6) is the supply voltage; is the threshold voltages of transistor type k. The above equation shows that the amplifier gain is purely a function of the capacitor ratio and it Solving Equations 3 and 4 for Vo results in is independent of process parameters and the supply voltage. To confirm Equation 6, the amplifier circuit fiwin. + win, was simulated with CO= 10 pF while Cin was swept vo = - Kn from 5 pF to 25 pF in 5 pF steps. The simulation &won + WO, results are shown in Fig. 2.b. The second approach to the design of a controlled gain amplifier is to use ‘vCMOS inverter,’ which is simply a normal digital inverter that has N input terminals capacitively coupled to its gate. For the amplifier design a dual input ‘neuron inverter’ is used with one of the input terminals connected to the output of the inverter, while the other terminal is used as an input terminal, as shown in Fig. 3.a. Once such a con- Equation 5 can be simplified by setting ,& = p,, nection is made, the functionality of the circuit will &, V,,, Win, = Win, = Win/2, WO, = WO, = be completely different from the ‘neuron inverter,’ [l]

399 as in the case the ‘neuron inverter’ the output signal is a digital state of either ‘1’ or ‘0.’ While using this configuration the circuit will act as an amplifier. Vdd 7- The above equation can be simplified by letting Pn = pp, G,,= &, and V,, = V&/2, resulting in

bin vo = --CO vi, (10)

nom the above first order analysis, it can be seen that the gain is also function of the of the ratio of &/CO and independent of the process parameters and the supply voltage. The simulation results of the amplifier with Ci, swept from 5 pF to 25 pF in 5 pF steps, while assuming that Pn = &, and Vt,, = Vtp, are shown in Fig. 3.b. An interesting feature of the above circuits can be obtained by taking the special case when Cin = CO, this will result in an inverting analog buffer circuit with linearity completely independent of the transistor parameters and purely function of the capacitor ratios. Measurements results for a 6 dB neuron-MOS- amplifier circuit designed based on the above analysis will be presented in the conference. The amplifier is implemented in a 1.2 pm double poly, double metal CMOS process.

4 GaAs for Smart Sensors A number of physical and optoelectronic properties of GaAs make it a highly suitable medium for opti- (b) cal smart sensors. In this section, these properties are discussed with a view to smart image sensors (a) in Figure 3: (a) A schematic diagram of a controlled gain a stand-alone context and (b) in the context of spa- amplifier using vMOS transistor. (b) The simulation tial light modulators (SLMs). After establishing that results of relationship between the output voltage, V,, GaAs is indeed advantageous for smart sensors, we and the input voltage, Vi,, of the controlled gain am- then go onto discuss the possibility of a new neu-GaAs plifier circuit with input coupling capacitor, Gin,swept (YGaAs) paradigm and discuss the most suitable GaAs from 10 pF to 50 pF with 10 pF increment, while CO technology to achieve this. was fixed at 20 pF. The motivation to explore smart sensors in GaAs technology arises from the fact that (a) the optical absorption coefficients in GaAs are such that light is ab- The gain of the amplifier can be calculated by sorbed 10 times closer to the surface, than in silicon, writing the current equations of the p-YMOS and n- resulting in more efficient photocollection and tighter vMOS transistors using a simple transistor model in control over optical overload (blooming) [19] (b) the the saturation region as follows diffusion lengths in SI GaAs are over an order of magnitude shorter than in silicon, resulting in improved spatial resolution, showing promise for HDTV applications [20] (c) GaAs has superior dark current characteristics, as evidenced by the successful realisation room temperature GaAs X-ray detectors [21] and (d) there is promise of integration of high-speed process- where ing (eg. image compression) on the same chip as the is ratio’ of i/p coupling cap., Ci,, to total sensor. win capacitance, cTOT. This section demonstrates the superiority of GaAs is ratio of o/p to ilp coupling cap., to eo, in all areas over silicon, but reveals that shot noise wo total capacitance, cTOT. degradation is the main area of weakness for MESFET technology. However, newly emerging GaAs technolo- Solving Equations 7 and 8 for Vo gives gies such as HIGFETs [22], anisotype FETs [23] and

400 MOS-GaAs [24] are discussed, showing promising re- lengths and small carrier diffusion lengths. The supe- sults. riority of the GaAs over silicon, in terms of absorption length, is illustrated in Fig. 5. As can be seen, 4.1 GaAs Smart Image Sensors light is absorbed about ten times closer to the surface in GaAs than in silicon. This implies tighter con- In this context, the ‘smart sensor’ paradigm implies trol over blooming, increased photocollection efficiency the integration of processing circuitry (eg. for image and greater spatial resolution. compression) with the image sensor. The superior power-delay product of GaAs becomes ideal for such high-speed processing in real-time. Such integration Gate Depletion rules out the possibility of using a CCD process - CCD technology cannot support conventional digital circuits. Therefore, such a GaAs image sensor must use a standard or near-standard VLSI GaAs technology. The type of imager in this technology uses an XY Substrate . addressable array of transistors as shown in Fig. 4.

Column Select Register

I 1 I Video io5 - Analogue Multiplexer

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 Wavelength (Fm)

Figure 5: GaAs v. silicon absorption length

It can be estimated [20] that the carrier diffusion length is <10pm. This is much smaller than in CMOS where minority carrier diffusion lengths are in the 200- 400pm range. The implication of short diffusion length together with shallow absorption length is excellent spatial resolution for HDTV applications [25]. How- ever, in practice, for silicon imagers, good spatial resolution is obtained at the expense of responsivity, by use of a thin epi layer. Therefore in practice, with GaAs, improved spatial resolution translates into im- Figure 4: XY Array imager architecture - charge sensing approach. proved responsivity over silicon, as the epitaxial approach can be dispensed with. This improved respon- There are two methods of readout: (a) charge sivity impacts not only on GaAs HDTV sensors, but sensing and (b) voltage sensing. In a voltage sensing on the GaAs smart sensors discussed herein. approach, signal charge is converted to a voltage at each pixel node. As the conversion capacitance at each 4.2 GaAs Spatial Light Modulators pixel is small, this results in reduced kTC noise and (SLMs) hence improved dynamic range. However, the down- side is that capacitor and source follower mismatching SLMs are basically 2-D arrays that output image pat- between pixels lead to high fixed pattern noise (fpn). terns reflectively (eg. via Ferroelectric Liquid Crystal In the charge sensing approach, this source of or FLC) or directly (eg. a micro-array of LEDs or a fpn is eliminated by dumping the charge from each VCSEL). These light patterns can be modulated ei- pixel on to the output node. In this way, charge-to- ther electrically (ie. an electrically addressable SLM or EASLM) or optically (ie. an optically addressable voltage conversion occurs at the final output - thus only one source follower is required at the output. Due SLM or OASLM). Thus these devices essentially per- to the architecture of the array a large output node form smart optical spatial filtering functions. capacitance is unavoidable, leading to increased kTC The EASLM can consist of an array of smart noise and reduced dynamic range. pixels sandwiched to either a LED or FLC display de- However, due to the semi-insulating (SI) sub- vice. Further to this, the OASLM utilises a smart strate, capacitances are reduced making the charge image sensor for optical addressing. sensing XY array, in Fig. 4, the best choice in GaAs. GaAs offers two significant possibilities: an LED/- GaAs, Fig. 6, or an FLC/GaAs, Fig. 7, architecture. Further advantages with the shift to GaAs, as outlined in Sec. 5, include shallow optical absorption The advantages of GaAs are numerous. Firstly the

40 1 larger absorption coefficient in GaAs leads to improved digital GaAs process is also intrinsically more planar optical addressing characteristics [19]. Secondly, FLC than CMOS (eg. no field oxide) and therefore varia- technology is sensitive to surface planarity and wafer tions in FLC thickness are further reduced. warp as little as 1 pm - GaAs offers excellent planarity Due to the improved power-delay product of due to the absence of .field oxide steps and a warp of GaAs over silicon, either throughput rate can be in- less than 0.5 pm has been achieved. In silicon, for typ- creased or, for the same speed, power dissipation is ical devices, the warp is greater than 1 pm leading to reduced. This becomes important for stacked devices critical nom-uniformities in the FLC layer. GaAs also as greater care over thermal management is required. offers the potential to move away from LC technology altogether as LED arrays can be monolithically integrated [26]. With the emergence of low-power comple- 5 Choice of GaAs Technology mentary GaAs, already available with VLSI maturity, the traditional problems with power dissipation are no We have shown [27] that shot noise dominates the noise of the output circuit of a smart sensor array longer of concern. Other advantages of GaAs include no latchup, fewer masking layers (simpler) and existing based on GaAs MESFET technology. Unfortunately techniques for through-substrate-vias (this has impli- it is impossible to remove shot noise by correlated dou- cations for future 3-D mounted SLMs). ble sampling. This means that the circuit cannot be optimised €or this MESFET technology. The source of this shot noise is ‘the high gate leakage current in MESFETs, which also makes the realisation of vGaAs Optical Optical circuits impossible due to the consequent rapid dis- I Input output charging of the various coupling capacitors. In the longer term, two emerging GaAs tech- GaAs $. Detector nologies are promising: the HIGFET and the anisotype FET. The HIGFET [23] uses a semi-insulating AlGaAs layer in the gate to reduce leakage currents. The anisotype FET [22] uses a graded semiconductor GaAs Substrate InGaAs/GaAs layer in the gate, producing yet a fur- L ther improvement in gate leakage. Recently Lucent have announced a true MOS- GaAs [24], using a mixture of gallium oxide and gadolin- Figure 6: A LED/GaAs smart pixel ium oxide Ga203(Gd203).If oxide stability and high integration levels are eventually proven, this will be the ideal medium for the GaAs smart sensors based on uGaAs.

- Glass However, in the immediate short term, complementary GaAs based on HIGFET transistors appears IT0 Coating to be the most viable option for uGaAs smart sen- FLC ThinFilm sors in terms of maturity, low power performance and Modulator/ Transmitter tolerable gate leakage levels. We have performed some initial complementary HIGFET simulations based on a I Si or GaAs Substrate I realistic composite parameter set derived from a number of complementary GaAs processes. These include Honeywell [28], Sandia [29], Univ. Lille [30], Fujitsu [31] Figure 7: A FLC/Si or FLC/GaAs smart pixel and MIT [32]. Although this parameter set is con- trived, our approach be to adjust the parameters (esp. GaAs has a number of advantages with respect gate leakage) to produce the optimum uGaAs perfor- to the smart pixel concept. Firstly in order to enable mance. In this way we ‘reverse engineer’ the expected optical input,, a 2D image sensor must be vertically complementary HIGFET parameter set for best uGaAs stacked with parallel connections to the display device performance. Then this information will help to select using, for example, flip-chip techniques. Fortunately, the best HIGFET vendor for vGaAs. At this stage the GaAs crystal has excellent crystal properties en- vGaAs simulations are somewhat hypothetical, as con- abling etching of through-substrate-vias with relative venient capacitors do not exist - whereas in MOS the ease and this is a known technique in GaAs MMICs coupling capacitors are conveniently provided by the that use vertical connections to a backside ground- poly1 to poly2 overlap. However, in principle, it would plane. Smart pixel functions can be embedded either be relatively simple to add a special high capacitance in the sensor or display device or both. MIM layer to existing HIGFET processes. Justifica- Another feature of GaAs is that wafer warp tion of this would not be solely based on uGaAs, but across a chip is superior to silicon and <1 pm. Silicon would also be for RF circuits in instances where com- has the disadvantage that a warp >1 pm degrades the plementary GaAs is used in mixed RF/digital applica- performance of the FLC display, creating a deleterious tions. This would be particularly pertinent in mobile dispersion in phase across the area of the device. The multimedia systems that use both smart sensors and

402 RF wireless communications. Preliminary simulations A. Moini, A. Bouzerdoum, A. Yakovleff, D. Ab- demonstrate functional vGaAs 3-bit A/D converters bott, 0. Kim, K. Eshraghian, and R. Bogner, “An with a factor of 4 reduction in gate count and power analog implementation of early visual processing dissipation reduction over a factor of 50 over conven- in insects,” in Int. Symposium on VLSI Technol- tional complementary GaAs layouts. ogy, Systems, and Applications, pp. 283-7, May 1993. 6 Conclusion D. Abbott, A. Moini, A. Yakovleff, X. Nguyen, A. Blanksby, W. Kim, A. Bouzerdoum, and The Neuron MOS transistor has been used extensively R. Bogner, “A new VLSI smart sensor for collision in the design of digital circuitry, however, the use of avoidance inspired by insect vision,” Proc. SPIE, such a transistor in analog design has not been fully Intelligent Vehicle Highway Systems, vol. 2344, investigated. In this paper a number of key design pa- pp. 105-15, 1994. rameters for analog and digital circuits have been iden- tified. The analog examples designed and discussed in D. Abbott, A. Moini, A. Yakovleff, X. Nguyen, this paper and based on these key design parameters R. Beare, W. Kim, A. Bouzerdoum, and are meant to demonstrate that the vMOS transistor K. Bogner, R.E.; Eshraghian, “Status of recent can be used to design useful analog circuitry. This was developments in collision avoidance using motion demonstrated through the design of controlled gain detectors based in insect vision,’’ in Proc. SPIE, amplifiers. These circuits have gain that is indepen- Transportation Sensors and Controls, vol. 2902, dent of the process parameters and also independent pp. 242-7, NOV. 1996. of the supply voltage. The designed circuits represent T. Nakai, T. Shibata, and T. Ohmi, “Neuron good candidates for basic building blocks in analog MOS quasi-two-dimensional image processor for signal processing and in the smart pixel environment. real-time motion vector detection,” in Proc. of Moreover, we have discussed a number of advantages the 4th International Conference on Soft Comput- of the GaAs technology for smart sensors and have ing (IIZUKA ’96) Methodologies for the Concep- indicated that the complementary GaAs technology tion, Design, and Application of Intelligent Sys- based on HIGFETs is the most promising approach tems, vol. 2, pp. 833-6, World Scientific; Singa- for future vGaAs circuits. pore, Sept. 1996. In conclusion, vMOS transistor can be used successfully in designing useful analog building blocks and E. Lange, Y. Nitta, and K. Kyuma, “Optical neu- has the potential to provide low power circuitry be- ral chips,” IEEE Micro, vol. 14, no. 6, pp. 29-41, cause the input signals are capacitively coupled to the 1994. floating gates which are of small area. Moreover, as the functionality per unit area increases, this would T. Shibata and T. Ohmi, “A functional MOS enable the design of systems with complex functions transistor featuring gate-level weighted sum and with smaller silicon area compared to traditional MOS threshold operations,” IEEE Trans. ED, vol. 39, circuitry, and hence provide a step forward toward pp. 1444-55, June 1992. pseudo ULSI integration density. S. Al-Sarawi, D. Abbott, and P. Ramon, “A re- view of 3-D packaging technology,” IEEE Trans. 7 Acknowledgement on CMPT, Part B: Advanced Packaging, vol. 21, no. 1, pp. 2- 14, 1998. The authors would like to thank The Computer Vision T. Shibata and T. Ohmi, “Neuron MOS binary- Group in the The Centre for High Performance Inte- logic integrated circuits. I. design fundamentals grated Technologies & Systems (CHiPTec) for includ- and soft-hardware-logic circuit implementation,” ing test module fabrications as part of their system. Trans. ED Circuits (Mathematical, Astronomical Funding from the Australian Research Council (ARC) and Physical Science), vol. 40, pp. 570-6, Mar. is greatfully acknowledged. 1993. [ll] S. Al-Sarawi, D. Abbott, and P. Cole, “Applica- References tion of neuron MOS in analog design,” in Proc. of T. Shibata and T. Ohmi, “An intelligent MOS the 14th Australian Microelectronics Conference. transistor featuring gate-level weighted sum and Microelectronics, Meeting the Needs of Modern threshold operations,” in Inter. Electron Devices Technology., (Melbourne, Australia), pp. 123-8, Meeting, (Washington, DC, USA), pp. 919-22, IREE; Edgecliff, NSW, Australia, Sept. 1997. Dec. 1991. [12] K. Yang and A. Andreou, A multiple input dif- K. Hirose and H. Yasuura, “A comparison of par- ferential amplifier based on charge sharing on allel multipliers with neuron MOS and CMOS a floating-gate MOSFET, ch. 6, pp. 197-208. technologies,” in IEEE APCCAS ’96, pp. 488-91, Kluwer Academic Publishers, Nov. 1994. Nov. 1996.

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