RoleRole ofof HighHigh--KK GateGate DielectricsDielectrics andand MetalMetal GateGate ElectrodesElectrodes inin EmergingEmerging NanoelectronicNanoelectronic DevicesDevices

Robert Chau Intel Fellow Director of Transistor Research and Nanotechnology Technology and Manufacturing Group Intel Corporation

June 22, 2005 1 Contents

ƒ Introduction ƒ Review of physics of high-K on Si ƒ Emerging nanoelectronic devices – III-V – Carbon nanotube FETs – Semiconductor nanowire FETs ƒ Benchmarking emerging non-Si nanoelectronic devices versus conventional planar and non-planar Si transistors ƒ Role of high-K/metal-gate in emerging nanoelectronic devices for future, potential high-performance and low- power logic applications ƒ Summary

2 Transistor Nanotechnology

90 n m Tec 200 65 hnolo 3 nm gy Ge Emerging M 20 45 nera anufa 05 nm tion cturin Nanoelectronic g 2007 32 nm De velop 200 Devices ment 9 20 11+ Res earch 30 nm 50 nm 20 nm 10 nm 35 nm SiGe S/D SiGe S/D S PMOS D S PMOS Si Uniaxial III-V Uniaxial Tri-Gate G strain High-k Strain 1.2nm thin gate oxide 1.2nm thin Si Substrate 5 nm gate oxide Semiconductor Focus of this talk: emerging 5 nm Nanowire Carbon Nanotube nanoelectronic devices 3 Note: Future options subject to change Experimental 10nm Si MOS Transistor

Source: R. Chau et. al., Intel Corp., 61st DRC, June 2003

m]m] 0.75V µµ 600 0.65V 0.55V

400 0.45V

200

DRAIN CURRENT CURRENT [A/ [A/ DRAIN DRAIN 0 0 0.2 0.40.6 0.6 0.8 DRAIN VOLTAGE [V]

LG = 10nm Si

ƒ 10nm Si transistors produced in research labs − Still a switch with gain ƒ Need to benchmark emerging non-Si nanoelectronic research devices versus state-of-the-art Si research transistors 4 Review of High-K Physics on Si

Poly-Si Gate TCAD Simulation* Metal Gate

EG EG

High-K High-K dielectric

ELO ELO Mob ilit y di E’LO E’G p E’LO E’G

ETOT=E’LO+E’G ETOT=E’LO-E’G Si channel Si channel EGATE-PLASMON ELO Poly-Si gate Metal gate E (off resonance) (In resonance) TO

• High-K phonons and gate plasmons modeled as electric dipoles

18 -3 • Doped polySi gate (~10 cm ): When ETO < EGATE-PLASMON < ELO, in-resonance condition occurs which degrades channel mobility • Metal gate (>1020 cm-3): Off-resonance condition weakens phonon- carrier coupling, hence channel mobility is recovered 5 * Source: R. Kotlyar et. al., Intel Corp., IEDM 2004 Review of High-K Physics on Si

Experimental Measurements Inverse Modeling 4.5E-05 1200 Channel 4.0E-05 Si/High-K/PolySi 1000 mobilityP860 3.5E-05 800 Si/SiO2/PolySi

3.0E-05 /V.s) 2 Phonon scattering 600 2.5E-05 (cm 400 Si/High-K/Metal-Gate 2.0E-05 Si/SiO2/PolySi d(1/ueff)/dT 200 Si/High-K/PolySi 1.5E-05 T = 25 C 0 1.0E-05 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 0 0.5 1 1.5

Effective Vertical Field (MV/cm) Limited Mobility Phonon Surface Effective Vertical Field (MV/cm)

• Surface phonon scattering in high-K is primary source of mobility degradation • Metal gate is effective for screening phonon scattering and improves channel mobility

Source: R. Chau et. al., Intel Corp., IEEE EDL, June 2004 6 Review of High-K Physics on Si + P Poly-Si/SiO2 5.15 P-type Metal on High-K SDK 4.95

4.75 Mid-gap Metals on High-K

4.55

4.35 NDK N-type Metal on High-K WORKFUNCTIONWORKFUNCTION [eV] [eV] + 4.15 N Poly-Si/SiO2 4.05 polypoly polypoly + + + + MetalMetal J J MetalMetal I I MetalMetal F F MetalMetal D D PP MetalMetal H H MetalMetal A A MetalMetal E E NN MetalMetal G G MetalMetal B B MetalMetal C C P-metalP-metal N-metal N-metal

GATE ELECTRODE MATERIALS • Gate electrodes with the “right” work function are required for high-performance CMOS applications 7 Source: R. Chau, Intel Corp., AVS ICMI, March 2004 Review of High-K Physics on Si

• Example of high-performance CMOS transistors on bulk- with high-K/metal-gate

– Correct VTH’s, high-mobility, low gate

Source: R. Chau et. al., Intel Corp., IEEE EDL, June 2004 8 Conventional Planar and Non-Planar Si Transistors NMOS 1.5 NMOS 70nm Si Planar (VCC=1.3V) [Poly/SiO2] 1.2

60nm Si Tri-Gate (VCC=1.3V) Si Planar [Poly/SiO2] 0.9 Si Tri-Gate 40nm Si Planar (VCC=1.1V) 0.6 [Poly/SiO2]

0.3

GATE DELAY CV/I [ps] 35nm Si Tri-Gate (VCC=1.1V) NMOS [High-K/metal-gate] 0 1E+0 1E+1 1E+2 1E+3 1E+4 1E+5

ION / IOFF Si Planar ƒ Need to benchmark emerging non-Si Si Tri-Gate nanoelectronic devices versus these conventional planar and non-planar Si NMOS transistors 9 Conventional Planar and Non-Planar Si Transistors

PMOS PMOS 2.5

70nm Si Planar (VCC=1.3V) 2.0 Si Planar [Poly/SiO2]

1.5 40nm Si Planar (V =1.1V) Si Tri-Gate CC [Poly/SiO2] 1.0

0.5

GATE DELAY CV/I [ps] 35nm Si Tri-Gate (VCC=1.1V) [High-K/metal-gate] PMOS 0.0 1E+0 1E+1 1E+2 1E+3 1E+4 1E+5

ION / IOFF SiSi Planar Planar ƒ Need to benchmark emerging non-Si nanoelectronic devices versus these Si Tri-Gate conventional planar and non-planar Si

PMOS transistors 10 Emerging Nanoelectronic Devices

(a) (d) Drain (c) 2.0 nm High-K Gate III-V (Pd) Source Drain CNT Source 5.0 nm Source SingleDrain -wall Si Nanowire Drain D = 1.4 nm Source Gate L = 75 nm (Pt) Multi g Si L = 10 nm epitaxial g Gate Source body 5 nm Gate III-Vlayers layers • Semiconductor • Carbon nanotube FETs • III-V quantum-well (Q-W) nanowires with with high-K gate transistors (high-K gate high-K gate dielectrics dielectric is currently absent in III-V but required Role of High-K/metal-gate: for logic applications) – enabling continued equivalent gate oxide thickness scaling and hence high performance, and controlling gate leakage 11 – required for high ION/IOFF ratios in III-V Q-W devices for logic Intrinsic Gate Delay CV/I for PMOS

D = 1 to 2.5nm D = 4 to 35nm

• CNT shows significant p-ch CV/I improvement over Si – CNT has >20X higher effective p-ch mobility than Si

• Si nanowires currently do not show improvement over12 Si Energy-Delay Product for PMOS

13 Carbon Nanotube (CNT) p-FET with High-K/Metal-Gate

Drain current

(ID) Source current

(IS)

Gate leakage (IG)

ƒ CNT FET exhibits low leakage with the use of high-K ƒ Ambipolar leakage identified as the major source of parasitic leakage in CNT (due to metal-CNT Schottky S/D contacts) 14 Capacitance of High-K/Metal-Gate on Carbon Nanotubes (CNT)

D=2R CNT

High-K Dielectric TPHYS Metal Gate

−1 −1 −1 C TOTAL = COX + CQM 2πε K C = 0 OX  R + T  ln2 PHYS   R 

CQM ~ 400 aF / µm *

* Guo et al, Applied Physics Letters 2002

ƒ High-K dielectric constant has a stronger effect than high-K dielectric thickness in increasing gate capacitance of carbon nanotube FETs 15 CV/I versus ION/IOFF Ratio

50nm CNT p-FET (VCC=0.3V) [Metal-CNT S/D contacts 80nm CNT n-FET (Vcc=0.5V) cause ambipolar conduction] [Chemically-doped junction delays ambipolar conduction]

70nm Si PMOS (VCC=1.3V)

40nm Si PMOS (VCC=1.1V)

35nm Si Tri-Gate PMOS (VCC=1.1V)

ƒ For ION/IOFF < 100, CNT p-FET shows improvement over Si due to higher channel mobility and lower VCC used

ƒ Highest ION/IOFF ratio in CNT limited by ambipolar conduction due to metal-CNT S/D contacts; chemically-doped junctions delays ambipolar conduction despite poor CV/I performance 16 Physics of Silicon Nanowires

TCAD Simulation (R. Kotlyar, Intel, APL 2004) Measurements Increasing temperature 15nm 9nm 5nm 3nm

Room Temp.

• Previous understanding: Reducing wire diameter reduces available density of states for elastic scattering (1D), thus improving mobility • Current understanding of Si nanowires – Impact of phonon scattering becomes significant above 50 K – Mobility at room temperature decreases with reducing diameter (< 10nm) due to phonon scattering – Performance of Si nanowires limited by phonon scattering at room temp 17 Intrinsic gate delay CV/I for NMOS

• n-channel CNT not as well established as p-channel CNT • III-V (e.g. InSb) devices show significant CV/I improvement over Si – III-V devices have >50X higher effective n-ch mobility than Si 18 – III-V devices operated at low VCC = 0.5V Energy-Delay Product for NMOS

19 III-V Transistors for Low VCC 180 0.5V 1.2V 160 SOURCE 140 InSb QWFET 0.3V DRAIN (LG=200nm) 120 Si NMOS 100 (LG=80nm) 80 DRAIN GATE InSb Vds=0.3V 60 5-10X InSb Vds=0.5V InSb Vds=0.6V 40 Lower Power InSb Vds=0.7V Si Vds=0.5V III-V (InSb) Cutoff Frequency, fT (GHz) Cutoff Frequency, Dissipation Si Vds=0.7V 20 Si Vds=1V Q-W Transistor Si Vds=1.2V 0 (Schottky metal 1 10 100 1000 gate with no Power Dissipation (mW/mm) gate dielectric) CV C WLV C WL L 1 = 0 = 0 = = I I gm v eff 2πfT 20 Source: Intel & QinetiQ, ICSICT, Oct 2004 IIIIII--VV Nanoelectronics:Nanoelectronics: EnergyEnergy--DelayDelay ProductProduct vsvs DeviceDevice GateGate LengthLength

n-FET

Si InSb/AlInSb

Quantum-well/ Barrier InSb

• InSb QW-FETs have the lowest NMOS energy-delay product

(highest mobility and lowest operating VCC) 21 IIIIII--VV Nanoelectronics:Nanoelectronics:

HighHigh--KK RequiredRequired toto EliminateEliminate SchottkySchottky IIGATE m] µ

QWFET VDS=0.5V 1 High electron Non Self-aligned Schottky Barrier mobility InSb Ohmic contacts Metal quantum well V =50mV I DS Higher band-gap 0.1 DS matrix AlxIn1-xSb for Remote reduced junction Doping leakage Layers

0.01 metamorphic AlInSb buffer layer VDS=0.5V s.i. GaAs substrate for epitaxial growth 0.001 Schottky VDS=50mV

Drain and Gate Current [mA/ IGATE 0.0001 -0.8 -0.6 -0.4 -0.2 0 Gate Voltage, V GS [V] Requires a gate stack to eliminate Schottky I , e.g. high-K/metal-gate GATE 22 Source: Intel & QinetiQ, ICSICT, Oct 2004 IIIIII--VV Nanoelectronics:Nanoelectronics:

HighHigh--K/MetalK/Metal--GateGate RequiredRequired toto ImproveImprove IION/I/IOFF

n-FET

Due to Schottky Gate leakage

• ION /IOFF ratio of InSb QWFET is limited by Schottky gate leakage 23 One of the Grand Challenges in III-V Nanoelectronics for logic: Compatibility of III-V and High-K/Metal-gate Stack III-V/High-K/metal-gate

on III-V

High-K

High-K/metal-gate

1E-6 on III-V

8E-7

Fast Surface 6E-7 [F/cm²]

G 4E-7 States C 2E-7 -1 -0.5 0 0.5 1 VG [V]

24 Summary

ƒ High-K/metal-gate will be one of the key enablers for emerging non-Si nanoelectronic devices for future potential high-performance, low-power logic applications ƒ High-K/metal-gate stacks are required for improving the Ion/Ioff ratio of III-V quantum-well transistors for future potential low-power, high-speed logic applications

25