NANO-ELECTRO-MECHANICAL SWITCH (NEMS) FOR ULTRA-
LOW POWER PORTABLE EMBEDDED SYSTEM APPLICATIONS
ANALYSIS, DESIGN, MODELING, AND CIRCUIT SIMULATION
By
KHAWLA ALZOUBI
Submitted in partial fulfillment of the requirements
For the degree of Doctor of Philosophy
Dissertation Advisor: Prof. Daniel Saab
Dissertation Co-Advisor: Prof. Massood Tabib-Azar
Department of Electrical and Computer Science
CASE WESTERN RESERVE UNIVERSITY
AUGUST, 2010
CASE WESTERN RESERVE UNIVERSITY
SCHOOL OF GRADUATE STUDIES
We hereby approve the dissertation of
Khawla Alzoubi
candidate for the Ph.D degree*.
(signed) Daniel Saab
(chair of committee)
Massood Tabib-Azar
Francis “Frank” Merat
Michael Rabinovich
(date) June, 30, 2010
* We also certify that written approval has been obtained for any proprietary
material contained therein.
DEDICATION
To my husband who keeps encouraging and helping me to achieve my goals.
TABLE OF CONTENTS
CASE WESTERN RESERVE UNIVERSITY ...... ii
SCHOOL OF GRADUATE STUDIES ...... ii
DEDICATION ...... iii
TABLE OF CONTENTS ...... iv
LIST OF TABLES ...... xiv
LIST OF FIGURES ...... xv
ABSTRACT ...... xxii
Chapter 1 : I NTRODUCTION ...... 1
1.1. MOTIVIATION ...... 1
1.2. THESIS OVERVIEW ...... 4
Chapter 2 : CMOS TECHNOLOGY SCALING AND LIMITATIONS ...... 8
INTRODUCTION ...... 8
2.1. SCALING CMOS TECHNOLOGY ...... 8
2.2. TRADITIONAL CMOS SCALING ...... 9
2.2.1. ADVANTAGES OF TRADITIONAL SCALING ...... 10
2.2.1.1. Transistor Density ...... 10
2.2.1.2. Performance ...... 11
2.2.1.3. Dynamic Power ...... 12
2.2.2. TRADEOFFS OF TRADITIONAL SCALING ...... 15
2.2.2.1. Physical Perspective ...... 16
2.2.2.2. Device Perspective ...... 17
2.2.2.3. Circuit Perspective ...... 25
2.3.NEW TRENDS IN CMOS TECHNOLOGY ...... 29
2.3.1.CIRCUIT TECHNIQUES ...... 30
2.3.1.1. Power Dissipation: Issues & Circuit Techniques ...... 30
2.3.2. DEVICE OPTIMIZATION TECHNIQUES ...... 33
2.4. FUTURE TECHNOLOGY TRENDS USING EMERGING
TECHNOLOGIES ...... 34
SUMMARY ...... 36
Chapter 3 : MEMS/NEMS BACKGROUND ...... 37
INTRODUCTION ...... 37
3.1. MEMS/NEM TECHNOLOGY ...... 37
3.2. MEMS VERSUS NEMS ...... 38
3.2.1. CHARACTERSTICS ...... 38
3.2.2. PHYSICS ...... 39
3.2.3. MANUFACTURING ...... 40
3.2.3.1. TOP DOWN APPROACH (FABRICATED) ...... 40
3.2.3.2. BOTTOM-UP APPROACH (SYNTHESIZED) ...... 41
3.3. NEMS STRCTURES ...... 41
3.4. MEMS/NEMS OPERATION MODES ...... 42
3.4.1. SWITCHING MODE (QUASI-STATIC) ...... 43
3.4.1.1. Capacitive Switch ...... 43
3.4.1.2. Ohmic Contact Switch (Resistive Switch) ...... 43
3.4.2. RESONANT MODE (ACOUSTIC) ...... 44
3.5. MEMS/NEMS PHYSICAL ACTUATION PRINCIPLES ...... 44
3.6. MEMS/ NEMS MATERIALS ...... 46
3.7. MEMS/NEMS COMPUTATIONS ...... 46
Chapter 4 : LITERATURE REVIEW ...... 48
INTRODUCTION ...... 48
4.1. ELECTROSTATIC MECHANICAL SWITCHES ...... 48
4.2. ELECTROSTATIC MECHANICAL SWITCHES AS AN EMERGINIG
TECHNOLOGY ...... 49
4.3. LITERATURE REVIEW ...... 50
4.3.1. ACTIVE PART‘S MATERIAL ...... 58
4.3.2. FABRICATION APPROACHES ...... 58
4.3.3. VALIDATION/EVALUATION ...... 59
4.3. KEY CRITERIA TO CONSIDER NEMS SWITCHES AS AN EMERGING
TECHNOLOGY ...... 62
Chapter 5 : ELECTROSTATIC NEMS SWITCHES: CONCEPTS,
ANALYSIS, AND DESIGN ...... 67
INTRODUCTION ...... 67
5.1. PRINCIPLE OF OPERATION ...... 67
5.2. MULTI-PHYSICS DEVICE ...... 68
5.3. NEMS PHYSICAL QUANTITIES ...... 70
5.4. NEMS PHYSICAL PHENOMENA ...... 70
5.4.1 ELASTIC FORCE ...... 71
5.4.2. ELECTROSTATIC FORCE ...... 71
5.4.3. INTERMOLECULAR FORCES ...... 72
5.4.4. CONTACT FORCE ...... 73
5.4.4.1. Elastic Deformation ...... 74
5.4.4.2. Plastic Deformation ...... 75
5.4.4.3. Elastic-Plastic Deformation ...... 75
5.4.5. DAMPING FORCE ...... 76
5.4.5.1. Viscous Damping ...... 77
5.4.5.2. Compression Damping ...... 78
5.4.6. KINETIC FORCE ...... 79
5.4.7. CONTACT BOUNCING MOTION PHENOMENA ...... 79
5.5. NEMS CHARACTERSTICS ...... 79
5.5.1. PULL-IN AND PULL-OUT VOLTAGES ...... 79
5.5.2. SWITCHNIG TIME ...... 81
5.5.3. ON AND OFF RESISTANCES ...... 82
5. 5.3.1. OFF Resistance ...... 82
5.5.3.2. ON Resistance ...... 83
5.5.4. RELIABILITY ISSUES ...... 85
5.5.4.1. Stiction ...... 86
5.5.4.2. Wear ...... 88
5.6. NEMS PRODUCTION PROCESS ...... 90
5.7. NEMS SWITCH DESIGN PHASE ...... 92
5.7.1. NEMS SWITCH DESIGN: OBJECTIVE AND DECISION ...... 92
5.7.2. NEMS DESIGN APPROACHES ...... 93
5.7.3. NEMS DESIGN STEPS USING THE FEA SIMULATION TOOL ..... 95
Chapter 6 : FABRICATED TWO-TERMINAL TUNING FORK NEMS
SWITCH ...... 100
INTRODUCTION ...... 100
6.1. TWO-TERMINAL TUNING FORK (Ni-Ni) NEMS SWITCH ...... 101
6.2. TWO-TERMINAL TUNIG FORK NEMS SWITCH FABRICATION ..... 102
6.3. DEVICE CHARACTERSTICS ...... 104
6.3.1. OPERATION VOLTAGE ...... 105
3.2. LEAKAGE CURRENT ...... 106
6.3.3. ON RESISTANCE ...... 107
6.3.4. SWITCHNIG SPEED ...... 107
6.3.5. FOOTPRINT SIZE ...... 108
6.3.6. SWITCH LIFE TIME ...... 109
6.4. 3D FEA PHYSICAL DEVICE MODEL ...... 109
6.5. VERIFICATION ...... 113
6.6. DEVICE MACROMODLE (CIRCUIT SIMULATION MODEL) ...... 114
6.6.1. MECHANICAL LUMPED MODEL ...... 114
6.6.2. ELECTRICAL CIRUIT MODEL ...... 116
6.6.2.1. Electrical circuit model in the Switching/OFF state ...... 116
6.6.2.2. Electrical Circuit Model in the ON state ...... 117
SUMMARY ...... 119
Chapter 7 : FOUR-TERMINAL NEMS SWITCH: DESIGN, LOGIC
REALIZATION, AND MODELING APPROACH ...... 120
INTRODUCTION ...... 120
7.1. FOUR-TERMINAL NEMS SWITCH DESIGN ...... 120
7.2. NNEMS AND PNEMS CONFIGURATIONS ...... 123
7.3. CNEMS BASIC LOGIC GATES AND SEQUENTIAL CIRUIT ...... 124
7.3.1. CNEMS INVERTER ...... 125
7.3.2. CNEMS NOR ...... 125
7.3.3. CNEMS NAND ...... 127
7.3.4. CNEMS D-LATCH ...... 128
7.4. WORK OVERVIEW ...... 129
7.5. MODELING APPROACH ...... 130
Chapter 8 : 3D FEA PHYSICAL DEVICE MODEL ...... 133
INTRODUCTION ...... 133
8.1. 3D FEA PHYSICAL DEVICE MODEL ...... 133
8.2. MODELING NEMS SWITCH‘S CHARACTERSTICS USING 3D FEA
PHYSICAL DEVICE MODEL ...... 136
8.2.1. PULL-IN VOLTAGE ...... 136
8.2.2. VAN DER WAALS FORCE ...... 137
8.2.3. ELECTROSTATIC FORCE ...... 139
8.2.4. CAPACITANCES ...... 139
8.2.5. MECHANICAL ENERGY AND ELECTRICAL ENERGY ...... 141
8.2.6. TUNNELING LEAKAGE CURRENT ...... 141
8.2.7. SWITCHNIG TIME ...... 143
8.2.8. DAMPING FORCES ...... 145
8.2.9. CONTACT AREA AND CONTACT RESISTANCE...... 148
8.2.10. NATURAL FREQUENCIES ...... 149
8.2.11. RESONANT FREQUENCY ...... 150
8.3. MECHANICAL DEVICE COEFFICIENTS EXTRACTION ...... 151
8.3.1. EFFECTIVE STIFFNESS CONSTANT (keff) ...... 152
8.3.2. EFFECTIVE MASS (meff) ...... 153
8.3.3. DAMPING COEFFICIENTS (cd, kd) ...... 154
8.4. DEVICE COEFFICIENTS (keff, meff, cd, kd): 3D FEA PHYSICAL MODEL
VERSUS ANALYTICAL EQUATIONS ...... 155
SUMMARY ...... 157
Chapter 9 : DEVICE MACROMODEL ...... 158
INTRODUCTION ...... 158
9.1. DEVICE MACROMODEL VERSUS 3D FEA PHYSICAL DEVICE
MODEL ...... 158
9.2. DEVICE MACROMODEL ...... 159
9.2.1. MECHANICAL LUMPED MODEL ...... 160
9.2.2. ELECTRICAL CIRUIT MODEL ...... 163
9.2.2.1. Electrical Circuit model in the Switching/OFF State ...... 163
9.2.2.2. Electrical Circuit Model in the ON State ...... 166
9.3. VERIFICATION OF THE DERIVED DEVICE MACROMODLE ...... 168
SUMMARY ...... 171
Chapter 10 : CNEMS CIRCUIT SIMULATION ...... 172
INTRODUCTION ...... 172
10.1. MOTIVATION BEYOND THE CIRUIT SIMULATOR ...... 172
10.2. CIRCUIT SIMULATOR ARCHITECTURE ...... 173
10.2.1. NETWORK TOPOLOGY AND SETUP ...... 174
10.2.2. MATHEMATICAL MODELS ...... 175
10.2.3. CIRCUIT SIMULATOR ENGINE ...... 177
10.3. CIRUIT SIMULATOR IMPLEMENTATATION ...... 177
10.3.1. READING A CIRUIT DESCRIPTION ...... 178
10.3.2. FORMULATING SYSTEM OF EQUATIONS ...... 179
10.3.3. SOLVING SYSTEM OF EQUATIONS ...... 182
10.3.4. TRANSIENT ANALYSIS SOLUTION ...... 183
10.4. CNEMS BASIC LOGIC GATES AND D-LATCH EVALUATIONS .... 185
10.4.1. CNEMS INVETER ...... 185
10.4.2. CNEMS NAND GATE ...... 186
10.4.3. CNEMS NOR GATE ...... 187
10.4.4. CNEMS D-LATCH ...... 189
10.5. CNEMS 1-BIT FULL ADDER EVALUATION ...... 190
SUMMARY ...... 193
Chapter 11 : CNEMS POWER SAVING AND CNEMS APPLICATIONS .. 194
INTRODUCTION ...... 194
11.1. CNEMS POWER EVALUATION ...... 194
11.2. DIGITAL CNEMS CIRCUITS DESIGN ...... 196
11.3. CNEMS POWER ADVANTAGES ...... 197
11.4. APPLICATIONS ...... 199
SUMMARY ...... 200
Chapter 12 : CONCLUSIONs and summary of contributions ...... 201
APPENDIX A: POWER METRIC VERSUS ENERGY METRIC...... 209
A.1 POWER METRIC ...... 209
A.2 ENERGY METRIC ...... 210
A.3 VLSI APPLICATIONS ...... 211
LIST OF TABLES
Table 2.1: Leakage currents in different states [7] ...... 17
Table 2.2: Leakage mechanisms due to high field electrons [7] ...... 22
Table 2.3: Prediction of the development of the subthreshold current Isub, the ...... 23
Table 3.1: Comparison between MEMS and NEMS [35] ...... 39
Table 3.2: Comparison between actuation mechanisms in MEMS devices [42] [37]
...... 46
Table 5.1: Comparison between Van der Waals force and Casimir force [64] ...... 73
Table 6.1: 3D FEA physical device model‘s measurements for the two-terminal tuning fork Ni-Ni NEMS switch ...... 110
Table 6.2: The device‘s pull-in voltage and resonant frequency ...... 113
Table 6.3: The extraction of the mechanical coefficients from the 3D FEA physical device model ...... 115
Table 6.4: Characteristics of the two-terminal NEMS switch ...... 118
Table 7.1: The four-terminal NEMS switch material properties ...... 121
Table 8.1: Mechanical Device Coefficients ...... 156
Table 9.1: Characteristics of the four-terminal NEMS switch ...... 168
Table 10.1: Constitutive Equations (BCE) for basic elements ...... 176
Table 10.2: MNA stamps matrices for basic circuit elements in transient mode ... 182
Table 11.1: iscas85 benchmark circuits power evaluations ...... 198
Table 11.2: iscas89 benchmark circuits power evaluations ...... 198
LIST OF FIGURES
Fig 2.1 2: The number of transistor per chip increases every node generation according to Moor‘s law. Intel [3] ...... 11
Fig 2.2: The computation power (MIPS) per chip according to Moore‘s law. Intel
[4] ...... 12
Fig 2.3: The MPs power consumption. Source: Borkar, De Intel [5] ...... 15
Fig 2.4: Tradeoffs of traditional scaling CMOS technology in submicron regime .. 16
Fig 2.5: Leakage currents in MOS transistor [7] ...... 18
Fig 2.6: The subthreshold current leakage (VGS=0) for different node generations with increasing the ambient temperature from 30o to 110. Courtesy of Vivek De,
Intel[8] ...... 19
Fig 2.7: The subthreshold current versus the threshold voltage [5] ...... 19
Fig 2.8: Threshold voltage versus the effective channel length [7] ...... 20
Fig 2.9: The effect of increasing the VDS on long and short channel [4] ...... 21
Fig 2.10 [10]:a) Gate overdrive variation with temperature at the nominal supply voltage b) Mobility variation with temperature at the nominal supply voltage ...... 24
Fig 2.11: a) The dynamic and leakage power dissipation for different feature size
(250nm – 45 nm) b) Power density for MPs generations Source: Borkar, De Intel [9]
...... 27
Fig 2.12: Cost of lithogrphytool per year[11] ...... 28
Fig 2.13: End of traditional scaling era that last ~40 years ~2003[3] ...... 29
Fig 2.14: Material and structure innovations for the current CMOS technology [18]
...... 33
Fig 2.15:a) the improvement of the device performance with using device optimization) techniques as well as scaling the device dimensions [3] b) the suppression of the gate leakage in the 45 nm technology over the 65nm technology in SRAM cell[23] ...... 34
Fig 3.1: Fundamental theories in electromechanical systems ...... 40
Fig 3.2: Cantilever beam structure [38] ...... 42
Fig 3.3: Bridge (fixed-fixed beam) structure [38] ...... 42
Fig 5.1: Electrostatic NEMS switch: physical quantities, physical phenomena, and device characteristics ...... 69
Fig 5.2: NEMS production process ...... 91
Fig 5.3: NEMS switch design phase ...... 93
Fig 5.4: NEMS design flowchart ...... 98
Fig 6.1: Schematic of the two-terminal tuning fork NEMS switch ...... 101
Fig 6.2: Schematic of the fabrication process for metallic Nano-Electro-Mechanical switches (NEMS) on silicon substrate ...... 102
Fig 6.3: SEM picture for the two-terminal tuning fork NEMS switch ...... 104
Fig 6.4: The advantages of using two movable beams in the two-terminal tuning fork NEMS switch a) Voltage advantage of using two movable beams over one movable beam b) Switching speed ...... 105
Fig 6.5: Two-terminal tuning fork NEMS switch IV characteristic ...... 107
Fig 6.6: Switching/oscillation of the nickel device in the feedback loop of low noise RF amplifier. The bottom trace is the oscillation spectrum clearly showing the fundamental around ~1GHz and switching harmonics ...... 108
Fig 6.7: Mechanical lumped model ...... 116
Fig 6.8: Electrical circuit model for the two-terminal tuning fork NEMS switch in the OFF/switching state...... 117
Fig 6.9: The electrical circuit model for the Two-terminal tuning fork NEM switch in the ON state ...... 118
Fig 7.1: The four-terminal NEMS switch: dimensions and structure ...... 122
Fig 7.2: Four-terminal NEMS switch configurations a) Schematic for N-Channel
(NNEMS) b) Schematic for P-Channel (PNEMS) ...... 124
Fig 7.3: CNEMS INVERTER ...... 125
Fig 7.4: CNEMS NOR ...... 126
Fig 7.5: CNEMS NAND ...... 127
Fig 7.6: CNEMS D-latch ...... 128
Fig 7.7: Circuit simulation model ties the gap between the physical device and the architecture ...... 129
Fig 7.8: NEMS Switch Modeling Approach ...... 132
Fig 8.1:Structure for the 3D FEA physical device model of the four-terminal NEMS switch ...... 135
Fig 8.2: The Gaps [nm] between the movable parts‘ tips with sweeping the applied voltage [V] between the Body and the Gate of the four-terminal NEMS switch a)
Pull-in Without considering Van der Waals force b) With considering Van der
Waals force ...... 137
Fig 8.3: The simulated Van der Waal‘s force on the movable beam (Body) surfaces that is prone to this force...... 138
Fig 8.4: The electrostatic force that is generated on movable beam (Body) versus the applied voltage difference between the Body and the Gate ...... 139
Fig 8.5: Capacitance between the Body and the Gate and The capacitance between the Body and the Drain/Source versus the applied voltage between the Body and the
Gate ...... 140
Fig 8.6: The mechanical and electrical energy for the four-terminal NEMS switch based the 3D FEA physical model ...... 141
Fig 8.7: The Simulated tunneling current [A] between the Body and the
Drain/Source versus the applied voltage difference [V] ...... 143
Fig 8.8: The switching time when the applied voltage between the Body and the
Gate is equal to the device‘s pull-in voltage a) Without considering Van der Waals force b) With considering Van der Waals force ...... 145
Fig 8.9: Squeeze film damping forces on each movable beam: (a) The viscous damping force (b) The elastic damping force ...... 147
Fig 8.10: Knudsen number for changing the gaps versus the time ...... 147
Fig 8.11: The contact Area between the Body and the Drain/Source versus the applied voltage between the Body and the Gate ...... 148
Fig 8.12: the natural frequency for the Body beam (=0.4655 GHz) in the movement direction ...... 150
Fig 8.13: The natural frequency for the D-G-S beam (=0.4509 GHz) in the movement direction ...... 150
Fig 8.14: The simulated resonant frequency from the 3D FEA device model a) The
Body movable part b) The D-G-S movable part ...... 151
Fig 8.15: The derived effective stiffness constant for the Body beam (K1) and the
D-G-S beam (K2) ...... 153
Fig 8.16: Derived damping coefficients for each movable beam from the 3D FEA model a) Viscous damping coefficients b) Elastic damping coefficients ...... 155
Fig 9.1: NEMS Mechanical Lumped Model ...... 161
Fig 9.2: The electrical circuit model for the four-terminal NEMS switch in the
Switching/OFF state ...... 164
9 Fig 9.4: Gap versus time from the 3D FEA physical device model and from the device Macromodel ...... 169
Fig 9.5: Electrostatic force versus time from the 3D FEA physical device model and from the device Macromodel ...... 169
Fig 9.6: Van der Waals force from the 3D FEA physical device model and the device Macromodel ...... 170
Fig 9.7: Capacitances versus time from the 3D FEA physical device model and the device Macromodel ...... 170
Fig 10.1: Circuit simulator architecture ...... 174
Fig 10.2: Netlist for CNEMS NAND gate ...... 178
Fig 10.3: Link lists for CNEMS NAND gate a) Voltage source link list b) NEMS switch link list c) Resistor link list d) Capacitor link list e) CMOS transistor link list f) Current source link list ...... 179
Fig 10.4: Transient analysis flowchart ...... 184
Fig 10.5: CNEMS INVERTER a) Netlist description and schematic b) Simulation result ...... 186
Fig 10.6: CNEMS NAND Gate a) Netlist description and schematic b) Simulation results ...... 187
Fig 10.7: CNEMS NOR Gate a) Netlist description and schematic b) Simulation results ...... 188
Fig 10.8: CNEMS D-latch a) Netlist description and schematic b) Simulation results
...... 190
Fig 10.9: CNEMS 1-bit adder evaluation a) Netlist description b) Circuit evaluation c) Behavior ...... 192
ACKNOWLEDGMENTS
I would like to express the deepest appreciation for my advisor, Professor Daniel
Saab and my Co-advisor, Professor Massood Tabib-Azar, for their endless support, continues guidance, and great patience.
I would like to thank my committee members, Professor Francis ―Frank‖ Merat and
Professor Michael Rabinovich, for their time and valuable comments.
I would like to thank my family; my husband Khaled, my son Zaid, and my daughter Zeena; who shared these years with me and kept their patience.
Finally, I would like to thank all the people who helped me in direct and indirect ways to accomplish this work.
Thank you every one.
Nano-Electro-Mechanical Switch (NEMS) for Ultra-Low Power Portable
Embedded System Applications
Analysis, Design, Modeling, and Circuit Simulation
ABSTRACT
By
KHAWLA ALZOUBI
To overcome the excessive quiescent dissipation in Nanometer-CMOS technology, especially in portable embedded system computing where the energy efficiency, cooling system and environment changes are more important than the speed. In this work, I investigated a Nano-Electro-Mechanical Switch (NEMS) that offers novel characteristics in terms of virtually zero leakage current, low operating voltage ~1-1.2 V, high switching speed ~1-1.4 ns, and footprint size. Furthermore, this switch can be fabricated easily by using the modified CMOS fabrication process and equipment. These features make this switch a good candidate to address the energy efficiency problem in Nanometer-CMOS technology without extreme cost.
In this work, the NEMS switch that mentioned previously is studied. The study involves analysis, design, modeling, and building a circuit simulator. This switch is designed to mimic CMOS transistor‘s structure and configure to N-channel and P-
channel similar to NMOS and PMOS correspondingly in CMOS technology. Thus, the design of NEMS computational and sequential circuits can be expedited by using CMOS design concepts and CAD tools. This switch is designed to have simple structure that can be fabricated easily by using the modified CMOS fabrication process and equipment. In modeling this device, a new approach is developed to derive an accurate device circuit simulation model (Macromodel). In this approach, a Finite Element Analysis (FEA) physical device model is constructed. Using this FEA physical model and the fabricated device measurements, an accurate device circuit simulation model (Macromodel) is derived and calibrated. The derived Macromodel is capable of mimicking the physical device in a circuit environment in a circuit environment within average error is around 10% to the physical device model.
To evaluate an arbitrary NEMS circuit accurately, a circuit simulator is built.
The circuit simulator uses the derived circuit simulation model and the circuit simulation techniques.
Finally, to demonstrate the power advantage of using CNEMS technology in implementing computational and sequential circuits, circuit simulation experiments were conducted. The experimental results reveal significant improvements in reducing the quiescent power dissipation in CNEMS benchmark circuits over the counterpart Nanometer-CMOS benchmark circuit, moreover, improvements in reducing the active power dissipation in CNEMS circuits over Nanometer-CMOS is demonstrated.
CHAPTER 1 : I NTRODUCTION
1.1. MOTIVIATION
Quiescent power dissipation is becoming a crucial design parameter in nanometer-scale VLSI CMOS circuits, where excessive quiescent power dissipation can lead to excessive heat generation and reliability issues. Precisely, excessive quiescent power dissipation imposes two limitations on nanometer-scale CMOS applications: (1) Limited battery life for battery-powered systems in embedded system computing and (2) Inability of cooling systems to suppress the excessive heat generation.
The exponential growth of the quiescent power dissipation led to the end of the traditional scaling paradigm of CMOS technology around 2003. After this year, comprehensive efforts have been conducted to overcome this problem for later generations. The first approach was based on scaling the device size as well as using circuit solution techniques. This approach required significant circuit modification and performance overhead for leakage reduction. Furthermore, these circuit solution techniques mainly addressed the subthreshold leakage and ignored the gate and pn- junction leakage which are becoming comparable and possibly exceeding the subthreshold leakage with further pushing CMOS technology into the nanometer regime. Currently, CMOS technology trends to overcome the growing of problem of leakage power are based on novel device structures and materials as well as device scaling. Using this approach, Moore‘s law could be maintained for current and near
2 future technologies (45 nm, 32 nm, and 22nm). This approach has achieved significant advancements in reducing the leakage power, specifically the gate leakage. Even so, the leakage power still imposes limitations on nanometer-scale
CMOS VLSI circuits that are limited by their power efficiency, cooling system, and ambient environment changes.
The intrinsic physical limitations of CMOS technology, short-channel effects and leakage currents, will lead to unmanageable leakage power and reliability concerns with further scaling to the nanometer regime. If these problems are not solved, then the CMOS technology road map reaches its end.
Undoubtedly, there is a need to seek a new technology that is capable of working with current CMOS technology to suppress the excessive leakage power dissipation as well as one that can be reduced with device size for ULSI circuits that are limited by their power/energy efficiency, size, and ambient working environments. Such systems are network wireless sensors, some medical applications, and space applications.
Recently, many studies have been conducted to explore new technologies to overcome the intrinsic physical limitations of CMOS technology in the nanometer regime. Most of these technologies are based on nanotechnology materials and mechanisms. These technologies include: (1) Single Electron Transistors, (2)
Quantum Dots, (3) Resonant Tunneling Diode, (4) Spintronics, (5) Molecular
Devices, and (6) Carbon Nanotube. Generally, these technologies have limitations in terms of: (1) fabrication: the fabrication process could suffer from one or more of
3 these limitations: (a) cannot be controlled easily, (b) cannot be integrated seamlessly with CMOS process, and (c) cannot be fabricated in large numbers (2) cost: need new equipment and tools, and (3) logic gate realization is different than CMOS.
Thus, we cannot get benefits from what has been done in CMOS technology in terms of design concepts and CAD tools.
However, there is a need to a technology that offers the following specifications:
(1) it can suppress the leakage power dissipation without degrading its ON current,
(2) it can be easily controlled during the fabrication process and it can be fabricated in large numbers, (3) it can utilize CMOS fabrication tools, (4) it can be scaled down into the nanometer regime, and (5) it is immutable to process variations and to ambient variations. Such a technology that offers these specifications is Nano-
Electro-Mechanical Switch (NEMS) technology. Recently, significant advancements have been achieved in NEMS switches in terms of operating voltage, switching speed, and size. These NEMS switches could be used in implementing portable battery-powered systems in embedded system computing, where the battery life is the crucial design parameter and is more important than performance (speed).
A four-terminal NEMS switch is needed to implement logic gates and memory. This four-terminal NEMS switch should have the following specifications: (1) low operating voltage that is comparable to nanometer-scale CMOS voltage source, (2) low switching time on the order of nanoseconds, and (3) foot-print size. To take advantage of CMOS design concepts and system architectures, an N-channel and a
P-channel NEMS switch should be configured as an NCMOS and a PCMOS
4 respectively in CMOS technology. If such a device can be designed and fabricated, an accurate Macromodel that captures the physical phenomena of the device is needed. This Macromodel can be used to model the four-terminal NEMS switch in circuit environments to help in designing and evaluating NEMS circuits before fabrication. As this device can be configured to form N-channel and P-channel as in
CMOS technology, we can use all CMOS design concepts and CAD tools to expedite the design of digital NEMS VLSI systems. Furthermore, because this device has comparable operating voltage to nanometer-scale CMOS technology and its fabrication process is based on CMOS fabrication process, it can be easily integrated with CMOS technology in hybrid NEMS-CMOS circuits to manage the leaky Nanometer- CMOS transistors.
1.2. THESIS OVERVIEW
This work is based on the two-terminal NEMS switch that has been fabricated in Prof.Tabib-Azar‘s lab at Case Western Reserve University. This switch has demonstrated experimentally attractive switching characteristics in terms of turn on voltage ~1V, high switch-speed of ~1 GHz, footprint size, virtually zero leakage current in the OFF state, ~10 ohm ON resistance, and it has been demonstrated up to one billion hot switching cycles . Furthermore, this switch has been fabricated by using CMOS fabrication process and equipments.
5
To obtain the advantages of the switch, this work concentrates first on designing a four-terminal NEMS switch that inherits the fabricated device characteristics and can be fabricated using the same process. Thus, this switch is designed based on the fabricated device‘s design (material, structure, dimensions) by using multi-physics simulation tool. The designed switch has been designed to have four terminals. This switch is configured to N-channel and P-channel similar to
NMOS and PMOS in CMOS technology to form a Complementary NEMS
(CNEMS) technology. Secondly, this work models the four-terminal switch on three levels: (1) physical level using FEA multi-physics simulation tool, (2) 1D
Macromodel level, which is a coupling of a mechanical lumped model and an electrical circuit model, and (3) circuit level by building a circuit simulator that is capable of evaluating arbitrary NEMS circuits accurately in terms of behavior, timing, and power dissipation. Thirdly, the realization of CNEMS basic logic gates and basic sequential circuit (d-latch) is demonstrated. The demonstration will show that these circuits have been design by borrowing CMOS design concepts. These circuits will demonstrate the same counterpart CMOS behaviors. Lastly, the power efficiency of using CNEMS technology is demonstrated.
This dissertation is organized into chapters. Chapter 2 provides detailed background information about CMOS technology scaling paradigms and conventional scaling benefits and tradeoffs. This chapter also discusses CMOS technology trends to overcome the imposed limitations with scaling and how to keep Moore‘s law valid for current and future CMOS after the end of the
6 conventional scaling era. Finally, chapter 2 will discuss emerging technologies trends to overcome the intrinsic physical limitations of CMOS technology for future scaling. Chapter 3 provides an extensive discussion of MEMS/NEMS technology in terms of definition, applications, NEMS versus MEMS, structures, physics, materials, actuation principles, actuation operation modes, and MEMS/NEMS computation paradigms. Chapter 4 presents a literature review for previous and current works in NEMS switches, which have been proposed to be used in implementing logic gates and memories and reporting attractive switching characteristics. These works are presented in terms of: characteristics, material, structure, manufacturing technology, and evaluation methods for the claimed characteristics. Furthermore, the key criteria to consider for a NEMS switch as an emerging switching technology are highlighted. Chapter 5 addresses NEMS switches in terms of principle of work, and provides an essential analysis that must be understood in order to design, fabricate, and model a NEMS switch. This analysis includes the device‘s physical quantities, physical phenomena, characteristic, and reliability issues. Furthermore, this chapter discusses how to design a NEMS switch. Chapter 6 introduces the fabricated two-terminal tuning fork
NEMS switch in terms of fabrication steps, experimental measurements, FEA physical model, and device Macromodel. Chapter 7 serves as introductory chapter of the rest of this work. This chapter illustrates the four-terminal NEMS switch in terms of design, configurations, basic logic and sequential circuit realization, and modeling approach. Chapter 8 demonstrates the 3D FEA physical device model
7 four-terminal and how to use this model to derive the mechanical device coefficients. Chapter 9 shows how to derive an accurate circuit device Macromodel.
Chapter 10 discuses the circuit simulator program in terms of necessity, structure, and implementation. Chapter 11 demonstrates the power efficiency of CNEMS technology over Nanometer-CMOS technology. Finally, chapter 12 concludes this work.
CHAPTER 2 : CMOS TECHNOLOGY SCALING AND LIMITATIONS
INTRODUCTION
In this chapter, the following topics are discussed: (1) CMOS scaling: scaling paradigms, (2) traditional constant E-field scaling: benefits, tradeoffs, and circuit technique solutions, (3) current technology trends in scaling using a CMOS device optimization approach, and (4) future and emerging technological trends.
2.1. SCALING CMOS TECHNOLOGY
In 1965, Moore was the first to predict that innovations in technology would allow for doubling the number of transistors in a given space in every node generation1 (2- 3 years) and that each time the transistor size shrinks, integrated circuits (ICs) become cheaper and perform better [1].
Historically, Moore‘s law has driven the technology to produce miniaturization processors and Systems-On-Chip (SOCs) with high functionalities, high performance, and low prices.
A CMOS transistor could be scaled either by using a constant E-field scaling paradigm or by using a constant voltage scaling paradigm. These scaling paradigms are defined below.
1) Constant Electrical-field Scaling
In this paradigm, all the device‘s dimensions, including channel length L, width
W, and oxide thickness, are reduced by a factor of 1/S. The supply voltage VDD and
9 the threshold voltage are reduced by 1/S. The substrate doping NA is increased by S.
Consequently, as a result of equally scaling the device‘s dimensions and voltages, the electrical field remains constant. This scaling approach has the desirable effect where many nonlinear factors essentially remain unaffected [2].
2) Constant Voltage Scaling (Lateral Scaling)
In this paradigm, only the channel length is scaled, leaving the other dimensions, voltages, and doping levels unchanged. This offers a quadratic improvement in gate delay at the expense of increasing the electrical fields in the device [2].
The International Technology Roadmap and Semiconductor (ITRS), driven by
Moore‘s law, forecasts a major new technology generation approximately every three years with scaling factor S= .
2.2. TRADITIONAL CMOS SCALING
By the 1um generation, velocity saturation was severe enough that decreasing feature size no longer improved device current. Furthermore, device breakdown voltage from the high electrical field was another risk [2]. Therefore, the constant field scaling has been the traditional scaling paradigm for almost four decades.
Scaling CMOS technology has achieved significant advancements in minimizing the device‘s size, boosting the device‗s speed, and reducing the device‘s dynamic energy. But the high power dissipation, quiescent power, and the reliability
10 concerns are the tradeoffs for the further pushing CMOS technology into the submicron regime.
The following subsections provide detailed explanations of the acquired benefits and the tradeoff limitations of the traditional scaling CMOS technology into the submicron regime and circuit techniques and solutions to reduce the power dissipation.
2.2.1. ADVANTAGES OF TRADITIONAL SCALING
In this subsection, the advantages of traditional scaling are discussed in terms of: transistor density, performance, and dynamic power dissipation.
2.2.1.1. Transistor Density
Transistor density is the number of logic transistors in a unit of area. By scaling all the device dimensions by a factor of 1/ , the transistor density is increased by a factor of 2. Thus, a double number of transistors occupy the same area. Consequently, more functions are implemented in a smaller area. Fig 2.1 shows that the number of transistors was doubled every node generation [3], and it was expected that the number of transistors in a chip would follow the same trend if
Moore‘s law could be maintained.
11
K 1 Billion Transistor
1,000,000
100,000 Pentium Pro Processor 10,000 Pentium Processor 1,000 i486 100 i386 80286 10 8086 1
1975 1980 1985 1990 1995 2000 2005 2010 2015 Projected
Fig 2.1 2: The number of transistor per chip increases every node generation according to Moor’s law. Intel [3]
2.2.1.2. Performance
The performance of a system can be analyzed by examining its delay. By scaling the device dimensions and voltages by a factor of 1/ , the gate delay is reduced by 30% according to equation (2.1), where L is the effective channel length
, is the carrier mobility, and VDS is the voltage difference between the drain and the source. Consequently, the overall system performance is enhanced. The system delay could be computed by using equation (2.2), where C is the summation of all switching capacitors, and Isat is the saturation current in the saturation region(VDS >
VGS-Vt) . The saturation current is computed by equation (2.3), where the oxide capacitance per unit area and W is the transistor width [2]. Accordingly, the overall system delay is reduced. Fig 2.2 shows that the computation speed is increased
12 every node generation. And it was expected that the computation speed would follow the same trend if Moore‘ law could be maintained.
(2.1)
(2.2)
(2.3)
MIPS 1,000,000 100,000 MIPS
1,00,000
10,000
1,000 Pentium Pro Processor 100 Pentium Processor i486 10 i386 80286 1 8086 0.1
1975 1980 1985 1990 1995 2000 2005 2010 2015 Projected
Fig 2.2: The computation power (MIPS) per chip according to Moore’s law. Intel [4]
2.2.1.3. Dynamic Power
Logic circuits are either working in a standby mode or in an active mode. In standby mode, CMOS logic circuits have no pending tasks to perform. In an ideal case, with the assumption that the transistor is an ideal switch and it is fully charged or discharged, there is no power dissipation in
13 this mode. In active mode, CMOS logic circuits are operating at frequencies and working on a given set of tasks. The consumed power in this mode is called active power. In an ideal case, with the assumption that the transistor is an ideal switch, the active power is a function of the dynamic power. The dynamic power has two components: switching power and short path power as expressed in equation (2.4).
(2.4)
The switching power is the power that is consumed in charging and discharging the driven capacitors during the switching operation from 0 1 and 10. The switching power per transistor can be computed by using equation (2.5), where CL is the switching capacitors, VDD is the voltage source, and f is the operating frequency.
(2.5)
The short path power is the power that is consumed when there is a temporary connection between the power supply and the ground, PMOS and NMOS are simultaneously ON during the switching operation. Assuming the rising and the falling time are equal, the short path power for the inverter can be computed using equation (2.6), where is the device coefficient (transistor gain factor), Vt is the device‘s threshold voltage, VDD is the supply voltage, trf is the rising or the falling time with the assumption that tr=tf, and T is equal to 1/f where f is the operating frequency.
14
(2.6)
Generally, the short circuit power is negligible when it is compared to the switching power, and based on this fact, it can be assumed that the dynamic power is equal to the switching power. According to equation (2.5) the dynamic power that is consumed by each transistor should be reduced with the constant field scaling by
50% every generation as a result of scaling the device‘s dimensions and voltages by
1/ . Thus, with doubling the number of transistors on a chip every node generation, the consumed power in the whole chip should stay constant. But in practice, the overall system‗s power dissipation is increased with scaling because:
(1) the clock frequencies have increased much faster than classical scaling would predict, (2) the VDD is somewhat higher than the constant field scaling would demand, and (3) the transistor would be a non-ideal switch with further scaling.
Furthermore, the power dissipation of a chip depends not only on its technology, but also on its implementation in terms of size, circuit style, micro architecture, and operation frequency [6]. In general, the average total power consumption of the microprocessor had been increasing exponentially as shown in Fig 2.3.
15
Fig 2.3: The MPs power consumption. Source: Borkar, De Intel [5]
2.2.2. TRADEOFFS OF TRADITIONAL SCALING
Despite the significant advancements that have been achieved by traditional
CMOS scaling, further pushing CMOS technology into the submicron regime has been boosting the non-ideal switch characteristics of the MOSFET transistor. The non-ideal switch characteristics of MOSEFET transistor have been increasing the power dissipation and reliability concerns of CMOS circuits. The effects of scaling
CMOS technology into submicron regime could be seen from three different perspectives as shown in Fig 2.4. These perspectives are: (1) physical perspective,
(2) device perspective, and (3) circuit perspective.
16
Robustness
Performance (ON current and Device aspect Life Time ratio) Process Variations
Yield Shortening the channel length Temperature Variations
Reducing the TemperaturePhysical Cost dielectric oxide Reducing the thickness mechanisms threshold voltage
Increasing the doping concentration
Leakage Currents
Power Density , Power and Energy Efficiency
Fig 2.4: Tradeoffs of traditional scaling CMOS technology in submicron regime
2.2.2.1. Physical Perspective
The traditional CMOS scaling paradigm leads directly to the following physical modifications: (1) shortening the channel length, (2) reducing the threshold voltage,
(3) reducing the dielectric oxide thickness, and (4) increasing the doping concentration. Generally, these physical modifications strengthen the following physical mechanisms: short-channel effects, threshold conductance, gate electron tunneling, and pn-junction reverse-biasing. The short-channel effects are the dominant effects of scaling CMOS technology. In particular, the short-channel
17 effects are: DIBL, punch through, surface scattering, velocity saturation, impact ionization, and hot electron. These effects are attributed to two physical phenomena: the limitation imposed on the electron drift characteristics in the channel and the modification of the threshold voltage due to shortening the channel length.
The threshold conductance, gate electron tunneling, and pn-junction reverse- biasing will be addressed in details in the device perspectives.
2.2.2.2. Device Perspective
The aforementioned physical mechanisms affect the device characteristics in terms of leakage current, resilience to process variations, resilience to temperature variations, and device performance (ON current).
(1) Leakage currents
The leakage currents in MOS transistors can be divided into six different mechanisms as shown in Fig 2.5, occurring in different states as shown in Table 1.
These mechanisms are:
Table 2.1: Leakage currents in different states [7]
18
Fig 2.5: Leakage currents in MOS transistor [7]
a) Subthreshold conductance current
When the transistor is in the subthreshold mode, the current between the source and the drain is not exactly zero. This current is called the subthreshold current. The subthreshold current can be computed by equation (2.7) [7], where VTh is the thermal voltage (VTh=k T/q), Vt is the subthreshold voltage, and n is a process- dependent term affected by the depletion region characteristics and it is typically in the range of 1.4-1.5 for CMOS processes.
(2.7)
The subthreshold leakage is a function of the temperature and the threshold voltage. It increases exponentially as the subthreshold voltage decreases or as the temperature rises. i) Temperature
The subthreshold leakage current is increased with increasing the temperature as shown in Fig 2.6.
19
Fig 2.6: The subthreshold current leakage (VGS=0) for different node generations with increasing the ambient temperature from 30o to 110. Courtesy of Vivek De, Intel[8]
ii) Threshold Voltage
The subthreshold leakage current is inversely proportional with the threshold voltage as shown in Fig 2.7. The threshold voltage is influenced by the following physical phenomena:
Fig 2.7: The subthreshold current versus the threshold voltage [5]
20
1. Vt Roll off
In this phenomenon, the Vt of a MOSFET decreases due to shortening the effective channel length as shown in Fig 2.8.
Fig 2.8: Threshold voltage versus the effective channel length [7]
2. Body effect
This phenomenon describes the effect of the source-bulk voltage in modifying the threshold voltage. This phenomenon is beyond the data dependency leakage in
CMOS circuits.
3. Drain Induced Barrier Lowering (DIBL)
This phenomenon occurs when a high drain voltage is applied to a short-channel device; it lowers the barrier for electrons between the source and the channel as shown in Fig.9, resulting in a further decrease of the threshold voltage. This phenomenon can be seen as a lowering mechanism of the threshold voltage (Vt) by increasing the VDS voltage as shown in equation (2.8), where η is the DIBL
21
coefficient (typically in the range of 0.02-0.1), and is the effective threshold voltage.
(2.8)
Fig 2.9: The effect of increasing the VDS on long and short channel [4]
(b) Gate Tunneling Current
The gate tunneling current is the effect of the physical phenomenon of tunneling the carriers in or through the oxide layer that isolates the gate from the channel. The gate tunneling has two components: Fowler-Nordheim Tunneling, where the tunneling carriers pass directly from the semiconductor‘s conduction band to the insulator‘s conduction band and Direct Tunneling, where the current directly tunnels through the complete oxide layer.
The gate leakage current can be computed by equation (2.9), where K and can be derived experimentally or numerically [7].
(2.9)
(c)Hot Carrier Injection current (HC)
22
The large voltage drops in the pinch-off region of the channel generates a high electrical field. The movements of the carriers in the high electrical fields may lead to leakage losses by a variety of mechanisms depending on the carrier energy as shown in Table 2.2.
Table 2.2: Leakage mechanisms due to high field electrons [7]
Carrier Energy Mechanisms E > 1.12 eV Light emission 1.3eV
(d) Gate Induced Drain Leakage (GIDL)
This leakage describes the effect of the gate-field on the depletion layer of the drain. As the gate voltage gets higher, the depletion layer in the gate-drain overlap area becomes thinner. The thinner oxide and the higher supply voltage increase
GIDL current. The GIDL tunneling current can be computed by using equation
(2.10), where is the field of surface, and it is equal to [7].
(2.10)
(e) PN Junction Leakage
The junction leakage occurs from the source or the drain to the substrate through the reverse biased diodes. There are two physical mechanisms that cause the p-n junction current: diffusion by drift of minority carriers and electron-hole generation in the depletion region.
23
By raising the doping concentration, the pn-junction leakage increases. It is called band-to-band tunneling since it is caused by a direct tunneling of electrons from the p-side‘s valence band to the n-side‘s conduction band [7].
(f) Punch-through leakage
This leakage results from the high voltages in short channel devices as a result of scaling the supply voltage much slower than the device geometry. In this case, the depletion regions may be enlarged to electrically touch deep in the channel, which leads to a punch-through current leakage as shown in Fig 2.5 [7].
The dominant leakage current till 90nm generation was the subthreshold leakage, but with further constant electrical field scaling into the nanometer regime the gate leakage and the pn junction leakage are becoming comparable to the subthreshold leakage as shown in Table 2.3.
Table 2.3: Prediction of the development of the subthreshold current Isub, the BTBT current Ipn_jun and the gate tunneling current Igate as an approximation derived from [7] Generation Year Isub Ipn−jun Igate
90nm 2004 840pA 25pA 13pA
50nm 2010 21nA 3.0nA 52nA
25nm 2016 260nA 120nA 510nA
(2) Resilience to Process Variations
The process variations could be in coating, doping, and etching processes. These variations lead to slight variations in structure sizes and doping profiles. If these variations happen within the die, it is called intra-die variations, while if these
24
variations happen between dies, it is called inter-die variation [7]. By increasing the
short-channel effects (physical mechanisms), the device characteristics become
more influenced by the process variations.
(3) Resilience to Temperature Variations
As a result of unbalancing utilization and diversity of circuitry at different
sections of an integrated circuit, a temperature can vary significantly from one die
area to another. In addition, ambient temperature fluctuations can cause significant
variations in die temperature [10]. As shown in Fig 2.10, MOSFET device‘s
characteristics are becoming more influenced by temperature variations.
(a) (b)
Fig 2.10 [10]:a) Gate overdrive variation with temperature at the nominal supply voltage b) Mobility variation with temperature at the nominal supply voltage
(4) Device Performance: Gate Override and Device Aspect Ration
The ON current is affected with scaling CMOS technology by two physical
phenomena.
25
(a) Electron Velocity Saturation
When the transistor is completely velocity saturated, ν= and the saturation current becomes as shown in equation (2.11), where and it is in the range of 6-10 106 for the electron and in the range of 4-8 106 cm/s for the hole ,
) is the oxide capacitance per unit area [2].
(2.11)
(b) Channel Length Modulation
The reverse-biased pn junction between the drain and the source forms a depletion region with a width of ΔL that increases with VDB. Thus, the effective channel length is equal to Leff= L- ΔL. The depletion region effectively reduces the channel length [2]. Thus, the ON current is modified accordingly as shown in equation (2.12), where is the carrier mobility and VDS is the voltage difference between the drain and source.
(2.12)
2.2.2.3. Circuit Perspective
Changes in the device characteristics as a result of the physical phenomena, caused by scaling the device into the submicron regime, can be seen from the circuit perspective as concerns about reliability. These reliability concerns are leakage power, robustness, lifetime before failure, fabrication yield, and cost.
(1) Leakage Power
26
Actually, leakage power is associated with holding or maintaining logic states between switching events. The leakage power is a wasted power because it does not contribute to computation. To compute the leakage power, equation (2.13) is used, where I leak is the total leakage currents and VDD is the supply voltage.
(2.13)
The leakage power has been increasing dramatically with traditional scaling
CMOS technology and it was predicted to reach about 50% of the total power dissipation in 45 nm as shown in Fig 2.11 (a). The increase in leakage currents in the nanometer regime is a result of reducing the transistor size, which makes reducing the supply voltage a necessity to avoid electrical breakdown and obtain the required performance. However, to maintain or improve performance, it is necessary to reduce the threshold voltage as well. The reduction of the threshold voltage results in exponential increases of the subthreshold current leakage. To control the short channel effect and increase the transistor driving strength, the gate-oxide‘ s thickness becomes thinner as the technology is scaled down.
Furthermore, by scaling CMOS technology, higher substrate doping density and application of the ―halo‖ profiles cause significantly large pn junction current leakage. Consequently, increasing the power dissipation leads to increasing the power density, which in turn increases the chip temperature as shown in Fig
2.11.(b).
27
(b) (a)
Fig 2.11: a) The dynamic and leakage power dissipation for different feature size (250nm – 45 nm) b) Power density for MPs generations Source: Borkar, De Intel [9]
(2) Robustness
It is the ability of a circuit to keep working when it is prone to external noise, variations (process, temperature, voltage), and soft errors. It is measured by a noise- immunity metric. The noise-immunity is degraded with scaling CMOS technology as a result of the short-channel effects and other physical mechanisms.
(3) Lifetime before Failure
This metric is degraded with the scaling of CMOS transistors, where new failures arise as a result of the short-channel effects which in turns make the device characteristics more sensitive to the variations (process, temperature, and voltages).
28
(4) Fabrication Yield
By scaling CMOS transistor, the intra and inter variations become more dominant. Thus, the number of defected devices increases, resulting in a decrease of the production yield and in new failures.
(5) Cost
By scaling CMOS technology into the nanometer regime, the overall cost of
CMOS cirucits is expected to increase as a result of increasing the cost of lithography fabrication tools as shown in Fig 2.12, the cost of cooling systems, and the cost of designing and testing to produce reliable circuits.
Fig 2.12: Cost of lithogrphytool per year[11]
29
2.3.NEW TRENDS IN CMOS TECHNOLOGY
With the trandittional scaling paradigm, many studies have shown that the power dissaption, power density, and other reliabilty concerns form a barrier beyond further pushing CMOS technology into the deep submicron regime. It was predicated that the leakage power dissapation would exceed 50% of the total power dissapation in the 45 nm generation. Also, the power density will be very high, which could be capable of increasing the chip power density up to that of a rocket nozzle. Thus, the conventional scaling CMOS technology using the constant E-field scaling paradigm was stopped around 2003 as shown in Fig 2.13.
Fig 2.13: End of traditional scaling era that last ~40 years ~2003[3]
30
2.3.1.CIRCUIT TECHNIQUES
Thus, the CMOS technology trend move from traditional scaling into circuit techniques and optimiztion to enhance the CMOS circuits in the submicron regime.
The circuit techniques address: (1) increasing the circuit performance, (2) suppressing the effects of the power densiy, and (3) reducing the power dissapation.
To increase the circuit performance without further pushing CMOS technology into the nanometer regime, parallelism and pipelining techniques have been used[12]. Cooling systems have been used to suppress the high temperature that is an effect of the high power desnsity cooling systems have been used. While to reduce the power dissapation and consequently reduce the power density, the power dissapation parameters should be understood. In the following subsection, the power dissapation types, issues, parameters, and cirucit techniques are discussed.
2.3.1.1. Power Dissipation: Issues & Circuit Techniques
CMOS circuits are operating either in standby mode or active mode. In the submicron regime, when the non-ideal switches behavior of the MOSFET transistor increases, the active power is becoming a function of dynamic power and leakage power as shown in equation (2.14). While in standby mode, the standby power is a function of leakage power as shown in equation (2.15).
(2.14)
(2.15)
31
The dominant reliability concern in submicron CMOS circuits is the dramatically increasing power dissipation. The high power dissipation leads to two major issues in CMOS circuits.
1) High Power Density
Increasing the power density leads to increasing chip temperature as shown in
Fig 2.11 (b). As has been discussed previously, the high temperature affects the characteristics of CMOS transistors as well as creates new defects. Thus, the whole circuit‘s performance and reliability (robustness and lifetime) will be degraded.
To avoid increasing the die temperature as a result of the high power density, there are two circuit-level solutions that could be used without affecting the overall system performance: use a cooling system to suppress high temperature and use parallelism or pipelining to suppress high power density [12].
(2) Low Power/Energy Efficiency
With high power dissipation, the circuit power/energy efficiency is reduced.
This imposes more limitations on the battery powered electronic circuits of embedded computing systems. Thus, to overcome this limitation in the submicron
CMOS circuits, the power dissipation should be reduced.
To minimize the circuit power dissipation, the power dissipation‘s parameters should be understood. As it has been explained previously, the active power consists of the dynamic power and leakage power as shown in equation(13), while the standby power, when the circuit is idle, is a function of the leakage currents as shown in equation(14), where n is the number of transistors and is the probability
32 of switching. The dynamic power is a function of the total switching capacitors C in the circuits, supply voltage VDD, and operating frequency f. Thus, to reduce the instantaneous dynamic power dissipation, one of these factors should be scaled. As shown in equation (5), the supply voltage has a quadratic effect on the dynamic power dissipation. Consequently, reducing the supply voltage decreases the dynamic power dissipation at the expense of increasing the device delay as shown in equation (delay). Consequently, to avoid the degradation of the device noise- immunity and the loss of the gate override (VDD-Vt), the threshold voltage should be decreased to a specific limit. But the reduction of threshold voltage increases the subthreshold current exponentially as shown in equation (subthreshold current equation), which in turn increases the leakage power. The second option is to reduce the switching capacitors. This requires reducing the device dimensions, which in turn boosts the short-channel effects as well as increasing the current leakages
(subthreshold, gate, and BTBT). Thus, the dynamic power could be decreased at the expense of increasing the leakage power. The third option is to reduce the operating frequency. This will reduce the dynamic power at the expense of degrading the circuit performance.
The leakage power reduction is the crucial design parameter to reduce the power dissipation in the nanometer regime, especially for the systems that are limited by the low-power dissipation rather than their performance. Thus, many leakage power techniques have been explored, such as: stacking or body-biasing
[13], power –gating (sleep transistor) using dual threshold voltage [14], clock-
33 gating [15], supply voltage optimization, threshold optimization, and threshold voltage and supply voltage optimization. Most of these techniques require significant circuit modification and performance overhead for leakage reduction
[16] [17]. In addition, some of these techniques will be not be helpful in reducing the leakage power when further pushing CMOS technology into the nanometer regime, where gate leakage and band-to-band-tunneling (BTBT) are becoming comparable to subthreshold leakage.
2.3.2. DEVICE OPTIMIZATION TECHNIQUES
To keep Moore‘s law applicable, the current trend in CMOS technology is to use device techniques to control the exponential growth of the leakage power as well as scaling the device dimensions. These device techniques are based on using material and structural innovations as shown in Fig 2.14 [18]. These techniques are: using novel structure such as SOI [19], FinFET [20], or TriGate [21] or using device materials such as using a metal gate and a high-k dielectric material [22].
Fig 2.14: Material and structure innovations for the current CMOS technology [18]
34
The device optimization techniques enable the realization of the 45 nm CMOS technology. The 45 nm CMOS technology shows advancements in the device performance as well as in reducing the gate leakage over the previous node generation (65nm) as shown in Fig 2.15 (a) and Fig 2.15 (b) respectively.
(a) (b)
Fig 2.15:a) the improvement of the device performance with using device optimization) techniques as well as scaling the device dimensions [3] b) the suppression of the gate leakage in the 45 nm technology over the 65nm technology in SRAM cell[23]
2.4. FUTURE TECHNOLOGY TRENDS USING EMERGING TECHNOLOGIES
Despite the improvements that have been achieved in reducing the leakage currents with using device optimization techniques in the recent CMOS technology, high power dissipation and power density issues still impose limitations on the nanometer-CMOS circuits; especially the nanometer -CMOS circuits that are
35 limited by their power/energy efficiency. Thus, to overcome these limitations, many studies have been conducted to explore emerging technologies. These emerging technologies are being explored either to suppress the current nanometer-
CMOS technology limitations or to be alternatives for CMOS technology in current and future technology trends in the nanometer regime. The emerging devices that have been explored are: single electron transistors [24], quantum dot [25], resonant tunneling diode [26], spintronics [27], molecular devices [28], and Carbon
Nanotube [29].
The limitations of using nanotechnology in terms of materials, mechanisms, and structures can be summarized by : limited drive current (SET), limited fan-out and structure control (quantum dot), challenge to fabrication and process integration
(resonant tunneling diode), need for high spin injection and long spin coherent time
(spintronics), limited thermal stability and need for new architectures are needed
(molecular devices), and controlled growth (Carbon Nanotube) [4].
Thus, there is a need to find an emerging technology that has high ON current, has virtually zero leakage current, can be fabricated easily, can utilize CMOS technology in terms of fabrication, design concepts, and CAD tools, and can be integrated with CMOS technology without additional overhead.
36
SUMMARY
The chapter provided detailed explanation about CMOS technology in terms of scaling paradigms, traditional scaling paradigm advantages, and the limitations of
CMOS technology in submicron regime. This chapter addressed the limitations of scaling CMOS technology in three perspectives: physical perspective, device perspective, and circuit perspective. In addition, this chapter discussed the new trends to minimize leakage power in submicron CMOS technology. These trends range from using circuit techniques to minimize the leakage power dissipation in submicron CMOS technology to using new innovations to minimize the leakage power in deep submicron CMOS technology. Finally, this chapter provided the current research for future technology trends to find alternatives for CMOS technology in the nanometer regime.
37
CHAPTER 3 : MEMS/NEMS BACKGROUND
INTRODUCTION
In this chapter, a brief background about MEMS/NEMS devices is introduced in terms of: definition, applications, difference between MEMS and
NEMS, structures, physics, materials, actuation principles, actuation operation modes, and MEMS/NEMS computation paradigms.
3.1. MEMS/NEM TECHNOLOGY
Micro-Electro-Mechanical Systems are tiny mechanical devices that are built onto semiconductor chips and are measured in micrometers; Nano-Electro-
Mechanical Systems (NEMS) are MEMS scaled to sub-micrometer dimensions
[30]. MEMS/NEMS are relatively a recent development which can be used in a variety of industrial as well as consumer product applications where IC-based technology fails. There are a wide range of applications for MEMS/NEMS, which could be classified mainly into four categories: (1) sensors, gathering information from environments, (2) actuators, controlling the environment by positioning, regulating, pumping, and filtering in responding to actuation sources, (3) switches, such as two-terminal and three-terminal relays, and (4) resonators; such as oscillators and filters in communication systems and signal processing applications.
38
3.2. MEMS VERSUS NEMS
As it has been mentioned above NEMS is MEMS with submicron dimensions.
Does this mean that both MEMS and NEMS have the same characteristics, physics, and manufacturing steps?
3.2.1. CHARACTERSTICS
Enhanced characteristics have been achieved by pushing MEMS to nanometer scale (NEMS), For instance, NEMS-based devices can have fundamental frequencies in the microwave range (~100 GHz) [31], mechanical quality factors in the tens of thousands, active mass in the femtogram range, force sensitivity at the attonewton level, mass sensitivity up to attogram [32] and subattogram[33] levels, power consumption in the order of 10 attowatts [34], and an extreme high integration level, approaching 1012 elements per square centimeter [31]. In general, the switching speed and operating frequency are increased when immigrating from
MEMS to NEMS, where the operating voltage, power dissipation, and reliability are decreased. The following table, Table 3.1, illustrates the effect of downsizing the mechanical switch from micro regime to nanometer regime.
39
Table 3.1: Comparison between MEMS and NEMS [35]
Metric MEMS NEMS Switching Time Ms‐us ns‐ps Actuation Voltage 30‐70 V 0.5‐15 V Lifetime 1011 (cold switch) - ‗hot-switched‘ life cycle test results of 1.02 × 108 and 2.70 × 108
Resonant Frequency MHZ MHZ‐GHZ
Quality Factor 10‐104 ,107 10 3‐10 4 Van der Waals Force neglect able 1‐20 nN Effective Mass ~ 10‐12 ~ 10‐15 ‐3 ‐6 ‐8 Power Dissipation(per 10 ‐10 W ~ 10 W switching cycle) (~10 nJ per switching cycle) (~<1 a J)
OFF Resistance (Ohm) =>10 10 - ON Resistance (Ohm) <=5 - Reliability Cost Moderate High
3.2.2. PHYSICS
Different theories and physical properties have to be considered with shrinking
MEMS to nanometer scale (NEMS). For example, the effects of Van der Waals and tunneling current are negligible in MEMS where they have large effects in NEMS.
Conventional electromechanical systems and MEMS are based on classic mechanics and electromagnetism, But to the contrary, NEMS are studied using quantum theory and Nano-Electro-Mechanical concepts. [36] Physicist says ―with MEMS, you could make a mirror and it is still a mirror, only smaller. But with NEMS, the whole interaction of matter with light is different. You get completely new physical properties, and that‘s a big opportunity for new devices.‖ [37].
40
Electro-Mechanical Systems
Conventional Micro-Electro- Nano-Electro- Electro-Mechanical Mechanical Systems Mechanical System Systems Fundamental Theories: Classical Mechanics Fundamental Theories: Electro-Mechanics Quantum Theory Nano-Electro-Mechanics
Fig 3.1: Fundamental theories in electromechanical systems
3.2.3. MANUFACTURING
NEMS can be manufactured by following one of these approaches: (1) a top- down approach, (2) a bottom-up approach, or (3) a combination of bottom-up and top-down.
3.2.3.1. TOP DOWN APPROACH (FABRICATED)
This approach is utilized to shrink MEMS devices to submicron dimensions by using the same fabrication process that is used for MEMS This can be done in order to obtain better properties or simply squeeze more chips on a wafer, but the properties obtained may be revolutionary. In this method, NEMS fabrication could
41 be classified into bulk and surface micromachining, which are based on a modified
CMOS technology fabrication process. The bulk machining is based on material removal from the bulk substrates, whereas the surface micromachining creates
NEMS devices by adding materials layer by layer on top of a substrate [38].
3.2.3.2. BOTTOM-UP APPROACH (SYNTHESIZED)
In this approach, the atoms and molecules are synthesized, grown, or self- assembled to manufacture NEMS using different Nanotechnology‘s materials. For instance, Carbon Nanotube have been investigated recently to manufacture NEMS switches and memories [39]. In fact, the assembly of molecular structures into the functional devices could push NEMS to further miniaturization and property enhancement; these kinds of NEMS can be called molecular devices.
3.3. NEMS STRCTURES
The interesting properties of the NEMS devices typically arise from the behavior of the active parts, which are in the forms of cantilevers, gears, membranes, or doubly-clamped beams. The most common structures for
MEMS/NEMS relays are the following.
1) Cantilever beams: In this structure, the mechanical part is fixed from one side and free from the other side. This structure needs less force to pull than fixed-fixed beam (bridge).
42
Fig 3.2: Cantilever beam structure [38]
2) Bridges (doubly-clamped-beam): In this structure the two ends of the beam are fixed.
Fig 3.3: Bridge (fixed-fixed beam) structure [38]
3.4. MEMS/NEMS OPERATION MODES
Generally, there are two actuation modes for MEMS/NEMS devices: switching mode and resonant mode.
43
3.4.1. SWITCHING MODE (QUASI-STATIC)
In the switching mode, MEMS/NEMS performs its functions by the movement
(displacement) of the active part under the influence of the applied force/forces until the air gap is dismissed (the switch is closed). When the applied force(s) is (are) removed or minimized to specific value, the active part moves back to reform the air gap.
Depending on the contact type, there are types of the mechanical switches.
3.4.1.1. Capacitive Switch
When the switch is closed, there is still a capacitor between the active part and the passive part (fixed part) as a result of the insulator layer. The general architecture of the capacitive switch is in the form of an active part-gap-insulator- passive part. For instance, metal-gap-insulator-metal is a capacitive switch. The most important limitation of capacitive switches is the affect of dielectric charging.
3.4.1.2. Ohmic Contact Switch (Resistive Switch)
In this type of switch, when the switch is closed, a direct contact between the active part and the passive part is formed. This direct contact is modeled electrically as a contact resistance. The contact resistance is a function of the contact area, where the capacitive switch characteristics are a function of the applied force(s).
The general architecture of the Ohmic switch is in the form of active part-gap-
44 passive part. For instance, metal-gap-metal is an Ohmic switch. Ohmic contact switches suffer from a degradation of the switch contacts with repeated cycling and they suffer from the stiction problem.
3.4.2. RESONANT MODE (ACOUSTIC)
In this mode, the MEMS/NEMS performs its functions by the acoustic movement of the active part under the influence of the applied forces. The air gap should not be dismissed as a factor in this operation mode.
3.5. MEMS/NEMS PHYSICAL ACTUATION PRINCIPLES
MEMS/NEMS can be actuated using different actuation principles to perform its function/functions. These physical principles include: electrostatics, Maxwell's equations, classical mechanics, Navier's equation, first and second laws of thermodynamics, quantum mechanics, and Schrödinger‘s equation. Four main principles [40] [41] are commonly employed for actuation of MEM/NEMS devices and are listed below.
1) Electrostatic Actuation Principle
The mechanical part moves under the influence of the electrostatic force, which is generated by applying a voltage difference between parallel plates or electrodes.
45
2) Piezoelectric Actuation Principle
The mechanical parts are fabricated by using certain materials with piezoelectric effect property. Thus, applying a voltage to its movable part causes it to expand [42].
3) Magnetic Actuation Principle
There are two approaches for magnetic actuation. First, for larger devices, the micro-actuator can be equipped with a permanent magnet and a planar coil, generating a vertical force that actuates the magnet [43]. This approach is very difficult to integrate and probably not applicable for NEMS devices. In a second approach, the conducting actuator is positioned in a static magnetic field. In this case, the current through the actuator causes a Lorentz force to bring the device into motion. It uses simple fabrication technology, and it is easy to integrate [44].
4) Thermal Actuation Principle
This principle can use the bimetal effect with different thermal expansions or shape memory alloys, which create a stress in the actuator upon heating.
46
Table 3.2: Comparison between actuation mechanisms in MEMS devices [42] [37]
Actuation Electrostatic Piezoelectric Magnetic Thermal Voltage High Medium Low Low Current Low Low Medium High Power consumption Low Low Medium/high High Switching time Short(us) Medium() Short(us-ms) Long(ms) Contact force Medium Small Medium Large Force Generated Moderate Moderate High Moderate Deflection/Range Moderate Small Large Small Fabrication method Simple Complex Simple Simple Energy density - equation
3.6. MEMS/ NEMS MATERIALS
There are a wide range of materials that have been investigated in fabricating
MEMS/NEMS devices, these materials could be classified into three categories: (1) semiconductors (SiC, Si, SiN, GaAs, etc.), (2) Metals (Al,Au, Cu, W, and Ni), and(3) polymers (photoresists, polyimides, etc.).
3.7. MEMS/NEMS COMPUTATIONS
Recently, with continuous enhancement of characteristics of MEMS/NEMS devices, much research has been conducted to re-examine mechanical computation.
The idea of mechanical computation is not new, in the 1820s; Charles Babbage designed the first mechanical computer. Mechanical computation can be conducted in two possible forms: linear (displacement) form and dynamic (acoustic) form. In
47 the linear form, the linear or angular displacement of mechanical part(s) can form the basis for multistate logic, with the logic ―state‖ being a physical spatial configuration of the mechanical parts where the state is changed by a displacement of the mechanical parts. In the dynamic form, the computation is based upon acoustic waves; for example, the vibration modes of mechanical elements.
Actually, these two methods of computation are not distinct. Even within linear displacements of mechanical elements, the resonant frequency and damping factor play important roles in determining the switching speed [45].
SUMMARY
In this chapter, an overview of MEMS/NEMS devices has been provided focusing on NEMS switches. The reasons for choosing the electrostatic actuation principles as an actuation source for implementing NEMS switches have been explained. The characteristics that make those switches good candidate for CMOS technology in implementing logic gates and memories have been shown.
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CHAPTER 4 : LITERATURE REVIEW
INTRODUCTION
This chapter serves as a literature review for the previous works in MEM/NEMS switches including: (1) designing/fabricating MEMS/NEMS switches with attractive characteristics in terms of low operating voltage, high switching speed, and footprint size, (2) using MEMS/NEMS switches as an emerging technology to implement logic gates and memories, and (3) evaluating MEM/NEMS switches at the device level/ circuit level.
In this chapter, the previous works are addressed in terms of applications, characteristics, material, structure, manufacturing technology, and evaluation methods for the claimed characteristics.
Finally, the criteria that should be addressed to consider the designed/fabricated
MEMS/NEMS switch as a good solution to overcome CMOS limitations in nanometer regime are highlighted.
4.1. ELECTROSTATIC MECHANICAL SWITCHES
The electrostatic mechanical switches are actuated by the electrostatic actuation principle, where the mechanical part moves under the influence of the electrostatic force. The electrostatic force is generated by applying a voltage difference between two parallel plates or electrodes. Thus, these switches can be configured to be in ON
49 state or OFF state by controlling the voltage difference between switches‘ electrodes.
The electrostatic mechanical switches are more attractive than other actuation types of mechanical switches. The qualities that make the electrostatic mechanical switches more attractive when they compared to other types of mechanical switches, as shown in Table 3.2 in the previous chapter, are simplicity in manufacturing, high switching speed, low power consumption, and ease in being integrated with other electrical circuit elements.
Today‘s mechanical switches are fabricated by utilizing the fabrication process of CMOS technology, which helps to release Micro-Electro-Mechanical
Switches (MEMSs). By shrinking the electrostatic mechanical switches into the micro-regime (MEMS), many enhancements have been brought to the characteristics of these switches in terms of lowering the operating voltage and increasing the switching speed, which makes these switches an attractive solution to be used in wide range of applications.
4.2. ELECTROSTATIC MECHANICAL SWITCHES AS AN EMERGINIG
TECHNOLOGY
To overcome CMOS limitations in the nanometer era, some studies have investigated the electrostatic mechanical switches as a good candidate for CMOS technology in implementing logic gates and memories. The reasons behind
50 considering the electrostatic NEMS switches either as an alternative technology in implementing logic gate and memories or as sustainable technology to be integrated with CMOS technology to overcome the excessive leakage power dissipation in nanometer regime are summarized below. 1) The intrinsic characteristics of the electrostatic mechanical switches in terms of: (a) configuration to ON and OFF states by controlling the voltage difference between the switch‘s electrodes and (b) offering high ON current, limited by the supply voltage, in the
ON state, and virtually zero leakage current in the OFF state.
2) The numerous advancements that have been achieved in the electrostatic mechanical switches in terms of fabrication and operations. In addition, further shrinking the device size into submicron regime enables releasing Nano-Electro-
Mechanical Switches (NEMSs), which have a lower operating voltage and higher switching speed than the MEMS switches.
3) The ease of integrating them with CMOS technology in terms of manufacturing process and operation process without extreme cost, when they are compared to other types of mechanical switches.
4.3. LITERATURE REVIEW
To consider MEMS/NEMS switches as good candidates for CMOS technology in implementing logic gates and memories or to be integrated with CMOS technology to overcome the dramatic leakage current, the devices should have
51 comparable characteristics to the current semiconductor technology in terms of size, operating voltage, and switching speed. This gives a potential to many researchers to investigate new methods or material to design/fabricate MEMS/NEMS switches with high attractive characteristics in terms of operating voltage and switching speed.
In the literature, many studies have reported two-terminal and three-terminal electrostatic NEMS switches. These previous reported works in MEMS/NEMS switches generally addressed: (1) designing/fabricating NEMS switches that have attractive characteristics, (2) using NEMS switches that has attractive characteristics in implementing logic gates or memories to overcome CMOS limitations in the nanometer regime, and (3) evaluating NEMS switches in device level and circuit level. Table 4.1 summarizes some of those works in terms of MEMS/NEMS characteristics, material, structure, manufacturing technology, and evaluation methods for the claimed device characteristics.
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Table 4.1: Literature MEMS/NEMS logic gates and memories
Work # NO# of Characteristics Material( Structure Manufacturing Evaluation terminals active technology method part(s)) work#1 Three Vpin=15V Conductor Cantilever Nanotechnology Experimental Ts = in ns range Carbon material (Carbon results [46] 2003 Nanotube Nanotube) [47]2004 [48]2004
Work#2 Two Vpin (AN)=2.34 V Carbon Cantilever Nanotechnology Experimental Vpin(EXP) ~2.33V Nanotube material (Carbon result, and [49]2005 Nanotube) analytical model
53
Work#3 Three Vpin/Vpo Silicon Bridge Analytical (Vds=0) ~0.38/0.28 V ------model [50]2005 (Vds=1) ~0.7 /0.53 V [51]2007
Work#4 Three Vpin/Vpo ~ 1/0.1 Silicon Bridge ------Analytical analysis
[52]2008
54
Work#5 Four Vpin=1V CNT(Carbon ------Analytical Ts = in ps range Nanotube ) model, and circuit [53]2007 simulation
.
Work#6 Two Vpin/Vpo=13 /8.5V Metal Cantilever By utilizing Experimental Ts = in tens of second (TiN) conventional results [54]2007 CMOS fabrication process
55
Work#7 Two Vpin=8.5V Carbon Nanotube Cantilever nanotechnology Experimental beam(twee material results [55]1999 zers‘ arms) (Carbon [56]2001 Nanotube)
work#8 Three Vpin=30 V Al, Au Cantilever Utilizing conventional Experimental results Ts=2us CMOS fabrication [57]1999 process
SEM micrograph of switch. The area of this switch is 30 X 74 um2
56
Work#9 Three Vpin =~1V ------Cantilever ------3D Numerical Ts < 50 ns ----- simulation results [58] 2007 [59]2008
Work#10 Two VPin~1V Au Cantilever bottom-up approach, by Experimental beam subsequently deposited results [60]2004 Molecules
57
Work#11 Two Vpin ~ 4.5V, SWNT Carbon Bridge Nanotechnology Experimental Ts= in ns range Nanotube material (Carbon results, with [61]2006 Nanotube) analytical analysis
As mentioned above, the electrostatic NEMS switches with the characteristics,
footprint size, low pull-in voltage, and high switching speed are more likely
candidates to be used in implementing logic gates and memories and furthermore to
be hybridized with CMOS technology. This motivates the researchers to target these
characteristics of NEMS switches in their designs and implementations by using
different materials, structures, dimensions, and technologies as has been shown in
Table 4.1.
In the following subsections, the works in Table 4.1 are discussed in more
detail in terms of the materials used, the fabrication approach, and the evaluation of
NEMS switches at the device level and the circuit level.
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4.3.1. ACTIVE PART‘S MATERIAL
In works # (1), (2), (5), (7), and (11), the Carbon Nanotube was the active mechanical part of the reported NEMS switches. In works # (3), (4), (6), (8), (9), and (10), metal and semiconductor materials were used for the active mechanical part of the NEMS switches.
4.3.2. FABRICATION APPROACHES
Generally, the reported NEMS switches can be categorized based on their fabrication approaches into the following approaches.
1. Top-down approach
In this approach, NEMS switches are produced by pushing MEMS into the nanometer regime, as it has been mentioned previously. The fabrication process for those NEMS switches is based on the modified CMOS technology fabrication process. In works # (6), NEMS switches were produced using this approach. In works # (3), (4), and (9), the same approach was proposed to fabricate NEMS switches, which were evaluated based on the analytical model.
2. Top-down approach and bottom-up approach
In this approach, the mechanical parts are nanotechnology materials, such as
Carbon Nanotube. Usually, those Nanotechnology materials are produced by using bottom-up approach techniques, while the other part/parts of NEMS switch are fabricated by following the top-down approach. Finally, the mechanical part(s) and the other parts (fixed) of NEMS switch are integrated together by utilizing the
59
CMOS technology fabrication process. The NEMS switches in works # (1), (2), (5),
(7), and (11) were proposed or produced based on this approach.
3. Bottom-up approach
In this approach, the whole NEMS switch is produced by assembling molecules and atoms. In work # (10), the gold (Au) molecules were subsequently deposited to produce the NEMS switch with 2-3 nm air gap and a 75 nm electrode thickness.
4.3.3. VALIDATION/EVALUATION
The reported NEMS switches in Table 4.1 were validated based on one of the following approaches: using fabricated device measurements, using analytical/numerical analysis, or using fabricated device measurements and analytical analysis equations. The reported NEMS switches‘ characteristics in works
# (1), (2), (6), (7), (8), (10), and (11) were based on the fabricated device measurements. The reported NEMS switches‘ characteristics in works # (3), (4), (5), and (9) were based on the analytical/numerical analysis. And the reported NEMS characteristics in works # (2) and (11) were based on the fabricated device measurements and the analytical analysis.
The three-terminal switch, in work # (1), reported firstly in [46], was based on a static analytical analysis. In this analysis, Van der Waals force was not considered.
In [47], the switch [46] was demonstrated experimentally. The experimental results demonstrated that the pull-in voltage for this switch is 15 V and the switching time
60 is in the ns range. In [48], the dynamic behavior of this switch was studied. The study demonstrated the switching time for this switch is in the nanosecond range.
In work # (1), they reported that this switch is a good solution for implementing logic gates and memories, but without providing an accurate device Macromodel and without conducting circuit simulation experiments.
The two terminal NEMS switch in work # (2) was fabricated. An analytical solution for the device‘s pull-in voltage with considering Van der Waals force was provided. The demonstration showed good agreement between the experimental and the analytical results. The dynamic behavior of this switch was not reported.
In work # (3), the three-terminal NEMS switch was reported based on the analytical solution found in [50]. In the analytical solution, Van der Waals was not considered. In [51], the reported switch in [50] was investigated to be used in hybrid
CMOS-NEMS and NEMS SRAM. Based on the analytical model in [50], an electrical equivalent spice model was developed. The spice simulation was used to evaluate the advantages of using NEMS switches to reduce the leakage currents.
The dynamic analysis for this switch was not addressed.
In work # (4), an analytical model for three-terminal NEMS switch was provided. The analytical model is based on the 1D parallel-plate capacitor model.
The computations for the mechanical coefficients were not demonstrated. In this work, the static analytical equations for the pull-in and pull-out were provided, while the dynamic behavior for this switch was not analyzed. To simulate NEMS logic gates, the static analytical analysis was integrated to the MOSFET EKV model
61 and the gate position was expressed as a function of the gate voltage. Because of this, a spice simulation could be used. The numerical solution in this work was based on the numerically computed displacement.
In work # (5), the reported switch was modeled in the circuit simulation by using an equivalent electrical circuit model that is shown in Table 4.1 and the general switch model in spice. The state of the switch was determined based on the analytical computation for the pull-in voltage and the switching speed.
In work # (6), the two-terminal NEMS switch was fabricated to work as a nonvolatile memory. Experimental results for the fabricated device were reported.
No analytical analysis was demonstrated and no device circuit model was provided for circuit simulation purposes.
In work # (7), the pull-in voltage for the reported NEMS switch was demonstrated based on the fabricated device measurement. The pull-in voltage for this switch is ~ 8.5V.
In work # (8), three-terminal MEMS switch was reported based on the fabricated device measurements. The pull-in voltage for the reported switch is ~30
V and the switching time is ~2us. The analytical analysis and the circuit model were not discussed in this work. This work concentrated on demonstrating how they constructed AND and OR gates using their switch. The AND and OR gate were constructed without following typical CMOS style.
The work # (9) was reported in [58] and revised in [59]. In this work, the 3D
FEA simulation was used to design the metallic NEMS switch. The 3D simulation
62 showed the pull-in voltage for different device dimensions without addressing the dynamic behaviors. The stiffness constant, k, was calculated using the theoretical equation. The simulations of MOS-NEMS were done by embedding the results from the 3D design (pull-in voltage) into the SmartSpice simulator by using the Verilog-
A interface. All the results for the NEMS switch that were embedded in the
SmartSpice simulator were based on the static solution for the pull-in voltage without considering the dynamic behavior of the NEMS switch, when it was integrated in CMOS.
In work # (10), the fabricated device measurements were provided. The pull-in voltage for this switch is around 1V. The analytical analysis and the device circuit model were not provided for this fabricated device.
In work # (11), the characteristics of the fabricated device were demonstrated based on the fabricated device measurements. The pull-in voltage for this switch is around 4.5 V and the switching time is in ns.
4.3. KEY CRITERIA TO CONSIDER NEMS SWITCHES AS AN EMERGING
TECHNOLOGY
To consider the NEMS switches that have been reported so far in the literature, as good candidates for CMOS technology in producing logic gates and memories, those switches should be re-evaluated in terms of fabrication, cost, reliability, compatibility with the CMOS technology, and evaluation methods . To evaluate efficiently, the behaviors and the advantages of using these switches in
63 implementing logic gates and memories or to be a hybrid with CMOS technology to reduce the quotient power dissipation in the nanometer regime, an accurate device Macromodel (circuit model) that is capable of producing the device characteristics in a circuit simulation environment is needed as well as a circuit simulator that is capable of simulating the NEMS switch using its circuit model
(Macromodel) and other electrical circuit elements.
The key criteria to consider NEMS switches an emerging technology to implement logic gates and memories or to be integrated with nanometer CMOS technology are as follows.
1. Fabrication
In works # (1), (2), (5), (7), and (11), those works investigated Carbon
Nanotube, as a tough material with high Young‘s modulus, to be the active mechanical part of their NEMS switches. In work # (10), the whole NEMS switch was fabricated by assembling the gold molecules to build the switch; thus, it could be considered a molecular device. To my knowledge, the fabrication of Carbon
Nanotube or molecular devices cannot be controlled easily meaning the actual dimensions of those devices cannot be controlled precisely. Subsequently, the fabrication of a large number of those devices with the same dimensions has not yet been done. Furthermore, the integration of those devices with the CMOS process cannot be seamless, where it is difficult to precisely position them.
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2. Cost
First, from a fabrication perspective, do those devices using expensive materials need new fabrication processes? If so, they may also require new equipment and tools. And, if they can be fabricated by utilizing CMOS technology fabrication process, are they easy to be fabricated?. Second, from a concept and design point of view, do those devices are being used to implement logic gates and memories in different ways than what have been done in CMOS technology; consequently, new design methods and simulation tools are needed.
3. Reliability
To consider those NEMS switches to be good candidates for The CMOS technology in implementing logic gates and memories, they should be tested carefully for reliability issues such as stiction, and durability (life time of the switch).
4. Compatibility with CMOS technology
The compatibility of NEMS switches with CMOS technology can be addressed by the possibility of integrating those NEMS switches with the CMOS technology in terms of fabrication and operation processes.
5. Evaluation in device level and circuit level
How accurate are the reported evaluations for these devices; especially for the reported devices that were just evaluated based on the analytical analysis?
Understanding the theories of NEMS switches is essential in designing NEMS switches, but the experimental results give more insight into the phenomena of
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NEMS switches that are not easy to predict and capture in the analytical model.
And, to be able to evaluate those devices in circuit environments, did the reported work provide an accurate device Macromodel that is capable of reproducing the device measurements in circuit environments? And if so, does the used circuit simulator engine is capable to dynamically evaluate the mechanical, and consequently, the electrical behaviors of the NEMS switch?
Overall, to consider any reported NEMS switch as a good candidate for CMOS technology in implementing logic gates and memories, NEMS switches should be addressed in terms of: (1) having good characteristics such as low operating voltage and reasonable switching time in compared to CMOS technology, (2) having good reliability in terms of durability and functionality (thus, these issues should be addressed), (3) the capability of fabrication this switch without extreme complexity and with fabrication cost that is comparable to CMOS transistor fabrication cost, (4) the ability of utilizing CMOS technology in terms of architecture design concepts, paradigms, and CAD tools, (5) the accuracy of the provided analytical analysis and accuracy of the derived circuit model (Macromodel) to accurately simulate this switch in circuit environment, and (6) how accurate the used circuit simulator is capable to handle the device circuit model to capture the dynamic movements of the mechanical switch and reflect this in the electrical circuit model.
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SUMMARY
In this chapter some previous works in the electrostatic mechanical switches that addressed designing/fabricated NEMS switches with attractive characteristics, using the NEMS switches that have attractive characteristics as emerging technology, and evaluating these NEMS switches in analytical analysis and the device circuit model to be used in circuit simulation environment.
The reported works in this chapter have been discussed in terms of the used material, fabrication approach, and validation and evaluating method for the claimed device characteristics in the device level and the circuit level.
Finally, the criteria that make any reported NEM switch a good candidate for
CMOS technology, either to replace CMOS technology in implementing logic gates and memories or to be hybrid with CMOS technology to overcome CMOS excessive leakage power dissipation, have been highlighted.
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CHAPTER 5 : ELECTROSTATIC NEMS SWITCHES: CONCEPTS, ANALYSIS,
AND DESIGN
INTRODUCTION
This chapter provides an intensive knowledge of electrostatic NEMS switches in terms of principle of work, physical quantities, physical phenomena, and device characteristics. Furthermore, an explanation of how the device characteristics are determined by the physical phenomena, where the physical phenomena are confined by the device physical quantities of dimensions, structure, and material.
Finally, this chapter describes the general NEMS production process and concentrates on NEMS design phase in terms of (1) objective and decisions that should be made to achieve the objective characteristics, (2) NEMS design approaches, and (3) NEMS design steps using FEA multi-physics simulation tool.
5.1. PRINCIPLE OF OPERATION
The electrostatic NEMS switches are actuated by the electrostatic force that is generated on the movable part/parts electrodes of NEMS switches when applying a voltage difference between the NEMS‘s electrodes. Besides the electrostatic force, there may be other intermolecular forces attracting the NEMS‘s movable electrode toward the fixed electrode or another moveable one. And, when the electrostatic
68 force and the intermolecular forces (if they exist) overcome the elastic force of the movable part/parts, the NEMS‘s electrodes come in contact abruptly.
There are two types of contact in NEMS switches: metal-metal contact (Ohmic switch), and metal-dielectric contact (Capacitive switch). In both types, if the voltage difference between the NEMS‘s electrodes is reduced to specific limit that makes the elastic force of the movable part/parts overcome the electrostatic and adhesion forces, the switch is opened.
5.2. MULTI-PHYSICS DEVICE
NEMS switch is multi-physics device, where multi-physics phenomena are involved in determining the device‘s characteristics based on the device physical quantities of dimension, material(s), and structures.
To design and model the electrostatic NEMS switches the device, the physical quantities, physical phenomena, and characteristics should be understood. Fig 5.1 shows how the characteristics of a NEMS switch are determined by the device physical quantities and the applied voltages through the involvements of the device physical phenomena.
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Voltage difference
Device Physical Quantities: Dimensions Material Structure
Physical Phenomena
Device Characteristics and Specifications
Fig 5.1: Electrostatic NEMS switch: physical quantities, physical phenomena, and device characteristics
In the following sections, the device quantities, physical phenomena, and device characteristics of NEMS switches are explained. In addition, mathematical equations that describe the direct relationships between the physical phenomena and device quantities are presented. The mathematical equations that describe the direct and indirect relationships between the switch characteristics and the physical device quantities through the involvements of the physical phenomena are also demonstrated.
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5.3. NEMS PHYSICAL QUANTITIES
The NEMS switch‘s quantities are the physical quantities that determine the device characteristics. The physical quantities of a NEMS switch are as follows.
1. Structure
As was mentioned before, the structure of NEMS‘s movable part(s), generally, cantilever(s) beam or bridge(s).
2. Dimensions
The dimensions of a NEMS switch are: the length (L) of the movable electrode(s), the width (W) of the movable electrode(s), the thickness (H) of the movable electrode(s), and the gap between the NEMS switch‗s electrodes.
3. Material
The materials of the NEMS switch are the materials of the movable electrode(s), the fixed electrode, and the dielectric layer/part (if used). The most important material properties relating to switching characteristics are the Young‘s modulus (E) of the movable part(s), the conductivity ( ) of the electrodes‘ material(s), the emitter work function ( ) of the electrodes‘ material, and the permittivity of dielectric material ( ) (if used).
5.4. NEMS PHYSICAL PHENOMENA
As mentioned previously, NEMS switch is a multi-physics device. The following physical phenomena are involved in determining the characteristics of
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NEMS switch when a voltage difference is applied between the NEMS‘s electrodes as shown in Fig 5.1.
5.4.1 ELASTIC FORCE
Elastic Force is a repulsive force that is generated when the movable part is moved under the influence of an external/internal force. The elastic force can be computed using Hooke‘s law as in equation (5.1), where k is the elastic constant of the movable part(s), and x is the displacement of the movable part(s). The elastic constant is a function of the device dimensions, material, and structure. The elastic constant can be computed analytically by using equation (5.2) [62] where is a variable depending on the structure (for example, in cantilever structure, it is equal to 0.25), E is the Young‘s modulus, H is the thickness of the movable electrode(s),
W is the width of the movable electrode(s), and L is the length of the movable electrode(s).
Feleastic=kx (5.1)
(5.2)
5.4.2. ELECTROSTATIC FORCE
It is an attractive force that is generated when applying a voltage difference between the NEMS‘s electrodes. The electrostatic force can be computed based on the 1D parallel- plate‘s model. The electrostatic force for an Ohmic switch can be
72 computed by using equation (5.3). While for Capacitive switch, the electrostatic force can be computed by using equation (5.4).
(5.3)
(5.4)
5.4.3. INTERMOLECULAR FORCES
Generally, the intermolecular forces are attractive forces. The intermolecular forces are more dominant when at least one of the switch dimensions is in the nanometer regime. Thus, for NEMS switches, the intermolecular forces should be considered, such as Casimir force and Van der Waals force.
It has been pointed out by many researchers in this field that the Van der Waals force and Casimir force describe the same physical phenomenon at two different scales [63] so they cannot in general be considered to simultaneously act in
MEMS/NEMS switches. Actually, the gap determines which force should be considered when designing or modeling NEMS switches. For instance, if the gap is smaller than the wavelength (plasma frequency of the material [64]) of the virtual transitions which is responsible for the quantum dipole fluctuations [64], the Van der Waals force should be considered. Otherwise, the Casimir force should be considered. The non-retarded Van der Waals force and the retarded Casimir force between two parallel plates can be computed by equations (5.5) and (5.6) respectively [65].
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(5.5)
(5.6)
Where A is the overlapping area, H = π2Cρ2 is the Hamaker constant which lies in the range (0.4 − 4)10−19 J, C is a constant characterizing the interactions between two atoms, is Planck‘s constant divided by 2π and is equal to 1.055×10−34 Js, c is
-1 the speed of light and is equal to 2.998×108ms , g0 is the initial gap between parallel plates, and x is the displacement of the movable plate(s).
The following table, Table 5.1, compares Casimir and Van der Waals forces based on Lifshitz‗s results (experiments) [64], where λ is the transition between the ground and the excited states of the atom.
Table 5.1: Comparison between Van der Waals force and Casimir force [64]
Van der Waal’s Force Casimir Force
1.Valid when the separation gap < λ 1.Valid when the separation gap ~λ or gap > λ
2. The attraction is proportional to 1/gap3 2. The attraction is proportional to 1/gap4
3. It is affected by the material properties 3. It is not affected by the material properties.
5.4.4. CONTACT FORCE
It is an attractive force that is generated on the NEMS‘s electrodes when they are in contact. To estimate the contact force, the contact area should be estimated first. To estimate the contact area, the contact analysis models should be used. The
74 contact analysis models are based on either the single-asperity contact model, such as the Hertz contact model, or based on a multi-asperity contact model [66]. For simplicity, the single contact model will be assumed in this analysis.
To estimate the effective radius of the contact area in a single asperity model, the deformation type of the NEMS‘s mechanical part should be defined. The deformation of the mechanical part could be. In the following subsections, the deformation types are explained.
5.4.4.1. Elastic Deformation
In elastic deformation assuming the single asperity contact model, the contact area depends on the asperity peak radius (R) of the curvature (surface roughness) and the asperity vertical deformation ( as shown in equation (5.7).
(5.7)
The contact force can be estimated by knowing the effective Young‘s modulus
for the contact materials as shown in equation (5.8). The effective Young‘s modulus can be computed by using equation (5.9); where E1 and E2 are the elastic modulus of the first and the second contact, and ν1 and ν2 are the Poisson‘s ratio of the first and the second contact.
(5.8)
(5.9)
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Assuming that the contact area is a circular area, the effective radius can be calculated as shown in equation (5.10).
(5.10)
5.4.4.2. Plastic Deformation
For plastic deformation, assuming the single-asperity contact model, the contact area and contact force can be expressed by equation (5.11) and equation (5.12) respectively, where A is the contact area, R is asperity peak radius of curvature, is asperity vertical deformation, Fc is the normal contact force, and H is the hardness of the contact material [67]. Assuming the contact area is a circular area, the effective radius can be computed by using equation (5.13).
(5.11)
(5.12)
(5.13)
5.4.4.3. Elastic-Plastic Deformation
Elastic-plastic deformation describes the deformation that could occur when parts of the contact area are plastically deformed, but encased by elastically deformed material [68]. In this kind of deformation, assuming the single-asperity contact
76 model, the contact area and contact force are expressed as shown in equation (5.14) and equation (5.15) respectively.
(5.14)
(5.15)
Where refers to the critical vertical deformation, where plastic yielding is assumed to occur. The critical vertical deformation could be calculated by using equation (5.16), where KH is the hardness coefficient which is assumed to be equal 0.6 at the onset of plastic deformation [69]. A, Fc, H, R, and are defined as they were defined previously in this section.
(5.16)
The effective contact radius can be expressed by equation (5.17) assuming circular contact area.
5.4.5. DAMPING FORCE
Damping force is a repulsive force. Generally, the squeeze film trapped air damping is the most dominant mechanism of damping in MEMS and NEMS switches [70]. The squeeze film damping force consists of two main components: viscous damping force and the compression damping force. The viscous damping
77 force is caused by the air when it is squeezed out (or sucked into) the gap region of the actuated movable plate/plates. This force is dominant when the movable part/parts oscillate at low frequency. The compression damping force (elastic damping force) is caused by the compressed air in the gap [71]. This force is proportional to the displacement of the movable parts and is dominant when the movable part(s) oscillate(s) at a high frequency [71].
5.4.5.1. Viscous Damping
As the movable parts approach the substrate or each other, gas molecules are pushed from the gap and undergo several collisions. For small air gaps (gap < the mean free path) or when the ambient pressure is lower than the ideal pressure, the molecular collisions are reduced before escaping the gap. In this case, the effective viscous damping is considered. The effect of viscous damping accounts for gas rarefaction
[72]. The gas rarefaction effect is closely related to the Knudsen number (Kn) [73].
For large Kn value (>> 1), the gas rarefaction is considered, otherwise it is not. The effective viscosity of the gas underneath the gap decreases when the Kn increases.
The effective viscosity as a function of Kn is given by equation (5.18)
(5.18)
where μ is the viscosity of an ideal gas at Standard Temperature Pressure (STP)
(μ =1.85*10-5 kg/m s (Pa s)). For a Knudsen number between 0 and 880, the effective viscosity in this formulation is within +/- 5% of the exact value. Kn [73] is
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equal to , where λ ( ) is the mean free path of the gas molecules at
pressure pa, and h is the local gap height, and λ0 is the mean free path defined at
constant pλ,0 (pλ,0= 101.325 KPa) under STP conditions.
5.4.5.2. Compression Damping
The squeeze number σ captures the compressibility effect in the squeezed gas.
The squeeze number σ is expressed as ), where W is the width of the movable part and ω is the angular resonant frequency. The compressibility effect should be considered when the squeeze number σ is less than the cut-off squeeze number σcut−off (≈ 10) [74]. To account for air compression when the squeeze number is greater than the cut-off squeeze number (σ > σcut−off ), the elastic damping force should be considered in the squeeze damping analysis.
In summary, for a 1-D analytical model, the squeeze film damping force Fd could be expressed by the elastic damping and viscous damping (
), where is the elastic constant of the squeeze film air damping
force, is the viscous damping coefficient of the squeeze film damping force(Fd), gap is the initial gap, u is the displacement in the direction of the movement; and is the velocity of the movement for the cantilever beam[71].
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5.4.6. KINETIC FORCE
Kinetic force is a repulsive force. The kinetic force can be computed by using equation (5.19), where is the acceleration of the movable part, and meff is the effective mass of the movable part.
(5.19)
5.4.7. CONTACT BOUNCING MOTION PHENOMENA
In the first time when the switch electrodes are becoming in contact, the impact force causes the movable part(s) to bounce many times before it becomes permanently in contact. The contact bouncing phenomena is a function of the switch‘s physical quantities and the applied voltage.
5.5. NEMS CHARACTERSTICS
The Characteristics of a NEMS switch are as follows.
5.5.1. PULL-IN AND PULL-OUT VOLTAGES
Usually, the operating voltages in MEMS/NEMS terminology are called pull-in
(Vpin) and pull-out (Vpout) voltages. When the pull-in voltage is applied between the
NEMS‘s electrodes, the electrostatic force overcomes the elastic force and a switch is closed abruptly. Thus, the pull-in voltage is the minimum voltage that should be
80 applied between a switch‘s electrodes to change its state from OFF to ON. The pull- out voltage is the maximum voltage that should be applied between a switch‘s electrodes to change its state from ON to OFF. The pull-out voltage should be greater than or equal to zero.
To design a NEMS switch to have a specific pull-in voltage, the physical quantities should be adjusted; consequently, the physical phenomena will be adjusted to meet the required pull-in voltage. The device operating voltages are a function of the device physical quantities including structure, dimensions, and material.
To understand the effects of the dimensions, structure, and material on determining the pull-in voltage, equation(34) [75] gives an estimation for the pull-in voltage based on the parallel plates 1D analytical model of Ohmic MEMS/NEMS switches without considering the intermolecular forces where the values of c1 and c2 depend on the NEMS switch ‗s structure. For example, for cantilever beam structure,
c1=0.07 and c2=1 ; is the effective Young‘s modulus (plate modulus), E is the Young‘s modulus of the movable part material, is the Poisson ratio of the movable part material, is the permittivity of vacuum, H is the thickness of the movable part, g0 is the initial gap, and L is the length of the movable part. Thus, equation (5.20) computes the pull-in voltage as a function of the dimensions,
Young‘s modulus (material property), and structure. The pull-in voltage is directly proportional to the gap and the thickness of the MEMS/NEMS switch and inversely proportional to the length of the movable part of the MEMS/NEMS switch.
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(5.20)
The physical phenomena that affect the pull-in voltage are electrostatic force, elastic force, and intermolecular forces. The physical phenomena that affect pull-out voltage are the same forces that determined the pull-in voltage in addition to the contact force.
5.5.2. SWITCHNIG TIME
The switching time is the time that the switch needs to change its state from ON to OFF and vice versa. The switching time is a function of the device physical quantities, structure; dimensions; and material, and the applied voltage.
To understand the effects of the device physical quantities and the applied voltage in determining the switching time, the switching time for NEMS switch can be estimated based on the equation(5.21) below [76], where Vpin is the pull-in voltage,
Vs is the applied voltage(Vs >Vpin), and is the angular resonant frequency. The resonant frequency can be approximated by equation (5.22) [62], where is the material density for the movable electrode(s), E is Young‘s modulus, W is the width of movable, and L is the length of movable part. Consequently, the switching time is directly proportional to quadratic length and inversely proportional to the width of the movable part.
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(5.21)
(5.22)
In terms of the physical phenomena, the switching time is a function of the following physical phenomena: electrostatic force, elastic force, intermolecular forces, damping force, bouncing impact motion, and kinetic force.
5.5.3. ON AND OFF RESISTANCES
In this section, the ON and OFF resistances of the Ohmic (resistive) switch are investigated.
5. 5.3.1. OFF Resistance
The OFF resistance of NEMS switches can be expressed by the tunneling current that flows between the electrodes of electrostatic NEMS switch when the switch is in the OFF state (switch opened). The tunneling current in the OFF state can be calculated based on Fowler-Nordheim tunneling mechanisms equation
(5.23).
(5.23)
(5.24)
Where A is the overlapping area cm2, J is the current density in A/cm2, φ (eV) is the emitter work function, It is the tunneling current (A), and E is the electric field
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(V/cm) perpendicular to the overlapping surface of the NEMS electrodes. Based on the tunneling current density and tunneling current equations (5.24) (5.25), the value of the OFF resistance is determined. Accordingly, the factors that determine the
OFF resistance of the NEMS switch are: (1) the applied voltage, the voltage difference between the NEMS electrodes that is inversely proportional to the OFF resistance of the NEMS switch, (2) the gap, the distance between the NEMS electrode, is directly proportional to the OFF resistance of the NEMS switch, (3) the emitter work function, a material property of the NEMS electrodes that inversely proportional to the OFF resistance of the NEMS switch, and (4) the overlapping area, the area between the NEMS electrodes where the electrical field (E) is perpendicular that is inversely proportional to the OFF resistance of the NEMS
Switch.
5.5.3.2. ON Resistance
The ON resistance is the resistance in the contact area between the electrodes of the NEMS switch when the switch is in ON state (switch opened).In the Ohmic
(resistive) MEMS/NEMS switch, the contact resistance that results from making an electrical connection is defined by equation (5.26), where Rc is the resistance resulting from the constriction effects, and Rcf is the resistance resulting from the contaminant film [77]. The contaminant film can be removed by plasma cleaning.
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Thus, in this section when contact resistance is mentioned, that means constriction resistance.
RC = Rc + Rcf (5.26)
The contact resistance is a crucial parameter in determining the ON resistance of
MEMS/NEMS switches. Actually, modeling the contact resistance is a challenge due the difficulty in predicting the behavior of the moving bodies when they are coming into and are going out of contact. In addition, the contact operation is highly coupled with the surface roughness and the material deformation type. To estimate the ON resistance of the MEMS/NEMS switch, the contact area and the electron transport mechanism should be determined. The computation of the contact area has been demonstrated in the physical phenomena section. The electron transport method could be determined by the effective contact radius and the electron free path of the NEMS electrodes [78]. There are three types of electron transport mechanisms that could occur in MEMS/NEMS switches:
1. Ballistic Transport
Ballistic transport occurs when the effective contact radius is less than the electron mean free path of MEMS/NEMS electrodes material (r < λe). In this transport mechanism, Sharvin resistance is the major contributor to the contact resistance [79]; Sharvin resistance could be computed by using equation (5.27), where K is the Knudsen number (K= λe /r).
(5.27)
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2. Quasi-ballistic Transport
Quasi-ballistic transport occurs when the effective contact radius is comparable to the electron mean free path of the MEMS/NEMS electrodes material (r ~ λe).
Sharvin resistance equation (5.27) is used to compute the contact resistance in the
Quasi-ballistic transport mechanism.
3. Diffusive Transport
The Diffusive transport occurs when the effective contact radius is much greater than the electron mean free path of the MEMS/NEMS electrodes material (r >> λe).
To compute the contact resistance when the electron transport is ballistic, Maxwell spreading resistance equation can be used [80]. The formula for the Maxwell spreading resistance is given in equation (5.28), where, is the electrical resistivity, and r is the effective contact radius.
(5.28)
5.5.4. RELIABILITY ISSUES
The reliability issues that control the life time (durability) of the NEMS switches should be considered when designing and Fabrication NEMS switches. The reliability issues for NEMS switches can be categorized into two groups: stiction and wear.
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5.5.4.1. Stiction
Stiction is the phenomena of adhesion of the movable mechanical electrode to the fixed/movable electrode of the switch. The stiction occurs when restoring forces are unable to overcome the interfacial forces such as electrostatic, capillary, Van der
Waals, Casimir forces, and other kind of chemical forces [81]; the stiction is considered a fundamental catastrophic failure in MEMS/NEMS switches.
The stiction in MEMS/NEMS switches can be classified into two groups, as they demonstrated in the following.
1. Manufacturing (release-related) Stiction
The manufacturing stiction occurs during the production process of the
MEMS/NEMS switches. In general, it occurs while removing the sacrificial layer; during the fabrication process of the mechanical part; it is caused by capillary forces.
Some mechanisms and engineering methods have been discussed to handle and overcome the release –related stiction. These methods could be: 1) Texturing the surfaces to reduce the geometrical contact area by [82] using Bumps (Asperities), these hemispherical bumps reduce the contact area to dimensions smaller than the resolution of the photolithography, or using side _wall spacers [82] 2) Surface modification by using hydrophilic materials(i.e,Ti,Al2O3) to suppress the water bridging causing a attractive capillary force between mechanical and stationary structures of switch during the subsequent process of drying liquid after release etching through the fabrication process [83].
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2. Operational (In-use) Stiction
The operational stiction occurs while the switch performs its functions in a specific application; when the elastic force cannot overcome the adhesion forces even though after removing the external force, voltage potential, the surfaces of switch electrodes permanently adhere to each other causing device failure.
Generally, the mechanisms or the techniques that could be used to avoid in-use stiction are [84]: 1) Choosing materials for the movable and fixed electrodes with low adhesion energy [84] 2)Coating with low surface-energy materials, or chemical passivation(e.g., self assembly monolayer (SAMs) coatings)[82] 3)
Reducing the contact area by using the same mechanisms that have been mentioned previously, in addition to increase the surface roughness [82], where Van der Waals force is expected to be extremely sensitive to surface roughness.
The problem of stiction is a major problem in Ohmic switches, as a result of the direct contact between the electrodes surfaces, While in the Capacitive switches, the dielectric layer prevent the direct contact between the electrodes when they are actuated.
In summary, from the design point view; anti-stiction mechanisms should be incorporated when designing the Ohmic (resistive) switches, in order to avoid the occurrences of stiction during the fabrication and the operation stages of
MEMS/NEMS switches. It is important to mention here that under specific
88 atmospheric conditions or when a large reduction of adhesion forces is needed, a combination of anti-stiction mechanisms could be used.
5.5.4.2. Wear
Wear is the erosion of material from a solid surface by the action of another solid material. Mechanical wear such as pitting and hardening of the metal contact area is considered as the dominant failure mechanisms in shortening the durability of MEMS/NEMS switches. Pitting and hardening occur as a result of the repeat impaction between two metal contacts [85]. This leads to in-use stiction.
In the following discussion, the factors that affect the Ohmic switch life time, and the NEMS switch life time test are demonstrated.
1. Factors that Affect Ohmic NEMS Switch Durability
Many factors are playing important roles in determining the durability of the resistive MEMS/NEMS switches: a) Contact bouncing motion
Usually, when the switch starts to contact, it bounces many times before making permanent contact. The impact bouncing motion affects the reliability of the Ohmic switch as a result of the repeat impaction between two surfaces of the electrodes.
Actually, large impact bouncing motion may cause pitting or hardening to the mechanical part as well as decrease the contact area which in turn increase the heat generation, and those possibly reduce the life-time of the switch [86].The contact bouncing motion should be considered when analyzing NEMS switches, in order to
89 increase the durability of the MEMS/NEMS switches, and reduce the power consumption.
In the literature, few studies have investigated some mechanisms to minimize the contact bouncing motion which in turn increase the switch life-span and reduce the power consumption. In [86] they demonstrated how to reduce the bouncing movements by multiple-step actuation voltage instead of single step actuation voltage. In [87] they demonstrated that their closed loop control system could be used to limit the number of switch bounces as well as reduce the impact force. In
[88] they demonstrated how the open loop control system was used to eliminate the switching bounces by soft landing (close the switch with near –zero-speed) approach.
b) Contact area.
As the contact area decreases, the switch will be more prone to wear and heat generation. c) Damping
There are strong relationship between the damping and the impact bouncing motion in MEMS/NEMS switches. Actually, increasing the damping reduces the impact bouncing motion in MEMS/NEMS switches.
2. Ohmic MEMS/NEMS Switch Durability Tests
To test the reliability of MEMS/NEMS switches and determine the life-time of those switches, there are three kinds of lifetime tests based on two different conditions: cold-switching with no load, and hot-switching with load [89].
90 a) Cold-switching
In this test the switch is repeatedly actuated without applying RF or DC power during the actuations. The life time of the switch in cold- switching test is mainly restricted by: structural fatigue, memory effect, stiction, and changes in the electrical DC on resistance [89]. b) Hot-switching
The switch in this test is repeatedly actuated with applying either RF power or
DC current during the actuations. Hot-switching characteristics test for
MEMS/NEMS switches are very important in determining the reliability of switches. Since most of the signals that are transmitted through the switches have high power loads in real cases. In hot-switching tests the life time of the switch is determined by the number of cycling of the switch before it is permanently stuck after the actuation signals are removed. The siction in this case is caused by micro- welding between the contacts. The micro-welding occurs by increasing the temperature in the contacts due to repeatedly opening and closing the switch during applying either high RF power signal or high DC current [89].
5.6. NEMS PRODUCTION PROCESS
NEMS production process consists mainly of three phases: design phase, fabrication phase, and validation phase. The production process of NEMS switch follows the iterative model methodology as shown in 2.5. During the production
91 process of NEMS switches, the production process ‗phases are revised many times till the NEMS physical quantities can be adjusted to release a NEMS switch with the desired characteristics. In the design phase, NEMS physical quantities should be initially set to approximately match the required characteristics. In the fabrication phase, the NEMS Switch is fabricated by using one of the fabrication paradigms that were discussed in chapter3 (MEMS/NEMS background), and adapts any mechanisms that help in avoiding release-related stiction as well as in-use stiction.
In validation phase, the NEMS switch is tested for its characteristics as well as its reliability, in-use stiction and wear, using the NEMS durability tests, which they were demonstrated previously. As it has mentioned previously these phases are revised many times till the switch be validated with the desired characteristics and reliability. Finally, the switch can be released to be used for intended applications.
Design Phase Fabrication Phase Validation Phase Release
Fig 5.2: NEMS production process
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5.7. NEMS SWITCH DESIGN PHASE
In this section, we concentrate on the NEMS design phase including: (1) define
NEMS design phase‘s objective and decision (2) discuss NEMS design approaches: the backward approach using analytical equations and forward approach using FEA physical model (3) demonstrate NEMS design steps using the FEA physical model.
5.7.1. NEMS SWITCH DESIGN: OBJECTIVE AND DECISION
The design phase of NEMS Switch is like any plan that has objectives and decisions to be made to achieve the required objectives. The objectives of the
NEMS design phase is to come up with a NEMS switch in terms of: structure, dimensions, and materials. This NEMS switch should be approximately have the required characteristics. The required characteristics of NEMS switch will be in terms of: size, operating voltages, switching time, ON and OFF resistances or
ON/OFF capacitances, and reliability issues. The decision that should be made at the end of the design phase is adjusting the NEMS physical quantities to meet the required characteristics. The NEMS physical quantities as they were mentioned previously including: dimensions (Width, Length, Thickness, and Gap), materials, and structure.
Generally, NEMS switch design phase follows the iterative model methodology, where the device quantities are adjusted many times till the required characteristics are met as shown in Fig 5.3.
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Design Phase
Set or Rest device: Dimensions, Structure, Material
Objective Decision Compute the device characteristics Required device Device structure, characteristics dimensions, and material
Check the computed characteristics versus the objective characteristics
No match
Yes Stop
Fig 5.3: NEMS switch design phase
5.7.2. NEMS DESIGN APPROACHES
Designing NEMS switches is not a trivial task, where multi-physics phenomena involve in determining the device characteristics. Thus, there is a need to adjust many device‗s attributes to control the device physical phenomena in a manner to come up with a NEMS switch that has the desired characteristics.
Actually, designing NEMS switches cannot be accomplished without understanding NEMS switch‘s behaviors, physical phenomena, and physical quantities as well as the relationships among them. As it has been demonstrated in
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Fig 5.2, NEMS production process is an iterative process, where its phases revised many times to come up with NEMS switch that has the required characteristics. To minimize the number of cycling through NEMS production ‗phases, a good design is needed. To design a NEMS switch, we can categorize NEMS design approaches into two approaches: backward approach and forward approach. The backward approach relies on the analytical equations that describe the behaviors of NEMS switches as functions of the device physical quantities. Generally, these analytical equations are based on the parallel-plate model and do not consider all the device physical phenomena. In this approach, the physical quantities are set by substituting the desired characteristic such as pull-in voltage or switching time in the analytical equation and write the equation in form of two variables. Thus, one variable is solved by substituting constant values for the other variable. The forward approach relies on understanding the relationship between NEMS switch characteristics, physical phenomena and device quantities. This approach is based on set initial values for the device quantities based on understanding the analytical equations.
And then construct a Finite Element Analysis device physical model using a FEA simulation tool. To construct an accurate device physical model, the device phenomena should be understood. The FEA device physical model is used to compute the device characteristics. Consequently, if the computed device characteristics are not close to the objective characteristics, the device physical quantities for the device physical model should be modified till the objective characteristics are approximately achieved as shown in Fig 5.3. Thus, in this
95 approach we are able to evaluate the initial design accurately without going to the fabrication phase.
In summary, a FEA modeling for NEMS switches helps in producing a good design, and consequently, minimizing the cycling through the NEMS production‘s phase. And this in turn leads to reducing the NEMS‘s production life cycle as well as reducing the NEMS production cost.
5.7.3. NEMS DESIGN STEPS USING THE FEA SIMULATION TOOL
The design phase of NEMS switches could be summarized by the following steps that we followed to come up with our NEMS switch:
(1) Select the material for NEMS‘s electrodes. This material should have good mechanical and electrical properties in terms of elasticity and conductivity.
(2) Determine the structure for NEMS‘s movable electrode(s). The structure should be chosen to be fabricated easily by utilizing the modified fabrication process of
CMOS technology. In addition to enhancing the NEMS characteristics and reliability in some cases.
(3) Set the NEMS dimensions: Length, Width, Thickness, and Gap. The NEMS dimensions are set under the size limitations. For instance, to come up with NEMS switch in foot-print size, the NEMS ‗Length, Width, and Thickness should be <1 um. And to ensure low pull-in voltage, the gap should be in the range of 1-10 nm.
With understanding the relationship between the switch‘s pull-in voltage and
96 switch‘s dimensions, as it was discussed previously, the pull-in voltage is directly proportional to the gap and the thickness of the MEMS/NEMS switch, and inversely proportional to the length of the movable part of the MEMS/NEMS switch. Thus, with this knowledge, the NEMS‘s switch dimensions could be set initially. And based on the initial design a NEMS physical model is built using a FEA simulation tool. The NEMS model is used to compute the pull-in voltage for the initial design.
If the computed pull-in voltage does not match or be close to the desired value, the device dimensions are re-adjusted based on understanding the relationship between the pull-in voltage and the device dimensions‘ parameters. While if the computed pull-in voltage matches or closes to the desired value, the physical model is used to compute the switching time as shown in Fig. 5.4.
The device physical model is used to compute the switching time. If the switching time is too far from the desired value, the device dimensions are adjusted with considering the relationship between the device dimensions and the switching time. As it was demonstrated the switching time is directly proportional to length and inversely proportional to the width of the movable part.
To avoid the stiction problem in our design, the device physical model is used to simulate the pull-out voltage by reducing the applied voltage and considering the adhesion force such as Van der Waals force. If the movable part is not be able to return to its original position with reducing the applied voltage to zero volt, in this case, the switch structure or material should be revised as well as the device dimensions.
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To evaluate the ON/OFF resistance for Ohmic switch, the physical model could be set to simulate the contact area. Consequently, the ON resistance could be computed. And to compute the OFF resistance, the physical model could be used to simulate the leakage current. If the leakage current is not reasonable, the device‗s gap should be increased, or the device material should be changed.
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Start the design phase
Choose or Re-choose NEMS electrodes material
Determine or Re-determine the movable part structure and the device architecture
Set/Re-set Dimensions:Length, Width,Thickness,Gap
Build/Re-build a device physical model
Compute the pull-in voltage
No Close to the desired one Yes Compute switching time
No Close to the desired one
Yes Reducing the applied voltage till the switch return to its original position
No Switch return to original position
Yes
Compute leakage current (ROFF ) and RON
Yes
No Reasonable leakage
End
Fig 5.4: NEMS design flowchart
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SUMMARY
A comprehensive study of electrostatic NEMS switches was provided in terms of: physical quantities, physical phenomena, and device characteristics.
Furthermore, analytical equations that describe the relationship between the device characteristics and the physical phenomena as well as the physical quantities were demonstrated. In addition, this chapter discussed NEMS reliability concerns including stiction and wear. And some techniques, from literature, were provided to avoid or overcome the stiction problems. To measure the durability of Ohmic
NEMS switches, this chapter described cold and hot switching tests.
Finally, this chapter demonstrated the design phase of the NEMS production process. And concentrated on how to minimize the time and cost of NEMS production process by constructing a physical device model that captures the physical phenomena and produces the device characteristics. The physical device model is constructed using Finite Element Analysis simulation tool that will be demonstrated in next chapters.
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CHAPTER 6 : FABRICATED TWO-TERMINAL TUNING FORK NEMS
SWITCH
INTRODUCTION
In this chapter, the fabricated two-terminal tuning fork NEMS switch is presented in terms of experimental device characteristics, fabrication process, and
3D physical device model. The demonstration will present the attractive characteristics of this device that make it unique. The design of this device will be used as a base for designing a four-terminal NEMS switch. This switch can be configured to be used in implementing computational and sequential circuits.
The 3D physical device model should capture the multi-physics phenomena in the fabricated device. To verify the ability of the constructed 3D physical device in capturing the device physical phenomena, a 3D physical device‘s measurements will show that the constructed 3D physical device model is capable of re-producing the fabricated device measurements. In this manner, the 3D physical device model forms a reference model that enables us to measure other device characteristics and phenomena that are not easy to be measured from the fabricated device.
Accordingly, this enables us to derive an accurate device circuit simulation model that is calibrated and derived based on the 3D physical device model and the fabricated device, as will be demonstrated. This circuit simulation model enables accurately modeling the NEMS switch in a circuit environment.
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6.1. TWO-TERMINAL TUNING FORK (Ni-Ni) NEMS SWITCH
The two-terminal NEMS switch has tuning fork geometry with two movable beams as shown in Fig 6.1.This switch is an Ohmic switch, where the contact type is a metal-gap-metal contact. When the applied voltage between the switch‘s electrodes is increased to the device pull-in voltage, the electrostatic and the small intermolecular forces overcome the elastic force. In this manner, the switch‘s electrodes become in contact abruptly after they travel for a specific distance that makes the electrostatic and the intermolecular forces overcome the device‘s elastic force. Thus, a direct current path is formed between the switch electrodes. To stop the direct current path between the switch‘s electrodes, the applied voltage difference between the switch‘s electrodes should be reduced to a specific value
(device‘s pull-out voltage) that makes the elastic force overcome the electrostatic and the adhesion forces. Consequently, the switch is opened.
Fig 6.1: Schematic of the two-terminal tuning fork NEMS switch
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6.2. TWO-TERMINAL TUNIG FORK NEMS SWITCH FABRICATION
This device was fabricated initially by a combination of lithography and
Focused Ion Beam (FIB) milling. Actually, the main issue with FIB is that it is not scalable and it also results in back-sputtering of ions on the device. This in turn can cause electrical shorts at low frequencies and reduce the overall device reliability and reproducibility. To overcome this problem and increase the device reliability and reproducibility, a fabrication technique that can be used to fabricate this device has been developed to realize 1-2 nm gaps with a sacrificial oxide layer as schematically shown in Fig 6.2 [90]. The yield of the microfabricated devices was much better than the Fibbed devices and their endurance was also better. The key steps in fabricating this NEMS switch using the developed microfabrication technique are shown in Fig 6.2.
Fig 6.2: Schematic of the fabrication process for metallic Nano-Electro-Mechanical switches (NEMS) on silicon substrate
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Fig 6.2 shows the schematic diagram of the proposed fabrication process that is used to develop a metallic NEMS. The NEMS switch on the silicon substrate was fabricated using the following steps [90]:
(a) Preparation of cleaned silicon wafer after RCA-1 process.
(b) The deposition of the silicon nitride film by low pressure chemical vapor deposition (LPCVD).
(c) The deposition of poly silicon (Poly-Si) layer with thickness of 1.5µm on the silicon nitride layer. Then, the polysilicon layer was doped by phosphorus from TP-
470 dopant source at 1050ºC.
(d) Etching at the outside of photoresist micropatterns until silicon nitride layer by using reactive ion etching (RIE) in an inductive coupled plasma (ICP) after photolithography.
(e) Depositing silicon dioxide layer with thickness of 8nm on the micropatterned
Poly-Si by thermal oxidation.
(f) Depositing 330 nm of Ni film on 20 nm adhesion layer of Cr by sputter (Denton,
USA).
(g) Polishing the Ni deposited wafer with FCN-560 slurry with a chemical mechanical polishing (CMP) tool (Strasbaugh 6EC, USA).
(h) Etching the sacrificial oxide layer by buffered oxide etchant.
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The Scanning Electronic Microscopy (SEM) picture for the fabricated two- terminal tuning fork NEMS switch is shown in Fig 6.3.
Fig 6.3: SEM picture for the two-terminal tuning fork NEMS switch
6.3. DEVICE CHARACTERSTICS
This switch has attractive characteristics in terms of turn-on voltage ~ 1V, and switching time ~ 1ns. In this switch, the tuning fork geometry with the two-movable beams helps in reducing the device‘s turn-on voltage by 30% and increasing the switching speed by 2X over the one-movable beam device‘s structure. This has been demonstrated in the fabricated devices as well as in the 3D physical devices‘ models with different gaps as shown in Fig 6.4. In this figure, the voltage advantage is shown in (a), while the switching advantage is demonstrated schematically in (b).
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(a)
(b) Fig 6.4: The advantages of using two movable beams in the two-terminal tuning fork NEMS switch a) Voltage advantage of using two movable beams over one movable beam b) Switching speed
6.3.1. OPERATION VOLTAGE
The pull-in voltage for this switch is ~ 1V as shown in the IV characteristics in
Fig 6.5. This makes this switch an attractive switch to address the power efficiency
106 problem in Nanometer-CMOS technology. In this switch, the tuning fork geometry helps in reducing the device‘s pull-in voltage as well as avoiding the stiction problem. Thus, the switch is capable of opening when the voltage difference is reduced to pull-out voltage, which it is ~ 0.1 V.
3.2. LEAKAGE CURRENT
The leakage current for this device, when the voltage difference between the switch‘s electrodes is very small (V << Vpin), is virtually zero. In the IV characteristic curve that is shown in Fig 6.5, the voltage difference was increased gradually till it reached the device‘s pull-in voltage. The leakage current shown in
Fig 6.5 demonstrates the leakage current after the gap was reduced (before the switch was closed and when the applied voltage is very close to the device pull-in voltage). It is important to point out that this leakage current, in the static mode, consists of two types of current leakage: tunneling current leakage and surface current leakage. Actually, these kinds of current leakages could be reduced during the fabrication process by surface treatments such as plasma cleaning and surface coating.
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Fig 6.5: Two-terminal tuning fork NEMS switch IV characteristic
6.3.3. ON RESISTANCE
When the switch is closed a direct current path is formed between the switch‘s electrodes. It has been demonstrated experimentally that the ON resistance for this switch is ~ 10 Ohms.
6.3.4. SWITCHNIG SPEED
This switch with the tuning fork structure achieves high operation frequencies because of the higher frequency of its second resonant mode (~2f0). In this mode, the center of mass does not move and the two vertical cantilever beams are moving against each other as schematically shown in Fig 6.4(b). The higher switching speed coupled with very low RC time constant associated with charging/discharging of the metallic interconnected transmission lines (feeding the RF signal to the
108 switch). This leads to a very high switching speed only limited by the ―mechanical‖ response of the switch‘s movable parts. It is important to point out that the damping effects by air molecules, in this switch, which have a mean free path ~ 65 nm at room temperature, are minimized by the device geometry with nanometer gaps. The switching speed is ~ 1 GHz as was demonstrated experimentally (Fig 6.6).
Fig 6.6: Switching/oscillation of the nickel device in the feedback loop of low noise RF amplifier. The bottom trace is the oscillation spectrum clearly showing the fundamental around ~1GHz and switching harmonics
6.3.5. FOOTPRINT SIZE
This switch has footprint size as demonstrated in Fig 6.1. As it is shown in this figure the dimensions of this switch are very small in submicron regime.
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6.3.6. SWITCH LIFE TIME
This switch has been demonstrated up to greater than one billion hot switching cycles. The work is still going in the lab to increase the life time of this switch by plasma cleaning and surface treatments.
6.4. 3D FEA PHYSICAL DEVICE MODEL
The 3D Finite Element Analysis (FEA) physical device model has been constructed for the fabricated two-terminal NEMS switch to capture the device‘s multi-physics phenomena. The capability of the constructed 3D FEA physical device model in capturing the device‘s multi-physics has been demonstrated by its ability in re-producing the fabricated device measurements as will be demonstrated.
In this manner, the 3D FEA physical device model forms a reference model that can be used to measure the device‘s characteristics/phenomena that cannot be measured easily from the fabricated device. Furthermore, by following the same procedure in modeling the device physically as will be explained in next chapter, a 3D FEA physical device model could be constructed for any device even if the device is not be fabricated. In this work, the 3D FEA physical device model will be used as based model to come up with an accurate device circuit simulation model that is capable of re-producing the static and the dynamic electro-mechanical device‘s characteristics accurately. Thus, the derived device circuit simulation model enables modeling the device accurately in a circuit in terms of behaviors, time, and power
110 dissipation, when it is used in a circuit environment as will be demonstrated in next chapters. In Table 6.1, the 3D FEA physical device model‘s measurements for the fabricated device‘s characteristics and phenomena are presented. The procedures to simulate these characteristics and phenomena will be demonstrated in next chapter.
Table 6.1: 3D FEA physical device model’s measurements for the two-terminal tuning fork Ni-Ni NEMS switch
Pull-in voltage Van der Waals force
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Switching time Tunneling Current
Capacitance Switching energy
112
Contact pressure Contact area versus the load force
Damping forces Resonant frequency for each beam
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6.5. VERIFICATION
To demonstrate the accuracy of the 3D FEA physical device model in producing the fabricated device measurements over the analytical analysis equations, the device pull-in voltage and resonant frequency have been computed using the 3D
FEA physical device model and using analytical equations. Table 6.2 shows that the 3D FEA physical device model is capable of reproducing the fabricated device‘s measurements more accurately than the analytical equations. The analytical equations that have been used to compute the device pull-in voltage have been modified to consider the two-movable beam advantages.
Table 6.2: The device’s pull-in voltage and resonant frequency
Evaluation Pull-in voltage Resonant frequency method Fabricated device ~ 1 V ~ 1GHz 3D physical device Without considering Van der Waals force 0.96 GHz model . Vpin ~1.15 V With considering Van der Waals force
. Vpin ~ 1 V Analytical L= 1 um L= 1 um equations . Vpin=0.65 V . Fr= 0.320 GHz
L= 640 nm L= 640 nm . Vpin= 1.6 V . Fr=0.78 GHz
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6.6. DEVICE MACROMODLE (CIRCUIT SIMULATION MODEL)
The device Macromodel for the two-terminal NEMS switch consists of two interacting models: a mechanical lumped model and an electrical circuit model. In the following explanations, the mechanical lumped model and the electrical circuit model of the two-terminal NEMS switch will be described. The detailed equations that have been used in these models will be demonstrated in the four-terminal device Macromodel chapter.
6.6.1. MECHANICAL LUMPED MODEL
The movement for each cantilever beam is described by the modified spring- mass-damper equation (43), where xn is the beam tip‘s displacement, keff is the effective stiffness constant for the cantilever beam, meff is the effective mass of the cantilever beam, cd is the viscous damping coefficient, and kd is the elastic damping coefficient. To derive an accurate mechanical lumped model, the mechanical coefficients have been extracted from the 3D FEA physical device model as shown in Table 6.3. While the electrostatic and Van der Waals forces have been computed with considering the gap variations along the movable beam length as shown in Fig
6.7. This was done by segmentation of the beam along its length into n segments.
Accordingly, the electrostatic force and the Van der Waals force for each segment have been computed. The Second Degree Differential Equation (2nd DFE), the modified spring-mass-damper equation (43), has been solved numerically using the fourth-order Runge-Kutta method.
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Table 6.3: The extraction of the mechanical coefficients from the 3D FEA physical device model
Effective elastic coefficient Effective mass
Effective viscous damping coefficients Effective elastic damping coefficients
(43)
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gapn K xn gapn-1 K Xn-1
B L B
m m gap2 gap1 gap 0
Fig 6.7: Mechanical lumped model
6.6.2. ELECTRICAL CIRUIT MODEL
6.6.2.1. Electrical circuit model in the Switching/OFF state
The electrical circuit model during the switching operation/OFF state is an interconnection of Ri, Ci, RA and RB. Ri is the resistance of two corresponding beam segments (Shown in the 1D Macromodel), and its value is derived from the reciprocal summation of the tunneling current, the surface current, and switching current. Ci is the capacitance between two corresponding beam segments as shown in the Fig 6.7; its value is derived using the parallel plate model. RA and RB are the metal resistance for port A and B as shown in Fig 6.8.
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Fig 6.8: Electrical circuit model for the two-terminal tuning fork NEMS switch in the OFF/switching state.
6.6.2.2. Electrical Circuit Model in the ON state
The electrical circuit Model consists of RA,Rcontact, RB. Rcontact is computed using the Sharvin resistance model [79], where the contact area for this model is computed from the FEA physical device model, and RA and RB are the metal resistance of the port A and B.
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Fig 6.9: The electrical circuit model for the Two-terminal tuning fork NEM switch in the ON state
To demonstrate the accuracy of the constructed 1D Compact Macromodel for the two-terminal NEMS switch over the analytical model (analytical equations), the computed mechanical and electrical characteristics of the two-terminal NEMS switch using the 1D Compact Macromodel and using the 3D FEA physical device model are presented in Table 6.4 versus the one that computed using the analytical model. The measurements from the 3D FEA physical device model and the derived
1D compact Macromodel are almost matched.
Table 6.4: Characteristics of the two-terminal NEMS switch
Characteristics/Phenomena Derived 3D FEA Analytical equations Macromodel Model L= 1um L= 640 nm Pull-in Voltage (V ) 1 V 1 V 1.58 V 0.65 V pin Switching time 1.13 ns 1.15 ns 3.0e-10 s 1.25e-10 s Capacitance ( Gap between 1.23 e-15 F 1.22e-15 F 1.48e-15 F beams' tip =1.2e-9, t=0.90e-9) Van der Waals force1 1.56e-7 N 1.6e-7 N 2.5e-7 N (gap=1.2e-9) Van der Waals force2 7.07e-8 N 7.1e-8 N 7.30e-8 N (gap=1.2e-9)
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SUMMARY
In this chapter, the fabricated tuning fork (Ni-Ni) has been presented in terms of fabrication steps, experimental fabricated device measurements, 3D FEA physical device model, and circuit simulation model.
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CHAPTER 7 : FOUR-TERMINAL NEMS SWITCH: DESIGN, LOGIC
REALIZATION, AND MODELING APPROACH
INTRODUCTION
In this chapter, the four- terminal NEMS switch is presented in terms of design, configurations, and logic gates and D-latch realization. Furthermore, to evaluate
NEMS logic gates and sequential circuits, a modeling approach that will be followed, in this work, is introduced.
7.1. FOUR-TERMINAL NEMS SWITCH DESIGN
To get advantages of the fabricated two-terminal NEMS switch in realizing
NEMS logic and sequential circuits, a four-terminal NEMS switch that inherits the unique characteristics of the fabricated device has been designed. The four-terminal
NEMS switch was designed by utilizing the fabricated two-terminal NEMS switch: geometry and material and using the FEA multi-physics simulation tool (COMSOL multi-physics). The initial FEA physical device model is constructed based on the fabricated two-terminal NEMS switch, and it is used to evaluate the characteristics of this design. Based on these evaluations, the NEMS switch‘s design is modified, as it has been demonstrated in the analysis and design chapter. The FEA physical device model helps in reducing the NEMS switch production life cycle as well as reducing the NEMS‘s production cost. Thus, the validated 3D FEA physical device
121 model that captures the objective device characteristics is constructed based on the decisions that have been made at the end of the design phase in terms of: dimensions, structure, and materials. The properties of the device materials of the constructed four-terminal are shown in Table 7.1 (Comsol documentation, material library)[92].
This switch with its simple structure can be fabricated easily using the modified
CMOS fabrication process that has been described in previous chapter.
Table 7.1: The four-terminal NEMS switch material properties
Material property Value
Young’s modulus (Ni) 219 G [Pa]
Poisson ratio (Ni) 0.31
Density (Ni) 8900 [kg/m3]
Electrical conductivity (Ni) 13.8*106 [S/m]
Permittivity constant 9.7 (Si3N4) Young’s modulus (Si3N4) 250 G[Pa] Young’s modulus (SiO2) 70 G [Pa] Permittivity constant (SiO2) 4.2 Poisson ratio (SiO2) 0.17 Density (SiO2) 2200[kg/m3]
The structure of this switch is shown in Fig 7.1. This switch has tuning fork geometry with the two movable beams. The two movable beams are the Body cantilever beam and the composed D-G-S cantilever beam. In this switch, there are two types of contacts in the ON state: metal-metal-contact between the Body and
122 the Drain/Source terminals, and metal-dielectric contact between the Body and the
Gate terminals. The dielectric layer (Si3N4) that coated the Gate forms isolation between the Body and the Gate in the ON and OFF state, while the direct metal- metal contact between the Body and the Drain/Source forms a direct current path between the Drain and the Source through the Body in the ON state.
L1= 1 um, L2= 64 nm, H= 330 nm, W= 200nm, Gap=1.5 nm
(a)
WD= 10 nm, WGD= 10 nm, WG= 160 nm, WGS= 10 nm, WS= 10nm, HGB=3 nm
(b) Fig 7.1: The four-terminal NEMS switch: dimensions and structure
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In the OFF state, there is no direct current path between the Drain and the
Source. In this case, if the voltage difference between the Body and the Gate is increased up to threshold voltage (pull-in voltage), the two-movable beams attract each other as a result of the attraction forces (the electrostatic force and the small
Van der Waals force).And when the gap reached ~1/3 of the initial gap, the switch movable parts are becoming in contact abruptly (ON state). Thus, a direct current path between the Drain and the Source terminals through the channel is formed. To open the switch, and stop the direct current path between the Drain and the Source, the switch‘s movable beams have been designed to have sufficient elastic force that enables them to overcome the electrostatic force and the adhesion forces, when the voltage difference between the Body and the Gate is reduced to the pull-out voltage( pull-out >=0). Accordingly, the stiction problem could be avoided.
7.2. NNEMS AND PNEMS CONFIGURATIONS
To implement NEMS logic gates and flip-flops, the four-terminal NEMS switch is configured to N-channel (NNEMS) and P-channel (PNEMS) in the form of
Complementary-NEMS (CNEMS) as in NMOS and PMOS correspondingly in
CMOS technology. The schematic of NNEMS and PNEMS are shown in Fig 7.2 (a) and (b) respectively. As demonstrated in these figures, the Source and the Body are electrically connected to the GND in the NNEMS configuration. While in the
PNEMS configuration, the Source and the Body are connected to the VDD. With
124 these configurations, CMOS design concepts, system architectures, and design tools can be used to expedite the design of CNEMS logic, computation, and sequential circuits.
(a) (b) Fig 7.2: Four-terminal NEMS switch configurations a) Schematic for N-Channel (NNEMS) b) Schematic for P-Channel (PNEMS)
7.3. CNEMS BASIC LOGIC GATES AND SEQUENTIAL CIRUIT
The configurations of the four-terminal NEMS switch into NNEMS and
PNEMS enable the design of NEMS logic gates and flip-flops by using the same
CMOS design concepts.
In this section, the design and the functionality of CNEMS basic logic gates and
CNEMS D-latch are demonstrated. Accordingly, an arbitrary CNEMS logic or sequential circuit can be designed by using these basic logic gates and flip-flops.
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7.3.1. CNEMS INVERTER
The basic building block for this family is the inverter which consists of two
NEMS in series, one PNEMS and one NNMES as CMOS INVERTER design. The
NEMS inverter is shown in Fig 7.3. When the input voltage A is 0, the voltage difference between G and B of the PNEM is equal or greater than the device pull-in.
In this case, this device is 'on'. While the voltage difference between G and B for the NNEMS is zero, thus, this device is 'off'. In this case, the output voltage is VDD or logic 1. When A is equal or greater than the device pull-in voltage (logic one), the PNEMS is 'off' and the NNEMS is 'on', the output voltage is equal to zero. This behavior is similar to CMOS INVERTER‘s behavior.
Fig 7.3: CNEMS INVERTER
7.3.2. CNEMS NOR
The CNEMS NOR gate consists of two series PNEMS and two parallel
NNEMS as CMOS NOR gate design. The CNEMS NOR gate is shown in Fig 7.4.
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If any input is connected to logic ‗1‘, one of the NNEMS is 'on', connecting the output to logic ‗0‘. The corresponding PNEMS is 'off' which disconnects the output from logic ‗1‘. The output is logic ‗1‘, when both inputs are connected to logic '0'.
In this case, all NNEMS are off and all PNEMS are 'on', connecting the output to logic ‗1‘. This behavior is similar to CMOS NOR gate‘s behavior.
Fig 7.4: CNEMS NOR
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7.3.3. CNEMS NAND
The CNEMS NAND gate consists of two series NNEMS and two parallel
PNEMS as CMOS NAND gate. The CNEMS NAND gate is shown in Fig 7.5. If any input is connected to logic ‗0‘, one of the PNEMS is 'on', connecting the output to logic ‗1‘. The corresponding NNEMS is 'off' which disconnects the output from logic ‗0‘. The output is logic ‗0‘, when both inputs are connected to logic '1'. In this case, all PNEMS are off and all NNEMS are 'on', connecting the output to logic
‗0‘. Consider the case when A and B are logic ‗1‘, the B switch turns 'on' first followed by the A switch which indicates that the output is available. This behavior is similar to CMOS NAND gate‘s behavior.
Fig 7.5: CNEMS NAND
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7.3.4. CNEMS D-LATCH
To construct sequential circuits, sequential elements need to be realized using
CNEMS technology. The basic building block of sequential circuits is the D-latch.
A CNEM D-latch design shown in Fig 7.6 is based and derived from a static CMOS d-latch. The CNEM D-latch has a single D input, a clock, and a single output Q.
The output Q assumes the logical value of the input D when the Clock = '1'. In this case, the circuit is a buffer. When the clock signal goes to zero, the output (Q) preserves its state through the feedback-path. In this circuit, the clock signal is an enable signal which allows the data to be loaded into the Q of the D-latch. The D- latch is used in the design of register files, counters, memory or as a delay element.
Fig 7.6: CNEMS D-latch
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7.4. WORK OVERVIEW
In this work, the four-terminal NEMS switch that inherits the characteristics, reliability issues, and the fabrication process of fabricated two-terminal tuning fork
NEMS switch, as it been described, is studied as switching technology to be used in implementing logic gates and sequential circuits. In this study, this switch is investigated to address the power efficiency problem in Nanometer-CMOS portable embedded systems that are limited by a battery-life, cooling systems, and environment changes rather than the speed. To use this switch in implementing and evaluating circuit architecture, an accurate circuit simulation model that is capable of reproducing the static and dynamic physical device characteristics in circuit environment is need. Fig 7.7 shows how the accurate circuit simulation model ties the gap between the physical device and the architecture that use this device.
Fig 7.7: Circuit simulation model ties the gap between the physical device and the architecture
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7.5. MODELING APPROACH
To ensure the accuracy of modeling and evaluating this switch in a circuit environment, in this work, a new approach is developed. In this approach, the switch is modeled in three levels: Physical level, Macromodel level, and Circuit level. The purpose of physical modeling is to build a physical device model using a
FEA multi-physics simulation tool. The multi-physics simulation tool is used to design the NEMS switch as well as to build a physical model for this switch. The device physical model captures the device‘s physical phenomena and capable of re- producing the physical device‘s characteristics. The construction and configurations of the 3D FEA physical device model for the four-terminal NEMS switch will be demonstrated in next chapter (3D FEA physical model). The physical device model is used to derive and calibrate a 1D device Macromodel. To derive an accurate device Macromodel that is capable of re-producing accurately the device‘s (NEMS switch) characteristics and phenomena with less computation and memory overhead, the 1D device Macromodel will be calibrated based on the 3D FEA physical device model. The derivation of the device Macromodel will be described in (Device Macromodel chapter). The device Macromodel consists of a mechanical lumped model and an electrical circuit model. The mechanical lumped model describes the mechanical movements in the switch. While the electrical circuit model describes the electrical behaviors of the NEMS switch using basic electrical circuit elements. The 1D device Macromodel models mathematically the device and
131 forms a circuit simulation model that is capable of re-producing the device characteristics in a circuit environment.
Finally, to evaluate interconnected NEMS switches, a circuit simulator that is capable of handling interconnected NEMS switches as well as solving the device circuit simulation model (Macromodel) is constructed. The constructed circuit simulator will be demonstrated in NEMS circuit simulation chapter. The circuit simulator enables modeling the NEMS switch at the circuit level by using the device
Macromodel (circuit simulation model). The circuit simulation techniques and the
NEMS circuit simulation model will be used in the circuit simulator. To model the dynamic and static behaviors of the NEMS switch accurately using the circuit simulator, the circuit simulator will be programmed to solve the derived device
Macromodel (mechanical lumped model), and continuously to update the electrical circuit elements of the device Macromodel (electrical circuit model).
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Physical Level: Device: 3D FEA Simulation Dimensions, Material, and Geometry
Extraction device parameters: M, B, K and other device’s simulated characterstics Macromodel Level: Mechanical Lumped Model Electrical Circuit Model
Circuit simulation model for NEMS switch
DC Circuit Level : Circuit Simulation
Circuit Netlist
Input Stimulus
Fig 7.8: NEMS Switch Modeling Approach
SUMMARY
This chapter introduced the four-terminal NEMS switch in terms of design, configurations, basic logic gates and D-latch realization. Moreover, this chapter gave an overview for this work and served as introductory for the rest of this work.
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CHAPTER 8 : 3D FEA PHYSICAL DEVICE MODEL
INTRODUCTION
In this chapter, the construction of a Finite Element Analysis (FEA) physical device model for the four-terminal NEMS switch that has been described in the previous chapter is demonstrated. The FEA physical device model is configured to model different device‘s characteristics using different solvers and algorithms, as will be demonstrated. Furthermore, the FEA physical device model captures the physical phenomena of the NEMS switch accurately. Thus, the FEA physical device model could be used in deriving the mechanical device parameters more accurately than the analytical equation; In addition, it can be used as a reference to derive a an accurate device Macromodel (circuit simulation model).
The following sections illustrate the construction and the configurations of the
FEA physical device model. The FEA physical device model is used in modeling the mechanical and the electrical characteristics of the four-terminal NEMS switch in terms of pull-in voltage, electrostatic force, intermolecular force, damping force, switching time, resonant frequency, leakage current, and contact area.
8.1. 3D FEA PHYSICAL DEVICE MODEL
The 3D FEA physical device model for the four-terminal NEMS switch has been constructed using a FEA multi-physics simulation tool. The FEA multi-physics
134 simulation tool uses different modules and solvers to model the different characteristics of NEMS switch.
The 3D FEA physical device structure that is sufficient to model the physical device is shown in Fig 8.1. This model is constructed using COMSOL multi-physics simulation tool. Generally, to construct 3D FEA physical device model that captures the NEMS switch characteristics using FEA multi-physics simulation (COMSOL) tool, three types of physical modules should be used: structural mechanics module, arbitrary Lagrangian-Eulerian (ALE) module, and electrostatic module. The structural mechanics module handles the movable part(s) in terms of structure; material(s); and dimensions to capture the mechanical characteristics of the movable part(s). The mechanical characteristics of the movable part(s) are the displacement, the switching time, the damping force, and the resonant frequency. The structural mechanics module determines these characteristics when an external force(s) or internal force(s) is/are applied to the movable part(s). The electrostatic module handles the electrostatic characteristics of the NEMS switch. Thus, this module helps in modeling the electrostatic characteristics of NEMS switch including the electrostatic force, the capacitances, the electrical energy, and the leakage current.
The arbitrary Lagrangian-Eulerian (ALE) module is used to account for the changing in the geometry of the 3D device physical model during the deformation process.
135
Fig 8.1:Structure for the 3D FEA physical device model of the four-terminal NEMS switch
The 3D FEA physical device model that is constructed using the default
COMSOL multi-physics modules does not consider the intermolecular forces such as Van der Waals force and Casimir force, which they are dominant in the nanometer regime. For our NEMS switch with small gap (less than or a round 2nm), the Van der Waals force is the dominant intermolecular force. To consider Van der
Waals force in the 3D FEA physical device model, the Van der Waals force is applied on the form of pressure on the movable part(s) of the NEMS switch that are prone to this force. Furthermore, the 3D FEA physical device model does not consider the fringing effect. In general, for wide beam [91], the pull-in voltage of the NEMS switch is affected by the fringing field in a measurable way. In our
NEMS switch, the fringing field effect is negligible due to the very small gap (gap
< 136 device characteristics and phenomena as a result of the small gaps as it has been explained. 8.2. MODELING NEMS SWITCH‘S CHARACTERSTICS USING 3D FEA PHYSICAL DEVICE MODEL In this section, the four-terminal device characteristics are modeled physically using the 3D FEA physical device model that has been demonstrated in the previous section. 8.2.1. PULL-IN VOLTAGE To compute the pull-in voltage of the NEMS switch, the 3D FEA physical device model was configured to use the static parametric solver. The static parametric solver enables us to sweep the voltage difference between the switch electrodes (Body and Gate) till the pull-in voltage occurs. In this configuration, the contact analysis is not considered. Thus, the static parametric solver is stopped just before the pull-in effect occurs [92]. The four-terminal NEMS switch‘s pull-in voltage has been simulated without and with considering the Van der Waals force. The simulate pull-in voltage without considering Van der Waals force is shown in Fig 8.2(a), and the one with considering Van der Waals force is shown in Fig 8.2 (b).These Figures show how the gaps between the two-movable cantilever beams is 137 decreased with increasing the voltage difference between the switch‘s electrodes till the device pull-in voltage happens. (a) (b) Fig 8.2: The Gaps [nm] between the movable parts’ tips with sweeping the applied voltage [V] between the Body and the Gate of the four-terminal NEMS switch a) Pull-in Without considering Van der Waals force b) With considering Van der Waals force 8.2.2. VAN DER WAALS FORCE As it has been mentioned previously, the Van der Waals force is not implemented in the physical modules of the FEA COMSOL simulation tool. Thus, to account for this force in the FEA physical device model, a pressure of the Van der Waals force is applied to the movable part‘s surfaces that are prone to this force. 2 2 The Van der Waals pressure is shown in equation (8.1), where Hm (Hm = π Cρ ) is the Hamaker constant which lies in the range (0.4 − 4)10−19 J [81], C is a constant charactering interactions between the two atoms, g0 is the initial gap between the overlapping surfaces, and g is the gap variations. 138 To compute the Van der Waals force with sweeping the applied voltage between the Body and the Gate, an integration of equation(8.1) over the movable beam‘ surfaces that are prone to this force is performed as shown in equation(8.2). The Van der Waals force versus the applied voltage is shown in Fig 8.3 In this figure, Fvdw1 is modeled the Van der force between the two movable cantilever beams, while Fvdw2 is modeled the Van der Waals force between the movable part of the electrode and its fixed part as shown in figure. (8.1) (8.2) Fig 8.3: The simulated Van der Waal’s force on the movable beam (Body) surfaces that is prone to this force. 139 8.2.3. ELECTROSTATIC FORCE The electrostatic force is already implemented in the electrostatic module of the 3D FEA physical device model. Thus, to examine the electrostatic force that is generated on the movable parts, an integration of the generated electrostatic pressure on the movable parts‘ surfaces that are prone to this force is conducted. The electrostatic force that is generated on each movable cantilever beam versus the applied voltage between the Body and the Gate is shown in Fig 8.4. Fig 8.4: The electrostatic force that is generated on movable beam (Body) versus the applied voltage difference between the Body and the Gate 8.2.4. CAPACITANCES To compute the four-terminal NEMS switch capacitances using the 3D FEA physical device model, an integration of equation (8.3) over the overlapping surfaces is conducted as shown in equation (8.4), where is the permittivity of 140 vacuum, is the initial gap, u is the displacement of the movable part in the movement direction, is the thickness of the dielectric layer, and is the dielectric constant. The capacitance between the body and the gate versus and the capacitance between the Body and Drain/Source versus the applied voltage difference between the Body and the Gate are shown in Fig 8.5. (8.3) (8.4) Fig 8.5: Capacitance between the Body and the Gate and The capacitance between the Body and the Drain/Source versus the applied voltage between the Body and the Gate 141 8.2.5. MECHANICAL ENERGY AND ELECTRICAL ENERGY The mechanical and electrical energy are generated when solving the 3D FEA physical device model. The mechanical energy is computed under the structural mechanics module. The electrical energy is computed under the electrostatic module. The mechanical and electrical energy versus the applied voltage between the Body and the Gate are shown in Fig 8.6. Fig 8.6: The mechanical and electrical energy for the four-terminal NEMS switch based the 3D FEA physical model 8.2.6. TUNNELING LEAKAGE CURRENT To model the tunneling leakage current in the 3D FEA physical device model, the Fowler-Nordheim tunneling current density equation is applied. To compute the tunneling current, the electrical field that is generated under the electrostatic module 142 of the 3D FEA physical device model is used. By solving the 3D FEA physical device model, the tunneling current density is computed. To compute the tunneling current, an integration of the tunneling current density equation is performed over the NEMS switch‘s surfaces that are expected to have a tunneling current. The tunneling current density equation that is used in the 3D FEA physical device model is expressed in equation(8.5), and the tunneling current is an integration of this formula as expressed in equation(8.6), where A is the overlapping area cm2, J is the current density in A/cm2, φ (eV) is the emitter work function ( for Nickel φ is equal to 5.15 eV [93]), It is the tunneling current (A), and E is the electric field (V/cm) perpendicular to the overlapping surface of the NEMS electrodes. Fig 8.7 shows the tunneling current between the Body and the Drain versus the applied voltage between the Body and the Gate. (8.5) (8.6) 143 Fig 8.7: The Simulated tunneling current [A] between the Body and the Drain/Source versus the applied voltage difference [V] 8.2.7. SWITCHNIG TIME To compute the switching time using the 3D FEA physical device model, the structural mechanics module is reconfigured to consider the viscous damping using the Rayleigh damping model. To explain this model, a 1D mechanical system is described in equation (8.7), where m is the effective mass of the movable part, u is the displacement, c is the viscous damping coefficient, k is the stiffness coefficient, and f(t) is the external force that is applied to the movable part. In this model, the damping is proportional to a linear combination of the stiffness and the mass as shown in equation (8.8), where αdm is the mass damping coefficient, βdk and is the stiffness damping coefficient [92]. (8.7) 144 (8.8) In general, in most application mass damping coefficient is set to zero. Thus, to compute the stiffness damping coefficient we can use equation (8.9), where W is the width of the movable part, is the effective viscosity, f0 is the first natural frequency of the movable beam, g0 is the initial air gap, ρ is material density of the movable part, and H is the thickness of the movable part. (8.9) After set the Rayleigh damping coefficients, the pull-in voltage is applied between the Body and the Gate, and the transient parametric solver is used to solve the 3D FEA physical device model. For our four-terminal NEMS switch, the damping force is very small, where the gap is very small (gap<< the electron free path of the air (70 nm)). The damping forces will be discussed in details in the damping force subsection. The switching time for the four-terminal NEMS switch using the 3D FEA model is shown in Fig 8.8. 145 (a) (b) Fig 8.8: The switching time when the applied voltage between the Body and the Gate is equal to the device’s pull-in voltage a) Without considering Van der Waals force b) With considering Van der Waals force 8.2.8. DAMPING FORCES The squeeze film damping is the dominant damping in MEMS/NEMS switches. As it has been explained in analysis and design chapter, the squeeze film damping consists of two components: viscous damping, and elastic damping. To model the squeeze film viscous damping, the FEA simulation tool ( COMSOL multi-physics) model the viscous damping force using a especial structural mechanics module that accounts for the viscous damping using the modified Reynolds equation (8.10), where, where pF denotes the gas film pressure variation, p = pA + pF is the total fluid pressure consisting of the ambient pressure and the variation, g = g0 +Δg is the gap height consisting of the initial gap and the deformation in the normal direction of the boundary, and µ is the fluid viscosity at normal conditions. 146 The term Qch denotes the relative flow rate function that accounts for the rarefied gas effects. (8.10) (8.11) To consider the elastic damping force in the 3D FEA model, the elastic damping pressure is applied on the movable surfaces that are prone to this force. The elastic damping pressure is expressed in equation (8.11). The 3D FEA physical device model, with the above configuration to model the squeeze film damping, is solved using the transient parametric solver. Fig 8.9 shows the damping forces on the movable parts of the NEMS switch that are modeled using the 3D FEA model. Where Fig 8.9 (a) shows the viscous damping forces on each movable beam as shown, and Fig 8.9(b) shows the elastic damping forces on each movable beam as shown. The simulated Knudsen number for the gap between the two movable parts and for the gap between the movable part of each electrode and its fixed part are shown in Fig 8.10. 147 (a) (b) Fig 8.9: Squeeze film damping forces on each movable beam: (a) The viscous damping force (b) The elastic damping force Fig 8.10: Knudsen number for changing the gaps versus the time 148 8.2.9. CONTACT AREA AND CONTACT RESISTANCE To model the contact area in the 3D FEA model, the contact analysis should be included. To configure the 3D FEA physical model to consider the contact analysis, the 3D FEA physical model is re-constructed using the structural mechanics module, and a contact pairs is created where a contact between surfaces should be happened. To model the contact operation in the constructed 3D FEA module, a pressure of the electrostatic force and Van der Waals force are applied on the movable parts and the parametric solver is used. The parametric solver solves the contact problem using the augmented Lagrangian method [92].The contact area versus the applied voltage between the Body and the Gate is shown in Fig 8.11. Fig 8.11: The contact Area between the Body and the Drain/Source versus the applied voltage between the Body and the Gate 149 The contact area for the 3D FEA physical device model as shown in Fig 8.11 is smaller than the electron free path of the electrodes material (~ 100nm [94]). Consequently, the electron transport mechanism for the four-terminal NEMS switch is a ballistic [78]. And this implies that the major contributor to the contact resistance for this switch is a Shavin resistance [78]. By fitting the contact area to a circular area, the Sharvin resistance is given by equation (8.12), where k is the Knudsen number (k= r is the contact radius, and ρ is the resistivity of the contact material. (8.12) 8.2.10. NATURAL FREQUENCIES To model the natural frequencies using the 3D FEA physical device model, the 3D FEA model is configured to be solved using the Eigen frequency solver. The natural frequency for the Body beam (in the direction of the movement) is shown in Fig 8.12, and the natural frequency for the D-G-S beam (in the direction of the movement) is shown in Fig 8.13. 150 Fig 8.12: the natural frequency for the Body beam (=0.4655 GHz) in the movement direction Fig 8.13: The natural frequency for the D-G-S beam (=0.4509 GHz) in the movement direction 8.2.11. RESONANT FREQUENCY The resonant frequency for the four-terminal NEMS switch with two-movable beams is equal to the summation of the resonant frequency for the Body movable beam and the D-G-S movable beam. The resonant frequency for each beam is molded by configuring the 3D FEA physical model to be solved using the frequency response solver. And by applying the pull-in voltage between the switch electrodes and sweeping the frequency, the displacement of the movable part is computed. In this case, the maximum displacement of the movable part occurs at the resonant 151 frequency. The frequency response for the Body movable part and the D-G-S movable part are shown in Fig 8.14 (a) and Fig 8.14(b) respectively. (a) (b) Fig 8.14: The simulated resonant frequency from the 3D FEA device model a) The Body movable part b) The D-G-S movable part 8.3. MECHANICAL DEVICE COEFFICIENTS EXTRACTION To model the four-terminal NEMS switch in a circuit environment, an accurate 1D Macromodel (circuit simulation model) is needed. In this work, a new approach is used. In this approach, the mechanical coefficients are computed from the 3D FEA physical device model. Using this approach demonstrates more accuracy in computing the device‘s mechanical coefficients over the analytical equations that have been reported in literature. In this approach, the mechanical device‘s coefficients are extracted from the 3D FEA physical device model. Thus, the 3D FEA physical device model serves as a reference model in deriving and validating 152 the accuracy of the derived device circuit simulation model (Macromodel) as will be demonstrated in next chapter. In this section, the extraction of the device‘s mechanical coefficients: effective stiffness constant (keff), effective mass (meff), and damping coefficients (elastic damping coefficient (kd), and viscous damping coefficient (cd)) from the 3D FEA physical device model are explained. These mechanical coefficients will be used to derive an accurate device Macromodel as will be demonstrated in next chapter. 8.3.1. EFFECTIVE STIFFNESS CONSTANT (keff) To derive the effective stiffness constant for each movable part, the 3D FEA physical device model is configured to conduct an integration to compute the mechanical energy over the movable part‘s sub-domain during the solution of the 3D FEA physical device model. Consequently, the total mechanical energy for each movable part is computed in the solution of the 3D FEA model. To compute the effective stiffness constant, the computed mechanical energy is divided by half the quadratic beam‘s tip displacement according to the mechanical energy equation ( , where u is the beam‘s tip displacement of the movable part). The derived effective stiffness constants using the 3D FEA physical model are shown in Fig 8.15, where K1 is the effective elastic coefficient for the Body beam, and K2 is 153 the effective elastic coefficient for the D-G-S beam. In this case, the total effective elastic coefficient for the whole switch is the summation of K1 and K2. (5.13) Fig 8.15: The derived effective stiffness constant for the Body beam (K1) and the D- G-S beam (K2) 8.3.2. EFFECTIVE MASS (meff) The effective mass for each movable beam is derived by solving the 3D FEA physical model using the frequency response solver as demonstrated in the resonant frequency subsection. And by using resonant frequency equation ( ) [62], the effective mass is computed by substituting the derived effective stiffness constant and the derived resonant frequency from the 3D FEA physical device model in the resonant frequency equation as shown in equation (5.14).The 154 effective stiffness constant for each beam is shown in Fig8.15, and the resonant frequency for each beam is shown in Fig 8.14. (5.14) 8.3.3. DAMPING COEFFICIENTS (cd, kd) The damping coefficients are derived from the 3D FEA physical device model by computing the damping forces. As it has been demonstrated previously, the squeeze film damping has two components: viscous damping and elastic damping. Actually, the viscous damping force is proportional to the speed of the movable part as shown in equation (8.15), while the elastic damping force is proportional to the displacement of the movable part as shown in equation (8.16). Thus, the viscous damping coefficients and the elastic damping coefficients are computed using the damping forces that have been modeled in the 3D FEA model and by using equation (8.15) and equation (8.16). The derived viscous and elastic damping coefficients are shown in Fig 8.16 (a) and Fig 8.16 (b) respectively. (8.15) (8.16) 155 (a) (b) Fig 8.16: Derived damping coefficients for each movable beam from the 3D FEA model a) Viscous damping coefficients b) Elastic damping coefficients 8.4. DEVICE COEFFICIENTS (keff, meff, cd, kd): 3D FEA PHYSICAL MODEL VERSUS ANALYTICAL EQUATIONS In this section, the mechanical device coefficients (keff, meff, cd, kd) for the four- terminal NEMSs are computed using the analytical equations 156 (8.17)(8.18,8.19)(8.20)(8.21)[62][70,95][96,72][71]. Table 13 shows the computed mechanical device coefficients using the analytical equations versus the derived mechanical coefficients using the 3D FEA physical device model. (8.17) (8.18) (8.19) (8.20) (8.21) Table 8.1: Mechanical Device Coefficients Mechanical 3D FEA Physical Analytical Equations Coefficients Model L= 1um L = 640 nm Effective K(B) ~ 1000 K (B)=393.510 K (B)=1501.12 stiffness K(D-G-S) ~ 950 K (D-G-S)=339.96 K (D-G-S)=1296.85 constant Effective M(B)= 1.1 e-16 . Equation (8.18) . Equation (8.18) mass M(D-G-S)= 1.19e-16 M(B)=1.4685e-16 M (B)=9.3985e-17 M(D-G-S)=1.2474e-16 M(D-G-S)=7.98336e-17 . Equation (8.19) . Equation (8.19) M(Body)=5.15e-16 M(B)=3.29e-16 M(D-G-S)=4.37e-16 M(D-G-S)=2.8e-16 Viscous Cd1=1.25e-9–3.75e-9 Cd=7.84417e-8 Cd=5.020e-8 damping Cd2=0.75e-9 – 1.75e-7 coefficients Elastic . Kd1=13 – 8 Kd=13.51 Kd=8.6464 damping . Kd2= 8 – 3.5 coefficients 157 SUMMARY This chapter demonstrated the construction of the 3D FEA physical device model for the four-terminal NEMS switch. The 3D FEA physical device model was constructed and configured to be able to capture the four-terminal NEMS switch phenomena and produce the device characteristics. Furthermore, the 3D FEA physical device model was used to derive the mechanical device‘s coefficients including the effective stiffness constant, the effective mass, and the damping coefficients, as it has been explained. The derived mechanical device‘s coefficients will be used in deriving an accurate 1D Macromodel (circuit simulation model) that is capable of reproducing the device characteristics in a circuit environment as will be demonstrated. Finally, to validate the accuracy of the used approach in computing the mechanical device‘s coefficients over the analytical equations that have been reported in literature, a comparison between the mechanical coefficients that have been computed using the 3D FEA physical model and the one that have been computed using the analytical equations was presented. The accuracy of the derived mechanical coefficients from the 3D FEA physical device model will be demonstrated, when it used in the mechanical lumped model as will be shown in next chapter. 158 CHAPTER 9 : DEVICE MACROMODEL INTRODUCTION In this chapter, the derivation of an accurate device Macromodel for the four-terminal NEMS switch is demonstrated. The accuracy of the device Macromodel is achieved by accurately model the mechanical behaviors of the device using an accurate mechanical lumped model and accurately model the electrical behaviors of this device using an accurate electrical circuit model. In this work, a new approach is used to derive and calibrate these two coupling models. In this approach, the 3D FEA physical device model is used. Finally, to verify the capability of the derived device Macromodel (circuit simulation model) in reproducing accurately the static and the dynamic electro- mechanical characteristics/phenomena in comparable measurements to the 3D FEA physical device model over the analytical equations, a demonstration that shows the evaluations of the device‘s characteristics/phenomena based on the derived device Macromodel, the 3D FEA physical device model, and the analytical equations are presented. 9.1. DEVICE MACROMODEL VERSUS 3D FEA PHYSICAL DEVICE MODEL To capture the characteristics of the physical device accurately, in the 3D FEA physical device model, complex physical PDEs equations are solved using numerical techniques for the all meshed segments of the simulated physical device 159 structure. Thus, modeling the device physically, using a 3D FEA model, needs high computation requirements in terms of memory capacity and CPU computation speed. Furthermore, generally, FEA physical device model needs different configurations and solvers to model the different characteristics physically. Consequently, the 3D FEA physical device model cannot be used in circuit simulation environment to evaluate a circuit architecture that is implemented or uses the physical device. Thus, there is a need to derive an accurate 1D device Macromodel that is capable of reproducing the physical device characteristics with comparable measurements and less computation requirements to the 3D FEA physical device model. In this manner, the accurate device Macromodel enables modeling the physical device efficiently in a circuit simulation environment as will be demonstrated. 9.2. DEVICE MACROMODEL To evaluate accurately NEMS circuit architecture in terms of functionality, delay, and power consumption, a device circuit simulation model (Macromodel) that is capable of reproducing accurately the static and the dynamic device‘s electro- mechanical characteristics in a circuit simulation environment is needed. To derive a device Macromodel that is capable of re-producing the dynamic and the static behaviors of a NEMS switch accurately, the device Macromodel should be composed 160 of coupling two models: a mechanical lumped model and an electrical circuit model. The mechanical lumped model models the mechanical behaviors of the NEMS switch, while the electrical circuit model models the electrical behaviors of the NEMS switch. In following subsections, the lumped mechanical model and the electrical circuit model for the four-terminal NEMS switch will be described. 9.2.1. MECHANICAL LUMPED MODEL The accuracy of the mechanical lumped model, which is generally described by the spring-mass-damper equation, is confined by: 1) the accuracy of the used mechanical coefficients 2) the accuracy of computing the load forces during the dynamic mechanical movements, and 3) the accuracy of the used technique to solve the Second degree Differential Equation (2nd DFE) that describes the mechanical lumped model. In this work, the mechanical lumped model that describes the mechanical behaviors of the NEMS switch for each movable cantilever beam is expressed by the modified spring-mass-damper equation (9.1), where un is the tip displacement for each cantilever beam, k is the total effective stiffness coefficient, m is the effective mass, B is the viscous damping coefficient, and kd is the elastic damping coefficient. In this equation, the mechanical coefficients have been extracted from the 3D FEA physical device model as it has been demonstrated in the previous chapter. And the load forces (electrostatic and Van der Waals forces) are computed accurately by considering the gap variations along the movable beam length as shown in Fig 9.1. 161 This has been achieved by segmentation each cantilever beam along its length to n segments. The electrostatic force on each segment is computed using equation (9.2). The Van der Waals force (Fvdw1) on each segment is computed using equation (9.3), and The Van der Waals force (Fvdw2) on each segment is computed using equation (9.4). Thus, as shown in equation (9.1), the total load (electrostatic and Van der Waals forces) forces on each cantilever beam is equal to the summation of the load forces on all segments along the length of the cantilever beam. Fig 9.1: NEMS Mechanical Lumped Model 162 Where WG is the width of the Gate, WBS is the width of the overlapping area between the Body and The Source, WBD is the width of the overlapping area between the Body and the Drain, d is the thickness of the dielectric layer (Si3N4) that is coated the Gate, Li is the length of each segment (Li=L/n, L1 and L2 as shown in Fig 8.1 , n is the number of segments), g0 is the initial gap between the movable electrodes; and it is the initial gap between the movable part electrode and its fixed part ( 3D FEA physical model chapter), ui is the displacement of segment i of each cantilever beam; where ui is computed using equation(9.5); is the permittivity of the dielectric layer, is the vacuum permittivity, and Hm is the Hamaker constant. (9.5) To solve the Second Degree Differential Equation (2nd DFE) (9.1) that describes the dynamic movement of the cantilever beam, the fourth- order Runge-Kutta method is used [97]. The solution of the 2nd DFE is conducted every time step (h) to compute the displacement of the cantilever beam‘s tip, and accordingly, update the electrostatic force, the Van der Waals force, and the electrical elements as will be demonstrated in the next subsection. 163 9.2.2. ELECTRICAL CIRUIT MODEL The accuracy of the electrical circuit model is defined by the accuracy of computing its electrical circuit elements during the dynamic and the static behaviors of the NEMS switch as well as the accuracy of the used electrical circuit model in describing the electrical behaviors of the NEMS switch. In this work, the accuracy of the electrical circuit model is achieved by accurately describing the electrical behaviors of the NEMS switch using electrical circuit elements and by accurately computing these electrical elements in the static and the dynamic modes of the NEMS switch. The electrical circuit model that describes the four-terminal NEMS switch electrically during the switching operation or in the OFF state is shown in Fig 8.2, while the electrical circuit model that describes the four-terminal NEMS switch electrically in the ON state is shown in Fig 8.3. To accurately compute the electrical circuit elements of the electrical circuit model, the gap variations along the cantilever beam length are considered in computing the variable capacitors and resistors. In this manner, the capacitor and resistor that associated with the corresponding segments are computed with considering the gap variations between these segments. 9.2.2.1. Electrical Circuit model in the Switching/OFF State The electrical circuit elements of the electrical circuit model, in the switching/OFF state, can be categorized into groups: fixed electrical circuit elements and variable electrical circuit elements. The fixed electrical elements are 164 RG, RS, RD, RB1, RB2, CGS, and CGD. These electrical elements are computed using the traditional capacitor and resistor equations. Fig 9.2: The electrical circuit model for the four-terminal NEMS switch in the Switching/OFF state (1)Variable Parasitic Capacitors The variable capacitors are CBD, CBG, CBS. These capacitors are computed using equation (9.6) (9.7) (9.8) respectively, where all the parameters as they have been defined previously. 165 (2)Variable Parasitic Resistors The variables resistors ( RBG, RBS, RBD) of the electrical circuit model in the switching/OFF state are used to model the leakage current and switching current that result of changing the variable capacitors during the switching operation. Accordingly, the variable resistors, in the electrical circuit model of the NEMS switch, model three types of currents: (a) Tunneling leakage current (b) Surface leakage current (c) Switching current that result from changing the variable capacitors as a result of the mechanical movements of the movable parts. In this model, the tunneling current is computed using modified Fowler-Nordheim equation (9.9), where Ei (V/cm) is the electrical field corresponding with the overlapping i segments, W (m) is the width of the overlapping segments, and the other parameters as they have been defined previously. The switching current is computed using equation (9.10), where h is time step, C(t) is the total capacitance between the overlapping surfaces at time t, C(t-h) is the total capacitance between the overlapping surfaces at t-h, and V(t) is the voltage difference between the overlapping surfaces at the time t. The surface leakage is a process dependent, and this current could be fitted from the fabricated device measurements. It is important to point out that the tunneling current and surface current in NEMS switches can be minimized during the fabrication process by surface coating and plasma cleaning. (9.9) (9.10) 166 9.2.2.2. Electrical Circuit Model in the ON State The electrical circuit elements of the electrical circuit model, when the Body is in contact with the Drain/Source (ON state), are fixed. The following resistors and capacitors, RG, RS, RD, RB1, RB2, CBG, CGS, and CGD, are computed using the traditional capacitor and resistor equations. The resistor between the Body and the Gate (RBG) models the leakage current between the Body and the Gate in the ON state. The leakage current in the ON state consists of the surface current leakage and tunneling current leakage. The tunneling leakage current is computed using equation (9.9) and equation (9.10) as it has been demonstrated. Fig 9.3: The electrical circuit model for the four-terminal NEMS switch in the ON state To compute the contact resistance between the Body and the Drain/Source (Rcontact), the contact area should be computed. The contact area for the four- 167 terminal NEMS switch can be computed either by solving the contact problem in the 3D FEA physical device model as it has been demonstrated in the previous chapter, or by using equation(9.11)[98], where Hr is the material hardness , for Nickel the Brinell hardness is equal to 700MPa[99], and ξ is the deformation coefficient; the deformation coefficient value is ranging from 0 to 1 depending in the deformation type(0.3>ξ for elastic deformation, 0.3<ξ<0.75 for elastic-plastic deformation, 0.75<ξ<1 for plastic deformation It has been found from the both approaches that the computed contact area, when it is fitted to the circle, is smaller than the electron free path of the contact materials ( for pure metallic material, the electron free path ~ 100 nm[94]). Thus, the electron transport mechanism for the four-terminal NEMS switch is a ballistic [78]. This implies that the major contributor to the contact resistance in the four-terminal NEMS switch is a Shavin resistance [78]. The Sharvin resistance is given by equation (9.12), where k is the Knudsen number (k= r is the contact radius, and ρ is the resistivity of the contact material. / (9.11) (9.12) 168 9.3. VERIFICATION OF THE DERIVED DEVICE MACROMODLE To validate the capability of derived circuit simulation model in modeling the four-terminal NEMS switch accurately in the static and dynamic modes, an evaluation for the device‘s characteristics/phenomena have been conducted using The constructed 3D FEA physical device model and the derived device Macromodel. In Table 9.1, the evaluations for some device‘s characteristics/phenomena are presented. This table shows that the derived device Macromodel is capable of reproducing the dynamic and static electro-mechanical device‘s characteristics/phenomena in comparable measurements to the 3D FEA physical device model. Furthermore, Fig 9.4, Fig 9.5, Fig 9.6, and Fig 9.7 demonstrate the capability of the derived device Macromodel in computing the gap variations, the changing of the electrostatic force, Van der Waals force, and the capacitances during the switching operation in comparable measurements to the 3D FEA physical device model. Table 9.1: Characteristics of the four-terminal NEMS switch Characteristics/phenomena Derived Macromodel 3D FEA Model Pull-in Voltage (Vpin) 1.20 V ~1.25 V Switching time 1.4 ns ~1.4 ns Gap at (VBG = 0.8 V) 1.38 nm 1.4 nm Capacitance CBG,CBD (at CBG= 8.08 e-15 F CBG= 8.5 e-15 F t=1.0 ns, VGB=1.2 V) CBD=6.109e-17 F CBD=6.00e-17 F Van der Waals force when Fvdw1=1.43e-7 N Fvdw1=1.45e-7 N VGB=1.0 V Fvdw2=0.5e-7 N Fvdw2=0.72e-7 N Electrostatic force when Felec=2.32 e-7 N Felec=2.4 e-7 N VGB=1.0 V 169 9 Fig 9.4: Gap versus time from the 3D FEA physical device model and from the device Macromodel Fig 9.5: Electrostatic force versus time from the 3D FEA physical device model and from the device Macromodel 170 Fig 9.6: Van der Waals force from the 3D FEA physical device model and the device Macromodel Fig 9.7: Capacitances versus time from the 3D FEA physical device model and the device Macromodel 171 SUMMARY This chapter demonstrated the derivation of an accurate device circuit simulation model (Macromodel) for the four-terminal NEMS switch. In this demonstration, the accuracy of the circuit simulation model was achieved by accurately modeled the mechanical characteristics of this switch using the derived mechanical lumped model, and modeled accurately the electrical characteristics of the NEMS switch using the derived electrical circuit model. The accuracy of these coupling models was achieved by extracting the mechanical device‘s coefficients from the 3D FEA physical device model and considering the gap variations along the cantilever beams‘ length during the switching operation. This in turn enables the device circuit simulation model (mechanical and electrical) to be capable of modeling accurately the static and the dynamic electro-mechanical characteristics of this switch in a circuit environment. Finally, to demonstrate the accuracy of the derived circuit simulation model (Macromodel) in reproducing device characteristics in comparable measurements to the 3D FEA physical device model over the analytical equations, the device‘s characteristics/phenomena were evaluated using the derived device Macromodel, the constructed 3D FEA physical device model, and analytical equations. 172 CHAPTER 10 : CNEMS CIRCUIT SIMULATION INTRODUCTION This chapter discuses a circuit simulator program in terms of motivation, structure, techniques, and solution. Furthermore, to use this circuit simulator in evaluating NEMS circuit architecture, the derived circuit simulation model is implemented in this simulator. Thus, the constructed circuit simulator program is capable of solving the derived circuit simulation model (Macromodel) accurately and handling interconnected NEMS switches. Accordingly, an arbitrary NEMS circuit can be evaluated accurately using this simulator in terms of functionality, timing, and power dissipation. 10.1. MOTIVATION BEYOND THE CIRUIT SIMULATOR The circuit simulation is an important tool for designing and evaluating integrated circuits (ICs).Actually, it is considered as a pre-manufacturing design verification strategy to predict circuits ‗behaviors before actual circuits are being fabricated. It is important to point out that the utility of a simulator as a tool for designing and analyzing circuits depends on the adequacy of the device‘ circuit simulation models that are used in the simulator [100]. In this work, to develop a circuit simulator program that is capable of evaluating accurately NEMS circuit architecture; the derived device circuit simulation model 173 (Macromodel) that has been demonstrated in the previous chapter will be implemented in the circuit simulator program. The circuit simulator program will be discussed in the following sections in terms of architecture, implementation, and solution. 10.2. CIRCUIT SIMULATOR ARCHITECTURE Generally, the architecture of a circuit simulator, as shown in Fig 10.1, consists of: 1) Network topology 2) Device mathematical Models, and 3) Circuit simulator engine. The network topology of a circuit is the description of a circuit design in terms of nodes, branches, and circuit elements. In addition to, the initial circuit configurations. The device mathematical models are the models that used in evaluating the circuit elements mathematically in a circuit environment. The circuit simulator engine is the processing unit of the circuit simulator program, where the circuit waveform solutions should be generated based on the circuit network description and circuit elements ‗mathematical models. In this work, the circuit simulator architecture‘s components and their implementations are described in the following subsections. 174 Fig 10.1: Circuit simulator architecture 10.2.1. NETWORK TOPOLOGY AND SETUP To simulate an arbitrary NEMS circuit, a circuit description should be provided to the circuit simulator. The circuit description consists of: 1) network topology: circuit elements and topology of each element within the circuit, and 2) the circuit setup. To identify the circuit topology, all the nodes in the circuit should be indexed. In this manner, the topology for each circuit element is described by the nodes‘ indexes that are connected to its terminals; according to the circuit design (schematic). And to identify the circuit setup, the circuit‘s initialization and analysis type should be determined. 175 Generally, the circuit description, in terms of network topology and setup, is called Netlist file. In our circuit simulator, to describe a NEMS circuit design, the SPICE format is used. 10.2.2. MATHEMATICAL MODELS To enable the circuit simulator to evaluate an arbitrary circuit, the mathematical models for its circuit elements should be provided to the circuit simulator engine. The mathematical model characterizes the corresponding device by a set of equations relating current, charges, flux, and voltages. It is important to understand that the accuracy of the circuit simulator tool is highly coupled with accuracy of the used mathematical models. The constitutive equations, mathematical equations, for the basic electrical elements are shown in Table 10.1. For storage-charging elements and nonlinear elements, a companion model that linearizes the I-V relationship is used at each iteration before formulating the mathematical equations that model the device. 176 Table 10.1: Constitutive Equations (BCE) for basic elements Element Mode Branch Eqn Linear Resistor All v = R·i Nonlinear Resistor All i=i(v), or i=i(v,t) Linear Capacitor Transient i = C·dv/dt Nonlinear Capacitor Transient i=C(t)dv/dt+V(t)dC/dt Inductor Transient v = L·di/dt Voltage Source Transient v = vs Current Source All i = is VCVS All vs = AV · vc VCCS All is = GT · vc CCVS All vs = RT · ic CCCS All is = AI · ic The NEMS switch is modeled in our circuit simulator by using the derived device Macromodel that have been introduced in the previous chapter. The derived NEMS Macromodel consists of coupling two models: mechanical lumped model and electrical circuit model. The electrical circuit model describes the NEMS switch by using basic electrical elements that are controlled by the mechanical lumped model. The mechanical lumped model models the mechanical behavior of this switch. The mechanical lumped model, 2nd DFE modified spring-mass-damper 177 equation, is solved by the simulator engine numerically by using the fourth-order Runge-Kutta method every time step. Accordingly, the electrical circuit elements of the electrical circuit model are modified. 10.2.3. CIRCUIT SIMULATOR ENGINE The circuit simulator engine is the heart of the circuit simulator tool. The circuit simulation engine evaluates an arbitrary circuit based on its description, topology and setup, and its mathematical elements‘ models. Thus the circuit simulator engine should be programmed to be capable of performing the following tasks: 1. Read a circuit description from the Netlist file. 2.Formulate a set of equations for a given circuit, which is described in the Netlist file, based on the circuit topology, using Kirchhoff‘s laws (KCL and KVL), and the circuit elements mathematical models (Constitutive equations). 3. Solve the system of equations to generate the requested outputs. 10.3. CIRUIT SIMULATOR IMPLEMENTATATION In the following subsections, the implementation of the circuit simulator engine is demonstrated briefly. 178 10.3.1. READING A CIRUIT DESCRIPTION The constructed circuit simulator has been programmed to read the Netlist file for an arbitrary circuit and store its circuit elements in link lists to be ready for further processing, where each circuit element type has a separate link list. Each link list consists of instances of a specific structure called symbol. The structure symbol is mainly defined each circuit element by its topology, value, and device characteristics. For example when the circuit simulator reads a Netlist file for NEMS NAND gate that shown in Fig 10.2, the link lists shown in Fig 10.3 are constructed. TITLE NAND * V6 5 0 DC 1.300 VA1 1 0 PULSE (0.0 1.3 0.0NS 0.0NS 0.0NS 5NS 10NS ) VA2 2 0 PULSE (0.0 1.3 0.0NS 0.0NS 0.0NS 5NS 15NS ) * N1 3 1 5 5 PNEMS N2 3 2 5 5 PNEMS N3 3 1 4 4 NNEMS N4 4 2 0 0 NNEMS C1 3 0 100F * .TRAN 0.01NS 100NS .PRINT TRAN V(1) V(2) V(3) I(V6) I(VA1) I(VA2) .END Fig 10.2: Netlist for CNEMS NAND gate 179 End Start V1 V2 V3 (a) End Start N1 N2 N3 N4 (b) End Start End R1 Start (d) (c) End End Start Start (e) (f) Fig 10.3: Link lists for CNEMS NAND gate a) Voltage source link list b) NEMS switch link list c) Resistor link list d) Capacitor link list e) CMOS transistor link list f) Current source link list 10.3.2. FORMULATING SYSTEM OF EQUATIONS After the circuit simulator engine reads a given circuit as has been demonstrated, a system of equations are formulated. The system of equations are formulated based on the circuit topology; Kirchhoff‘s laws which are also known as topological equations; and the circuit elements ‗mathematical models (constitutive equations). Generally, In circuit simulations, there are three methods to formulate a system of equations for a given circuit by combining the conservation laws (topological 180 equations: KCL and KVL) and The branch constitutive equations( devices mathematical models).These methods are 1)Spare Table Analysis (STA) 2)Nodal Analysis(NA), and 3)Modified Nodal Analysis ( MNA). The STA needs sophisticated programming techniques, and data Structures are required for time and memory efficiency. The NA is the basis method for the MNA, but it cannot handle floating voltage sources, VCVS, CCCS, and CCVS. The MNA technique overcomes the limitation of the NA technique. For the advantages of MNA technique over the STA and NA techniques as has been demonstrated, our circuit simulator program has been programmed to formulate a system of equations for a given circuit by using the MNA technique. The MNA matrix is shown in equation(10.1), where Yn is the node admittance matrix excluding the contributions due to voltage sources and current controlling elements, B contains partial derivatives of the Kirchhoff current equations with respect to the additional current variables and thus ‘s for the elements whose branch relations are introduced, C is the branch constitutive relations that are differentiated with respect to unknown vector, V is the common datum voltages, I is the branch currents for the circuits which contain voltage sources and other elements whose currents are controlling variables, and the vectors J and F are excitations which include the current sources as well as the initial values from the previous time steps corresponding to capacitors and inductors[101]. (10.1) 181 The MNA matrix for a given circuit is generated by using the MNA stamp matrix for each circuit element. The stamp matrices that have been used to construct the MNA matrix for arbitrary circuit are shown in Table 10.2. The circuit simulator engine arbitrarily labels all the nodes for a given circuit, and then continues to label the voltage sources as well as all the nodes (internal and external nodes) of the electrical circuit model for the NEMS switches. For each circuit element, its contributions to the MNA matrix can simply be read from the Table 10.2 and stamped into the MNA matrix according to its nodes numbers. For NEMS switches, each basic circuit elements of the NEMS‘s electrical circuit model, which has been demonstrated previously, is stamped into the MNA matrix separately. Thus, the system equations for a given circuit are formulated in a matrix form as in equation (10.2), where X is an n-vector of unknown variables; Y is a specified n- vector; and A is an n *n nonsingular real or complex matrix. This equation can be easily solved by using numerical techniques that have been used to solve system of linear equations. (10.2) 182 Table 10.2: MNA stamps matrices for basic circuit elements in transient mode Circuit Element Stamp Matrix Resistor i j i +1/R -1/R j -1/R +1/R Capacitor i j RHS i +C/h -C/h j -C/h +C/h CMOS transistor s d g RHS s +dVgs+dVds -dVds -dVgs +Ids d -dVgs-dVds +dVds +dVgs -Ids Where : dVgs =V(g)-V(s), dVds=V(d) –V (S), Ids: the linearized current from the I-V CMOS equation Independent voltage source i j Iv RHS i +1 j -1 BR 1 -1 E Independent current source i j RHS i +J j -J 10.3.3. SOLVING SYSTEM OF EQUATIONS The solution of a set of linear equations is an essential part of any circuit simulator. Generally, circuits are categorized into: linear and nonlinear circuits. In the linear circuit, all its circuit elements have a linear I-V relationship such as linear 183 resistor (V=RI). While in the nonlinear circuit, some of its elements have nonlinear I-V relationship such as CMOS transistors and charge-storage elements. It is well known in circuit simulations that the solution of linear circuits is conducted by LU decomposition technique such as Doolittle algorithm. The solution of nonlinear circuits is conducted by the iterative Newton-Raphson method. In this method, each iteration is solved by LU decomposition technique [102]. To solve a NEMS circuit, where its electrical circuit model has nonlinear elements, the iterative Newton-Raphson method is used in our circuit simulator. The Doolittle algorithm solves equation (78) efficiently by factorizing A into a product LU, where L is a lower triangular matrix and U an upper triangular matrix. The unknown X vector is then computed in two substitution steps: forward substitution, and backward substitution. These steps are performed in each iteration. 10.3.4. TRANSIENT ANALYSIS SOLUTION To evaluate NEMS circuits over a finite time interval [0, Tstop], a transient analysis has been implemented in our circuit simulator. The transient analysis is demonstrated in the flowchart that shown in Fig 10.4. In this analysis, the output is evaluated over a finite interval [0, Tstop] at every time step h. 184 Read Circuit: Topology and Element Values Specify initial Guess , k=0 Linearize Nonlinear Elements t=t+h Formulate The Linearized Circuit k=k+1 Equations Using MNA technique Solve by LU Decomposition (Doolittle algorithm) Find Next Iterate No Using Newton’s Check for Convergence method Yes Solution at time t No t=Tstop Yes Solution Fig 10.4: Transient analysis flowchart 185 10.4. CNEMS BASIC LOGIC GATES AND D-LATCH EVALUATIONS As it has been demonstrated, to evaluate accurately arbitrary circuit architecture, an accurate circuit simulation model for each element of the circuit architecture should be implemented in the circuit simulator. Accordingly, the constructed circuit simulator is capable of evaluating arbitrary circuit architecture that is designed by using the basic electrical elements that are shown in Table 16, In addition to the NEMS switch that is described in the previous chapter. In the following subsections, the evaluation for the basic CNEMS logic gates and D- latch are conducted by using the constructed circuit simulator. As will be shown, the simulation results demonstrate that the CNEMS switches, NNEMS and PNEMS, have the same functionality as CMOS transistors. Thus, CMOS design concepts and CAD tool can be used to expedite the design of CNEMS computation and sequential circuits. Furthermore, the simulation results validate the accuracy of circuit simulator in solving the derived NEMS circuit simulation model (Macromodel). This is demonstrated in terms of the used voltage (VDD) and the switching time. 10.4.1. CNEMS INVETER The description of CNEMS INVERTER in the Netlist formant is show in Fig 10.5 (a), and the evaluation of this INVERTER using the constructed circuit simulator is shown in Fig 10.5(b). The simulation result demonstrates that the CNEMS INVERTER‘s behavior is similar to CMOS INVERTER‘s behavior. 186 TITLE INVERTER V6 5 0 DC 1.3 V1A 1 0 PULSE (0.0 1.3 0.0NS 0.0NS 0.0NS 5NS 10NS ) N1 3 1 0 0 NNEMS N3 3 1 5 5 PNEMS C1 3 0 100F .TRAN 0.01NS 100.0NS .PRINT TRAN V(1) V(2) V(3) .END (a) (b) Fig 10.5: CNEMS INVERTER a) Netlist description and schematic b) Simulation result 10.4.2. CNEMS NAND GATE The circuit description design in the Netlist format for CNEMS NAND gate is shown in Fig 10.6(a), and the simulation results that have been gotten from evaluating this circuit using the constructed circuit simulator are demonstrated in Fig 10.6(b). These results verify that the functionality of CNEMS NAND gate is similar to the functionality of CMOS NAND gate. 187 TITLE NAND * V6 5 0 DC 1.300 VA1 1 0 PULSE (0.0 1.3 0.0NS 0.0NS 0.0NS 5NS 10NS ) VA2 2 0 PULSE (0.0 1.3 0.0NS 0.0NS 0.0NS 5NS 15NS ) * N1 3 1 5 5 PNEMS N2 3 2 5 5 PNEMS N3 3 1 4 4 NNEMS N4 4 2 0 0 NNEMS C1 3 0 100F * .TRAN 0.01NS 100NS .PRINT TRAN V(1) V(2) V(3) I(V6) I(VA1) I(VA2) .END (a) (b) Fig 10.6: CNEMS NAND Gate a) Netlist description and schematic b) Simulation results 10.4.3. CNEMS NOR GATE The circuit description design in the Netlist format for CNEMS NOR gate is shown in Fig 10.7(a), and the simulation results that have been gotten from evaluating this circuit using the constructed circuit simulator are demonstrated in 188 Fig 10.7(b). These results verify that the functionality of CNEMS NOR gate is similar to the functionality of CMOS NOR gate. TITLE NOR V6 5 0 DC 1.3 V1A 1 0 PULSE (0.0 1.3 0.0NS 0.0NS 0.0NS 5NS 10NS ) V1B 2 0 PULSE (0.0 1.3 0.0NS 0.0NS 0.0NS 5NS 15NS ) N1 3 1 0 0 NNEMS N2 3 2 0 0 NNEMS N3 3 1 4 4 PNEMS N4 4 2 5 5 PNEMS C1 3 0 100F .TRAN 0.01NS 100.0NS .PRINT TRAN V(1) V(2) V(3) .END (a) (b) Fig 10.7: CNEMS NOR Gate a) Netlist description and schematic b) Simulation results 189 10.4.4. CNEMS D-LATCH CNEMS D-latch is the basic building block for sequential circuits. The design description of the CNEMS D-latch in Netlist file is shown in Fig 10.8 (a), and the evaluation of this design using the constructed circuit simulator that has been demonstrated is shown in Fig 10.8(b). The simulation results as shown demonstrates that the CNEMS D-latch‘s behavior match the CMOS D-latch‘s behavior TITLE D-latch V6 5 0 DC 1.300 VA1 1 0 PULSE (0.0 1.3 0.0NS 0.0NS 0.0NS 17NS 29NS ) VA2 2 0 PULSE (0.0 1.3 0.0NS 0.0NS 0.0NS 5NS 15NS ) VA3 3 0 PULSE (1.30 0.0 0.0NS 0.0NS 0.0NS 5NS 15NS ) N1 4 1 5 5 PNEMS N2 6 3 4 4 PNEMS N3 8 6 5 5 PNEMS N4 9 8 5 5 PNEMS N5 11 2 9 9 PNEMS N6 7 1 0 0 NNEMS N7 6 2 7 7 NNEMS N8 8 6 0 0 NNEMS N9 10 8 0 0 NNEMS N10 11 3 9 9 NNEMS C1 11 0 100F .TRAN 0.01NS 100NS .PRINT TRAN V(1) V(2) V(3) V(8) V(11) .END (a) 190 (b) Fig 10.8: CNEMS D-latch a) Netlist description and schematic b) Simulation results 10.5. CNEMS 1-BIT FULL ADDER EVALUATION This section demonstrates the behavior of CNEMS 1-bit adder. As shown in Fig 10.9, the design of CNEMS 1-bit adder borrowed from CMOS 1-bit adder‘s design. This 1-bit adder has been simulated using the constructed circuit simulator. The simulation results are demonstrated in Fig 10.9. For instance, when V (1) is equal to 1.2V (logic ‗1‘), V (2) is equal to 1.2 V (logic‘1‘) V (3) is equal to 0 V (logic ‗0‘), in this manner, the carry is set to logic ‗1‘ after two switching time as shown below. This means that the logic ‗1‘ (VDD =1.2 V) passes to the carry output pin (V (5)) after the two PNEMS switches that are connected in series are closed. The sum output (V (10)) is available for the same inputs after three switching times as demonstrated below. The simulation results that are shown in Fig 10.9 demonstrate the capability of CNEMS technology in implementing computational circuits in the same manner like CMOS technology. Furthermore, these results validated the accuracy of the used circuit simulator in modeling the NEMS switch. In this 191 demonstration, the accuracy is shown in terms of the switching time and the operating voltage. TITLE 1 - bitAdder (a) V6 50 0 DC 1.3 V1A 1 0 PULSE (0.0 1.3 0.0NS 0.0NS 0.0NS 20NS 40NS ) V1B 2 0 PULSE (0.0 1.3 0.0NS 0.0NS 0.0NS 20NS 40NS ) V1C 3 0 PULSE (0.0 1.3 0.0NS 0.0NS 0.0NS 10NS 20NS ) N1 4 1 0 0 NNEM N2 4 2 0 0 NNEM N3 5 3 4 4 NNEM N4 7 1 0 0 NNEM N5 5 2 7 7 NNEM N6 9 1 0 0 NNEM N7 9 2 0 0 NNEM N8 9 3 0 0 NNEM N10 12 1 0 0 NNEM N11 13 2 12 12 NNEM N12 10 3 13 13 NNEM N9 10 5 9 9 NNEM N13 6 1 50 50 PNEM N14 6 2 50 50 PNEM N15 5 3 6 6 PNEM N16 8 1 50 50 PNEM N17 5 2 8 8 PNEM N18 11 1 50 50 PNEM N19 11 2 50 50 PNEM N20 11 3 50 50 PNEM N22 15 1 50 50 PNEM N23 14 2 15 15 PNEM N24 10 3 14 14 PNEM N21 10 5 11 11 PNEM C1 10 0 100F .TRAN 0.01NS 100NS .PRINT TRAN V (1) V (2) V (3) V (10) V (5) .END (a) (b) 192 (c) Fig 10.9: CNEMS 1-bit adder evaluation a) Netlist description b) Circuit evaluation c) Behavior 193 SUMMARY In this chapter, the circuit simulation program was demonstrated in terms of circuit simulation structure, circuit simulation techniques, and circuit transient analysis solution. Finally, the constructed circuit simulator was used in evaluating basic NEMS logic gates and NEMS d-latch. The simulation results demonstrate the accuracy of the constructed circuit simulator and the capability of CNEMS technology in implementing computational and sequential circuits. 194 CHAPTER 11 : CNEMS POWER SAVING AND CNEMS APPLICATIONS INTRODUCTION This chapter discusses the power dissipation in a NEMS circuit in terms of components, modeling, and advantages over Nanometer-CMOS technology. Furthermore, the capability of expediting the design of CNEMS combinational and sequential circuits using the existing CMOS CAD tool is demonstrated. Finally, the applications that will get significant benefits of using this switch when their computational, logical, and sequential circuits are implemented using CNEMS technology are discussed. 11.1. CNEMS POWER EVALUATION The consumed power in a NEMS switch consists of two components: switching power and leakage power. The switching power is the power that is consumed during the switching operation. The leakage power is the power that is dissipated as a result of leakage currents during the static and dynamic modes of a NEMS switch. The NEMS‘s switching power consists of switching electrical power and switching mechanical power. The switching power is modeled accurately in the constructed circuit simulator by considering the switching electrical power and the switching mechanical power. The switching electrical power is the power that is consumed in charging and discharging the capacitances between the switch‘s 195 electrodes. This power is considered by modeling the switching current that results from changing the voltage differences between the switch electrodes. The switching mechanical power is the power that is consumed in moving the mechanical parts of the switch‘s electrodes. This power is considered by modeling the switching current that results from changing the capacitances between the switch‘s electrodes. The leakage currents in a NEMS switch has two components: tunneling leakage current and surface leakage current. The leakage power is modeled accurately in the constructed circuit simulator by modeling the leakage currents components: tunneling leakage current and surface leakage current, as it has been demonstrated previously. Modeling accurately the NEMS switch‘s currents, switching and leakage currents, enables the circuit simulator to compute accurately the drawing current from each voltage source every time step. The circuit simulator computes the solutions for branches‘ currents and nodes‘ voltages at each time step during a circuit evaluation. Accordingly, the instantaneous drawing power from each voltage source can be computed by multiplying the drawing current from that voltage source by its corresponding value at that time. Consequently, the total consumed power in a circuit can be computed by the summation of instantaneous drawing power from all voltage sources in that circuit. 196 11.2. DIGITAL CNEMS CIRCUITS DESIGN To implement and evaluate digital computational and sequential circuits using CNEMS technology, the design of these circuits using CNEMS technology should be accomplished. As it has been demonstrated previously, basic CNEMS logic gates, sequential circuit, and computational circuit were designed using CMOS design concepts. These circuits demonstrated the same behaviors of the counterpart CMOS circuits. Accordingly, the design of complex CNEMS circuits can be expedite by using CMOS CAD tool. In this work, the design of CNEMS circuits has been accomplished by getting advantages of CMOS CAD tool. To generate a Netlist description for a digital CNEMS circuit, the procedure has been used. 1) Describe the behavioral of arbitrary digital circuit in Verilog or VHDL (hardware description language). 2) Use Leonardo synthesis tool to synthesize and optimize the circuit that is described in behavioral or structural level to gate level. After this step three files will be generated (file.v, file.vhl, file.sdf). 3) Convert the file.edf (gate level) into bench format using edif program. The generated file after this step will be in bench format ( .net) 4) Generate the Netlist file for a CNEMS circuit by using CNEMS cell library and the generated bench circuit file. 197 11.3. CNEMS POWER ADVANTAGES To demonstrate the power saving of using CNEMS technology over Nanometer- CMOS technology, the iscas85 and iscas89 benchmark circuits have been designed using both CNEMS technology and CMOS technology. The CNEMS‘s Netlist files for iscas85/iscas89 benchmark circuits have generated as it has been demonstrated. To evaluate CNEMS benchmark circuits, the constructed circuit simulator has been used. While the Nanometer-CMOS technology, 45 nm and 65 nm, has been evaluated using HSPICE and the 65nm model [103] for the 65nm CMOS benchmark circuits and the 45nm model [104] for the 45nm CMOS benchmark circuits. For both technologies, the consumed average power in each benchmark circuit during its two operating modes, active mode and standby mode, has been computed. The consumed power in the active mode consists of the switching power and the leakage power. While the consumed power in the standby mode is the leakage power. The average consumed power in Nanometer-CMOS and CNEMS iscas85/ iscas89 benchmark circuits are shown in Table 11.1and Table 11.2. Table 11.1 demonstrated the power saving of implementing iscas85 benchmark circuits using NEMS switch that has been described in the previous chapters over using 65 nm or 45 nm CMOS technology. Table 11.2 demonstrated the power saving of implementing iscas89 benchmark circuits using our NEMS switch over using 65 nm or 45 nm CMOS technology. 198 Table 11.1: iscas85 benchmark circuits power evaluations No# of CNEMS Technology Bulk CMOS Bulk CMOS Benchmark switch Technology Technology Circuit ( 65 nm ) ( 45 nm) Average Power Average Power Average Power standby Active standby Active standby Active ( ) 8bit-add 224 0.59 2.1 2.7 0.95 16bit-add 448 8.8 1.3 1.2 4.2 5.4 2.0 c17 24 0.031 0.079 C1355 2472 2.1 5.9 9.4 2.7 C1908 4154 2.9 16.0 C432 1120 16.0 1.0 2.7 C499 2344 6.4 2.0 1.6 Table 11.2: iscas89 benchmark circuits power evaluations Benchmark No# CNEMS Technology Bulk CMOS Bulk CMOS Technology Circuit of Technology ( 45 nm) switch ( 65 nm ) Average Power Average Power Average Power standby Active standby Active standby Active ( ) S27 146 1.2 0.21 0.19 0.63 0.89 0.30 S298 1208 2.9 1.5 1.3 5.3 6.1 2.5 S344 1208 6.7 4.5 1.4 3.5 6.4 1.6 S349 1216 5.0 2.7 1.4 3.5 6.4 1.7 S382 1508 8.6 1.9 1.7 8.1 7.6 3.8 S400 1550 8.9 1.2 1.7 8.5 7.8 4.0 199 The simulation results, in Table 11.1, show that the reduction of power in CNEMS iscas85 (combinational and computational circuits) over the counterpart bulk Nanometer-CMOS circuits is about three orders of magnitude, when these circuits are operating in the active mode. And it is about four orders of magnitude, when these circuits are operating in the standby mode. The results in Table 11.2 reveals that the power saving in implementing iscas89 benchmark circuits ( sequential circuits) in CNEMS technology over using bulk Nanometer-CMOS technology to implement these circuits is around three orders of magnitude, when these circuits are operating in the active mode. And it is around four order s of magnitude, when these circuits are operating in standby mode. 11.4. APPLICATIONS Despite the switching time for this switch is too long (1.4 ns), when it is compared to current CMOS technology, this switch with its attractive characteristics, forms a superior solution for implementing portable battery-powered system in embedded system computing that are limited by the battery-life, cooling system (power density), and ambient environments rather than the speed. Such these portable self-powered systems are: wireless sensors, medical applications, and space applications. It is important to point out that such these systems are mostly operated in the static mode (standby) mode. So, by using this switch in implementing these systems, the total energy that is consumed will be reduced significantly. And 200 consequently, the battery life is prolonged. Furthermore, in this switch, the leakage currents are not sensitive to ambient environment changes. SUMMARY This chapter discussed the NEMS switch power dissipation, explained how to expedite the design of CNEMS benchmark circuits by using CMOS CAD tool, and demonstrated the power advantages of CNEMS technology over Nanometer-CMOS technology. Finally, the applications that gain significant advantages of using CNEMS technology are discussed. 201 CHAPTER 12 : CONCLUSIONS AND SUMMARY OF CONTRIBUTIONS In this dissertation, the excessive quiescent power dissipation in Nanometer- CMOS technology was addressed by investigating a novel NEMS switch that demonstrated attractive switching characteristics in terms of low turn on voltage ~1.2 V, low switching time ~1.4 ns, footprint size, and virtually zero leakage current. These characteristics make this switch attractive switching technology to be used in implementing digital CMOS circuits, especially, portable digital embedded systems that are limited by the battery-life, cooling systems, and environment changes rather than the speed. Moreover, this switch can be fabricated easily by utilizing CMOS fabrication process and equipments. Accordingly, this switch can be integrated seamlessly with CMOS technology on the fabrication level and the operation level. In this work, to get benefit from the fabricated two-terminal NEMS switch, a four-terminal NEMS switch was designed by utilizing the design of the fabricated tuning fork NEMS switch (material and geometry) and using multi-physics simulation tool ( COMSOL multi-physics). And to get benefits from what have been done in CMOS technology in terms of design concepts and CAD tools, this NEMS switch was configured to N-channel and P-channel, in the form of Complementary- NEMS technology (CNEMS), similar to NMOS and PMOS correspondingly in CMOS technology. As it was demonstrated, the basic CNEMS logic gates and CNEMS D-latch were designed using CMOS design concepts, and they 202 demonstrated the same behaviors of the counterpart CMOS basic logic gates and D- latch. Thus, the design of CNEMS circuits, sequential; combinational; or computational, was expedited by using CMOS CAD tool. To evaluate accurately the NEMS switch in a circuit environment, an accurate circuit simulation model (device Macromodel) was derived and calibrated based on the 3D FEA physical device model. The 3D FEA physical device model was constructed using FEA multi-physics simulation tool. The 3D FEA physical device mode was able to capture the multi-physics phenomena in the NEMS switch and reproduce the fabricated device measurements. Consequently, the 3D FEA physical device model was used as a reference model to extract the device mechanical coefficients and calibrated the device Macromodel. Using the 3D FEA physical device model to extract the device mechanical coefficients is a new approach. This approach was able to produce the mechanical device coefficients more accurately than using the analytical equations that have been reported in literature. To make the derived circuit simulation model (Macromodel) capable of reproducing accurately the electro-mechanical device‘s characteristics in the static and the dynamic modes, the circuit simulation model was constructed of coupling two models: mechanical lumped model and electrical circuit model. The derived mechanical lumped model was able to produce accurately the mechanical characteristics of the NEMS switch with comparable measurements to the 3D FEA physical device model. And the derived electrical circuit model was able to reproduce accurately the electrical characteristics of the NEMS switch with comparable measurements to the 203 3D FEA physical device model. This circuit simulation mode enabled us to evaluate accurately the NEMS switch in terms of behavior, timing, and power dissipation; mechanical and electrical; with less memory and CPU requirements over the 3D FEA physical device model. To evaluate accurately an arbitrary digital CNEMS circuit, a circuit simulator that uses the derived circuit simulation model (Macromodel) was constructed. The constructed circuit simulation was built using the MNA technique and derived circuit simulation model. This circuit simulator is capable of evaluating accurately an arbitrary NEMS circuit by: 1) Solving the mechanical lumped model( 2nd DFE) for each NEMS switch instance at each time step, and consequently, modifying the electrical circuit model for each NEMS switch instance 2) Constructing system of equations 3) Solving the system of equations using the iterative Newton-Raphson. Using this circuit simulator we were able to evaluate accurately CNEMS sequential, combinational, and computational circuits in terms of behaviors, timing, and power dissipation. This circuit simulator is capable of evaluating the power dissipation (mechanical and electrical) of a CNEMS circuit when it is operating in active mode or in standby mode. Finally, to demonstrate the power saving of using CNEMS technology in implementing digital circuits over Nanometer-CMOS technology, iscas85 and iscas89 benchmark circuits have been designed using both technologies: CNEMS technology and Nanometer-CMOS technology. The generation of CNEMS Netlist files for these benchmark circuits was done by using CMOS CAD tool and using the 204 CNEMS cell library, as it was demonstrated. The evaluation of CNEMS benchmark circuits was done by providing the generated Netlist files for these benchmark circuits to the constructed circuit simulator. The constructed circuit simulator evaluated these circuits while they were operating in standby mode and in active mode. The CMOS benchmark circuits were evaluated using the Nanometer model (45 nm or 65 nm) and the HSPICE simulator. The Nanometer-CMOS benchmark circuits were also evaluated while they were working in the active mode and in the standby mode. The simulation results for iscas85 benchmark circuits demonstrated the power saving is about four orders of magnitude in the standby mode and is about three orders of magnitude in the active mode when these circuits are implemented using CNEMS technology over using (65 nm or 45 nm) Nanometer-CMOS technology. The simulation results for iscas89 benchmark circuits demonstrated the power saving is about four orders of magnitude in the standby mode and is about three orders of magnitude in the active mode when these circuits are implemented using CNEMS technology over using (65 nm or 45 nm) Nanometer-CMOS technology. The contribution of this dissertation can be summarized by: 1. Design a NEMS switch that has attractive switching characteristics and can be fabricated easily by using CMOS fabrication process and equipments. The design of this switch was done by utilizing the fabricated NEMS switch design (geometry and material) and using multi-physics simulation tool (COMSOL). This switch is capable of implementing digital circuits (combinational and sequential circuits) by 205 configuring this switch to N-channel and P-Channel. Accordingly, we can get benefits from what have been done in CMOS technology in terms of design concepts, CAD tools, and fabrication equipments. 2. Construct a 3D FEA physical device model for the NEMS switch using the COMSOL multi-physics simulation tool. This model was configured and solved using different solvers and algorithms to capture the multi-physics phenomena in this switch and reproduce the fabricated device measurements. This model was considered as a reference model to derive, calibrate, and validate a circuit simulation model for this switch. Furthermore. The 3D FEA physical device model enables us to measure some device‘s characteristics or phenomena that are cannot be measured easily from the fabricated device. 3. Derive an accurate circuit simulation model (device Macromodel) that is capable of modeling accurately the static and the dynamic electro-mechanical characteristics within average error is about 10% to the 3D physical device model. This model enables us to model accurately the consumed mechanical energy and electrical energy in this switch. This model was derived using new approach. In this, approach the physical device model was used as a reference model to extract the mechanical device coefficients and validate this model. 4. Construct a new circuit simulator that uses the derived circuit simulation. The constructed circuit simulator enables us to evaluate a NEMS circuit accurately in terms of behaviors, timing, and power dissipation. 206 5. Demonstrate the power saving of using this switch in implementing sequential and combinational circuits over using Nanometer-CMOS technology. The main conclusions that drawn from this dissertation can be summarized by: 1. To adapt a new switching technology to address the quiescent power dissipation in Nanometer-CMOS portable embedded systems that are limited by battery- life; cooling systems; and environment changes, this switching technology should have the following features: a) Has low turn on voltage that is comparable to Nanometer-CMOS technology to avoid the increasing of the dynamic power dissipation. b) Has reasonable switching time that meets the requirements for special applications that are limited by the energy/power consumption rather than the speed. c) Has footprint size in the nanometer regime to avoid unreasonable increasing in the circuit area. d) Has infinite ON current and virtually zero leakage current. e) Can be fabricated easily at the device level and the circuit level. f) Is preferable to be capable of getting benefits from what have been used in CMOS technology in terms of fabrication equipments and CAD tools. g) Is immutable to process and environment variations. 2.To evaluate a new switching technology, it is important to derive an accurate circuit simulation model. The derived model should be capable of reproducing the static and the dynamic behaviors of this device. In this work, a new approach was 207 followed to derive an accurate circuit simulation model based of the physical device model. This approach demonstrated accuracy in deriving the circuit simulation model over using other approaches that have been done in literature in terms of using analytical equations and simple parallel-plate model. 3.To evaluate accurately power dissipation, timing, and behaviors of a circuit architecture that is implemented using the new switching technology, a circuit simulator that uses and solves the derived circuit simulation model accurately is required. In this work, a circuit simulator that is capable of evaluating CNEMS circuits by providing their descriptions in the Netlist format was constructed. This is new software to be used in evaluating accurately NEMS circuits in terms of behaviors, timing, and power dissipation. In overall, despite the long switching time for the CNEMS technology ~1.4 ns when it is compared to current CMOS technology, This technology forms a superior technology to be used in implementing portable self-powered embedded systems that are limited by battery-life, cooling systems, and environment changes rather than the speed. Such these applications are medical applications, space applications, and network wireless sensors. Using this technology prolongs the battery-life as the result of reducing the consumed energy in the active and the static modes over Nanometer-CMOS technology. It is important to mention here that the NNEMS and PNEMS switches of CNEMS technology are identical in terms of design (geometry and material) and operating voltage and ON/OFF current. This means that there is 208 no need to worry about sizing these switches like CMOS circuits. Furthermore, the delay of this technology is limited by the mechanical movements not by the load capacitor like in CMOS technology. Moreover, these switches are switching based on the voltage difference between the Gate and the Body. 209 APPENDIX A: POWER METRIC VERSUS ENERGY METRIC This appendix introduces the power metric and the energy metric. Moreover, this appendix explains which metric is more suitable to be used in evaluating circuits‘ designs for circuits that have limitations in terms of cooling system (power density) or/and supply voltage, and for circuits that have limitations in term of battery-life. A.1 POWER METRIC This metric usually is expressed either in a peak-power form or an average power form. The average power is defined by the power that could be driven from the voltage source during a period of time. It is expressed in equation (A.1), where T is the time window. The peak-power is the maximum consumed power during a time window. (A.1) The power metric is a good metric to compare between different designs for power plug-in circuits, which they are limited either by the power density (cooling system) or the supply voltage. 210 A.2 ENERGY METRIC This metric could be defined either by the total active energy that the circuit consumes to accomplish its task/tasks as in equation (A.2), or by the total energy that the circuit consumes over a period of time when it is idle as in equation (A.3), where is the circuit delay to accomplish its task/tasks, and is the period of time when the circuit is idle. For battery powered portable systems, the energy metric is a good metric to estimate the battery life by the summation of the total active and standby energy as in equation (A.4). (A.2) (A.3) (A.4) For instance, reducing the operating frequency at the expense of degrading the performance reduces the average dynamic power. In spite of the achievements of lowering the power consumption as well as reducing the power density, the total dynamic energy that is required to accomplish the task/task will not be changed as shown in Fig.A.1. Moreover, for Nanometer-CMOS technology, the total active energy will be increased, where the circuit will be prone to leak currents for longer time. 211 Fig A.1: Power versus Energy [5] A.3 VLSI APPLICATIONS VLSI applications need different power and performance requirements. VLSI applications can be categorized into three types based on their requirements in terms of power and performance (speed) as shown in Fig.A.2. As shown in this figure, the applications such as medical, space, and specific network sensors require ultralow- power consumption and low speed. Furthermore, these applications are prone to environment changes. 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