Fabrication and Characterization of Gate Last Si Mosfets with Sige Source and Drain

Home , Gate oxide, Metal gate

EXAMENSARBETE INOM TEKNIKOMRÅDET ELEKTROTEKNIK OCH HUVUDOMRÅDET TEKNISK FYSIK, AVANCERAD NIVÅ, 30 HP STOCKHOLM, SVERIGE 2017

Fabrication and characterization of gate last Si MOSFETs with SiGe source and drain

BJÖRN CHRISTENSEN

KTH SKOLAN FÖR INFORMATIONS- OCH KOMMUNIKATIONSTEKNIK Abstract

The continuous evolution of digital technology we enjoy today is the result of ever shrinking, faster and cheaper transistors that make up the ubiquitous integrated circuits of our devices. Over the decades, the industry has gone from purely geometrical scaling to innovative solutions like high-k dielectrics combined with metal gates and FinFETs. A possible future is the use of high mobility materials such as Germanium for the active areas of a transistor instead of Silicon. As a step towards building devices on Ge, we characterize a gate last process with epitaxial deposition of Si0.75Ge0.25 source and drain areas on bulk Si wafers. Devices fabricated are proof-of-concept PMOSFETs and NMOSFETs with channel widths of 10 µm and 40 µm and channel lengths between 0.6 µm and 50 µm. The gate electrode of the fabricated devices is in- situ doped polycrystalline Silicon. The devices are electrically characterized through I-V measurements and exhibit a yield of 95%.

Keywords MOSFET fabrication, gate last, SiGe source and drain, IDP gate, epitaxy.

Abstract

Den konstanta utvecklingen av digital teknik som vi åtnjuter idag drivs av den ständiga utvecklingen av transistorer. Dessa blir mer kompakta, snabbare och kostar mindre för varje generation och bygger upp de integrerade kretsar som driver all vår vardagsteknik. Under ett tidsspann på flera decennier har krympningen gått från enbart geometrisk skalning till mer innovativa lösningar. Gate-oxiden har gått från rent kiseldioxid till material med lägre relativ permittivitet vilket möjliggjort en tunnare ekvivalent elektrisk tjocklek än vad som varit möjligt för kiseloxid. FinFet eller så kallade ’tri-gate’ transistorer har ersatt den plana varianten för att öka den ledande arean utan att enheterna sväller ut över substratet. En framtida möjlighet är även att använda material med högre mobilitet för elektroner och hål än kisel där en möjlig kandidat är Germanium. Som ett steg mot målet at bygga Germanium-transistorer tillverkar vi här gate last transistorer med source och drain i in-situ dopad kisel-germanium. Dessa konceptenheter används för att definiera och utveckla tillverkningsprocessen och tillverkas i flera omgångar. Varje skiva innehåller transistorer med en bredd på 40 µm och 10 µm. Kanallängden på transistorerna går mellan 0.6 µm och 50 µm för båda bredderna och av varje enhet finns 101 stycken per kiselskiva (100 mm diameter). Gate-elektroden består i samtliga fall av in-situ dopat poly-kristallint kisel. Enheterna karaktäriseras därefter genom elektriska mätningar och mätdata analyseras och sammanställs. Det visas genom dessa mätningar att ett utfall om över 95% fungerande enheter kan uppnås med processen.

Nyckelord MOSFET fabrication, gate last, SiGe source and drain, IDP gate, epitaxy.

Acknowledgements

I would like to extend my sincere and heartfelt thanks to Professor Mikael Östling for providing this research opportunity, Associate Professor Per-Erik Hellström for his supervision and Konstantinos Garidis for his invaluable guidance throughout the project.

I would also like to thank Associate Professor Gunnar Malm, Christian Ridder, Laura Zurauskaite, Ganesh Jayakumar, Mattias Ekström and Ahmad Abedin at ICT for stimulating discussions, problem solving and shared frustration over tool breakdowns.

Table of Contents

1 Introduction ...... 1 1.1 Historical scaling and some modern-day comparisons ...... 1 1.2 More than Moore ...... 3 1.3 Purpose ...... 3 1.4 Goal ...... 4 1.4.1 Why gate last? ...... 4 1.4.2 Why SiGe? ...... 5 1.4.3 Benefits ...... 5 1.5 Delimitations ...... 5 1.6 Outline ...... 6 2 Semiconductor and transistor theory ...... 7 2.1 Semiconductor theory ...... 7 2.2 MOSFET function ...... 8 2.3 Examples of MOSFET operation...... 8 2.3.1 OFF-state ...... 9 2.3.2 Depletion ...... 9 2.3.3 Inversion/ON-state ...... 10 2.3.4 Leakage ...... 10 2.4 MOSFET I-V characteristics ...... 11 2.4.1 Threshold voltage, Vt...... 11 2.4.1.1 Calculation of threshold voltage ...... 12 2.4.2 ON-current ...... 12 2.4.2.1 Linear region Vd < Vg - Vtm...... 12 2.4.2.2 Parabolic region Vd > Vg - Vtm ...... 13 2.4.2.3 Subthreshold behavior ...... 13 2.4.3 OFF-current ...... 13 2.4.4 DIBL ...... 13 3 Methods for semiconductor fabrication and characterization ...... 14 3.1 Lithography ...... 14 3.1.1 Resist ...... 14 3.1.2 Exposure ...... 14 3.1.3 Development ...... 15 3.1.4 Bake ...... 15 3.2 CVD ...... 15 3.2.1 Plasma enhanced chemical vapor deposition (PECVD) ...... 16 3.2.2 Atomic layer deposition (ALD) ...... 17 3.3 Epitaxy ...... 17 3.3.1 Homoepitaxy ...... 17 3.3.2 Heteroepitaxy ...... 17 3.3.3 Vapor phase epitaxy (VPE) ...... 18 3.3.4 Selectivity ...... 18 3.4 Physical vapor deposition (PVD) ...... 19 3.5 Dry etching ...... 20 3.6 Wet etching...... 20 3.7 Thermal oxidation ...... 21 3.8 Silicide ...... 21 3.9 Gate stack ...... 22

3.9.1 Gate electrode ...... 22 3.9.2 Dielectrics ...... 22 3.10 Annealing ...... 22 3.10.1 Forming gas anneal (FGA) ...... 23 3.11 Measurements of transistor characteristics ...... 23 3.11.1 I-V measurements ...... 23 3.11.2 Yield ...... 23 3.12 Theoretical calculations for comparison with real devices ...... 23 3.13 Simulation of MOSFETs ...... 24 3.13.1 COMSOL Multiphysics ...... 24 3.14 SEM ...... 24 4 Fabrication of gate last MOSFETs ...... 26 4.1 Mask set ...... 26 4.2 Device layout...... 26 4.3 Process flow ...... 28 4.4 Batch 1 – Trial wafer, PMOSFETs with n-doped IDP gate ...... 34 4.4.1 Batch 1 processing specifics...... 34 4.5 Batch 2 – PMOSFETs with n-doped IDP gate ...... 34 4.5.1 Batch 2 processing specifics...... 34 4.6 Batch 3 – NMOSFETs with n-doped IDP gate ...... 34 4.6.1 Batch 3 processing specifics...... 34 4.7 Batch 4 – PMOSFETs with p-doped IDP gate ...... 35 4.7.1 Batch 4 processing specifics...... 35 5 Results and discussion ...... 36 5.1 Device definitions ...... 36 5.2 Batch 1 characterization and analysis - PMOSFETs ...... 36 5.2.1 Batch 1 calculation of values ...... 37 5.2.1.1 Calculation of Vt ...... 37 5.2.1.2 Extraction of Ion ...... 37 5.2.1.3 Extraction of Ioff ...... 37 5.2.1.4 Calculation of DIBL...... 37 5.2.1.5 Calculating SS ...... 38 5.2.1.6 Average gate and bulk currents ...... 37 5.2.1.7 Yield ...... 38 5.2.1.8 Extraction of Rsd ...... 38 5.2.2 Batch 1 post-fabrication changes ...... 40 5.3 Batch 2 characterization and analysis - PMOSFETs ...... 40 5.3.1 80 nm dummy gate height (80DG) ...... 40 5.3.2 160 nm dummy gate height (160DG) ...... 41 5.3.3 Batch 2 calculation of values ...... 42 5.3.4 Low yield for 160DG...... 43 5.3.5 Spread of values...... 43 5.3.6 Batch 2 in-process analysis ...... 43 5.3.7 Batch 2 post-fabrication changes ...... 46 5.4 Batch 3 characterization and analysis - NMOSFETs ...... 46 5.5 Batch 4 characterization and analysis - PMOSFETs ...... 47 5.6 Troubleshooting Batch 3 and 4...... 48 5.7 Theoretical calculations and simulations ...... 51 5.7.1 Theoretical calculations ...... 51 5.7.1.1 Current model and limitations ...... 52

5.7.2 Simulations ...... 53 5.7.2.1 Limitations in the simulation...... 53 6 Conclusions and future venues...... 55 References ...... 56

1 Introduction

The usefulness of MOSFETs for computational tasks has transformed the world as we perceive it over the short span of just a few decades. As computing power has grown exponentially and prices have dropped, technological advances and usage scenarios have opened up that could not be have been conceived at the beginning of the millennium. Mobile System on Chips (SoC) being released in 2017 have ~3 Billion transistors on the 10 nm manufacturing node [1] (Qualcomm, SD835) which is ten times the amount of transistors compared to Intel’s game changing Core 2 Duo Conroe processors from 2006. Even considering that the SD835 contains several other functions such as graphics processing (GPU), dedicated digital signal processing (DSP), etc. the difference in magnitude is fascinating. All of this is based on the continued downward scaling in size of the individual transistors which allows for lower power consumption, improved device density and better utilization of raw materials. As scaling of the transistor continues downward, new challenges are faced. From quantum-mechanical physical barriers (direct tunneling from gate to channel or even from source to drain) prompting for new materials and gate stack designs to problems with decreased device performance as surface scattering of carriers increases for thin channels to regular short channel effects.

1.1 Historical scaling and some modern-day comparisons Gordon Moore at Fairchild, Inc. initially formulated the statement in 1965 that the number of devices per integrated circuit (IC) doubled every 12 months and would continue doing so for the coming 10 years [2]. He went on to help co- found Intel in 1968 and in 1975 he revised the time span of his prognosis to every two years instead [3]. A depiction of the trend over time can be seen in Figure 1 for select IC devices. Moore’s Law speaks of the transistor density in produced IC’s and says nothing about the performance of the devices. What is often quoted in popular scientific publications is a statement made by David House, Intel executive in the 1970’s. House took the increased speed of transistors into account, combined it with Moore’s statement of increased density and predicted that the performance of chips would double every 18 months [4]. Moore’s law has been pronounced dead or dying several times, for example in [5] but in 2017, high-level Intel executives still proclaim it to be alive and well [6]. In the author’s opinion, the most interesting aspect of Moore’s law is that it has become a self-fulfilling prophecy. The past trends of the semiconductor industry are used to define the ITRS roadmap [7] which then governs the pace at which technology nodes are reached. To remain competitive, individual companies need to push as hard as possible to follow the roadmap.

Figure 1. Visualization of Moore's Law, historical and current. Image reproduced from [8] without alterations under Creative Commons (CC-BY-SA) license.

Concerning the technology node, the description has historically corresponded to the half pitch of the shortest distance between the metal 1 (M1) lines of the integrated circuit (IC). When the scaling was purely geometrical, the step from one node to another involved linearly scaling features by 0.7. As this required new mask sets, some manufacturers introduced what was called ‘half-node’ steps where the shrinkage was instead 0.9 and achieved through reduction optics using the same mask set. This was done to present clients with an economical alternative that provided some of the benefits of shrinking while not corresponding to an ITRS-defined node. With the introduction of the 90 nm technology node pure geometrical scaling was no longer possible [9]. Subsequent technology nodes have therefore been decoupled from the actual dimensions of the device. This has led to different manufacturers adopting their own definitions of what actually constitutes a new node [10]. There is also a rather unfortunate complimentary law called Rock’s Law (or Moore’s Second Law) [11] stating that the cost of building semiconductor fabrication plants to follow the scaling will double every four years. In 2016, the approximated cost for building a new factory to produce the leading edge of logic ICs was estimated to be $8-$10 Billion, per the Gartner report Market Trends: Rising Costs of Production Limit Availability of Leading-Edge Fabs. This cost is expected to rise to between $15-$20 Billion by 2020 [12].

According to the Semiconductor Industry Association (SIA), the average growth of the semiconductors industry revenue was slightly less than 20% in 2017 [13] 2

which is on the high side of the average for the last decades. This makes it quite clear that with the current level of scaling costs, at some point in the near future building new factories will not be a sound investment. The construction costs will not be returned over the lifespan of a technology node. One cannot help but wonder, if the final nail in the coffin for Moore’s Law will not be pure economics. For consumers, the increasing cost of manufacturing has the unfortunate effect that there are fewer individual manufacturers. With the consolidation of factories comes a larger risk of isolated incidents causing delays in production as well as a larger risk of market manipulation and artificially raised prices in the long term.

1.2 More than Moore The backbone of the semiconductor industry is Si. It is cheap and abundant, mechanically stable and resilient. It also forms a very good native oxide with excellent mechanical and insulating properties. A challenge for research on new materials is that the industry is constantly developing Si, trying to get the most out of its faithful servant. For example, Si has a much lower bulk hole mobility than electron mobility. Traditionally, this would mean that PFMOSFETs would take up about five times the area of the corresponding NMOSFETs. An attractive alternative would then be to replace Si with a material with more symmetrical mobilities such as Ge. For CMOS design, the ratio of mobilities/currents/transistor size need not be 1:1 but instead depends upon the final circuit designers wish whether to prioritize rise or fall time in the logic gate. However, larger gates introduce a higher capacitance and slow down the operations of the device [14]. Therefore, it is desirable to not have a too large a discrepancy between PMOSFETs and NMOSFETs physical sizes to start with. Historically, the P:N ratio has been between 5:1 to 2:1 depending on technology node as hole and electron mobility are differently affected by shrinking designs. With the introduction of the 90 nm node and strained layers [15] the hole mobility was increased more than the electron mobility due to the design, somewhat mitigating the discrepancy between transistor sizes. With the advent of the 45 nm node, high-K metal gates were introduced to mitigate tunneling through the gate oxide [16]. For newer nodes when FinFETs have been employed, many manufacturers choose not to publish their data. Another attractive reason for materials with higher mobility than Si is that additional scaling causes more surface scattering in the channel, reducing the effective mobility of the device. In other words, the extra headroom could be used to mitigate detrimental effects of scaling.

1.3 Purpose The purpose of this report is to collect the work and results of a 21-week Master Degree project at the Department of Integrated Circuits, ICT, Royal Institute of Technology (KTH). The project is the culmination of a five-year program at KTH that started with an electrical engineering Bachelor’s Program and continued with studies in Nanotechnology for a two-year Master’s Program.

1.4 Goal The objective of this thesis project was to manufacture and characterize planar PMOSFETs and NMOSFETs using a gate last manufacturing process. The process was to be optimized for in-house work with epitaxially grown SiGe source and drain areas on a Si substrate.

1.4.1 Why gate last? The two main methods of MOSFET fabrication are gate first and gate last. Gate first uses the deposited gate stack and field oxide as a hard mask for ion implantation of source and drain and is therefore self-aligned as shown in Figure 2. This requires ion implantation techniques with high uniformity of the doping profile and efficient electrical activation of the dopants. For Ge, particularly the latter has proven to be a challenge [17], [18] and performing the doping in-situ during epitaxial growth of the SiGe has shown promise of higher activation [19].

Figure 2. Example of source and drain definition through ion implantation for a PMOSFET. The field oxide (FOX) defining the active area and gate stack are used as a hard mask.

Gate last processes can either be self-aligned or not self-aligned. A simplified schematic of the first case is shown in Figure 3. The process starts with the deposition of the S-D material, the field oxide is then deposited on top. A trench is etched trough both S-D material and FOX down to the substrate. Optionally, the substrate can be protected from etch damage with the help of an etch stop layer. The next step involves the growth or deposition of the gate oxide as well as spacers on the side walls. The final step involves the deposition, definition and etching of the gate electrode material. Variations of this process are widely used for fabrication of FinFETs usually with poly-crystalline source and drain areas as presented in [20]. Not self-aligned gate last manufacturing is used throughout this thesis and the process flow will be covered in detail in 4.3 but is described briefly here. In the not self-aligned gate last process (hereafter referenced as gate last), the active S-D areas are patterned and separated by a dummy gate which is then 4

removed. The real gate is deposited and patterned with photolithography. This means that epitaxially grown S-D areas can be used. The available mask set made self-aligned gate last unpractical. Also, at the facility where this work was conducted ion implantation could not be carried out. The sample would have to be sent elsewhere which introduces further complexity to the process and increases turnaround time. With the chosen process, faster prototyping of devices could be performed in house and improvements to fabrication steps could more readily be made.

Figure 3. Self-aligned gate last process. To get the desired overlap of the gate over the S-D, a wet etch step could be added before gate oxide deposition to widen the trench above the S-D layer.

1.4.2 Why SiGe? As a future goal is to fabricate transistors with active areas consisting of Ge (due to its increased mobility over Si), a process flow readily ported to Ge substrates is desirable. SiGe can be grown through selective epitaxy on Si if the Ge content is low enough and on Ge if the roles are reversed with a minimal amount of strain. While Ge MOSFETs have already been manufactured by several people before, such as reported in e.g. [21] and [22], the aim is to have a process flow that can be carried out in the Electrum Laboratory, KTH.

1.4.3 Benefits Conclusions and data from the thesis can be applied to further research at the Department of Integrated Circuits, ICT, KTH as part of a larger umbrella project on use of Germanium (Ge 3D project) [23].

1.5 Delimitations The devices manufactured during this thesis were based on existing shared lithography masks made available by the department. As such, no design modifications could be made to the mask. The devices were fabricated on single 100 mm Si wafers with space for 101 working dies. No encapsulation of the devices was made and devices were probed individually. Wafers were either PMOSFET or NMOSFET, no CMOS could be manufactured using the available masks. 5

1.6 Outline Chapter 2 contains a summary of semiconductor device theory from the field of work in this thesis. Chapter 3 looks at the fabrication and characterization methods used for the devices from a theoretical and schematic standpoint. Chapter 4 presents the process flow for device fabrication during the project and specifics for the different batches. Chapter 5 collects the characterization results and discussions about the results. Chapter 6 summarizes the contents of the project and presents the author’s ideas on future directions. Appendix A contains a list of all the specific tools/machines used during the project.

2 Semiconductor and transistor theory

Semiconductor theory with a focus on junctions as well as MOSFET and gate stack specifics is presented in this section.

2.1 Semiconductor theory The ability to change the properties of a material from conducting to non- conducting and vice versa is what enables the construction of transistors, essentially controllable switches at the micro- and nano-level. When a material is doped by introducing impurities with a different valency than the bulk material, it changes the position of the Fermi level in the bandgap [24]. For N- type materials, the shift is toward the conduction band while for P-type the shift is toward the valence band. As materials with different doping are put or grown together a P-N junction is formed. The Fermi levels of the two materials must line up at the junction.

Figure 4. Band diagram for a PN-junction. Charges can move in the indicated direction but are stopped from moving in the opposite by the resulting potential barrier within the dashed lines.

The valence and conduction bands must then bend to avoid non-physical discontinuities, giving the smooth transition shown schematically in the junction area of Figure 4. The effect is that a barrier against the carriers is formed in one direction and the resulting diode allows current transport in one direction only. When a positive voltage is applied to the p-type material, current is conducted and the diode is then forward biased. If the polarity is changed, the device is reverse biased and does not conduct any current. However, if a large enough reverse bias is applied, the device goes into breakdown and starts conducting uncontrollably in the reverse direction. If the current is not controlled externally, the device can be destroyed due to uncontrolled heat generation. Even for very high potential barriers, if a large enough bias is applied, there can be tunneling breakdown, Figure 5, as electrons from the valence band on one side of the junction are excited to the conduction band on the other side [24]. 7

Figure 5. Tunneling from valence to conduction band through potential barrier.

The formation of this barrier leads to an area depleted of charges (holes and electrons for a symmetrical barrier) called the depletion layer. The difference in energy levels for different materials is called the built-in potential, there is an internal electrical field generated by the different charge concentrations in the two materials that causes the band bending. If the physical layout of the depletion layer is examined, it can be determined that for a highly asymmetrical doping concentration in the P- and N-type materials the depletion layer is formed almost exclusively inside the lower doped material [24]. In this regard, the highly-doped side can be considered a metal (which does not have a depletion layer) and its part of the depletion layer can be neglected. When it comes to transistors, the width of the depletion layer is of great importance and can be calculated from the built-in potential, doping concentrations and the dielectric constant of the semiconductor material, using equations shown in section 2.4.

2.2 MOSFET function The metal-oxide-semiconductor field effect transistor (MOSFET), Figure 6, is the most widely used semiconductor structure today. It uses the ability of a MOS capacitor [24] to invert the charge of a channel in a lowly doped substrate (body) to allow for conduction between a highly-doped source and drain terminal of the same type as the inverted channel.

2.3 Examples of MOSFET operation The variation of the gate voltage is used to switch the transistor between ON and OFF states. The ability to switch the transistor on and off at a very high frequency (GHz range) allows for the use of digital design methods based on Boolean algebra to construct logic gates that can, in turn, be used for extremely complex integrated circuits [25].

Figure 6. Schematic of a MOSFET showing the different regions.

2.3.1 OFF-state Gate bias is set to 0 V and the drain bias is set by the supply voltage. In an ideal device, no current is transported from source to drain due to lack of carriers, Figure 7. A small leakage current is always present in a real device.

Figure 7. NMOSFET in OFF-state. No bias on gate gives equilibrium in the channel region and a carrier concentration defined by the substrate doping. The gate is electrically insulated from source, drain and bulk by a gate oxide.

2.3.2 Depletion A bias is placed on the gate electrode which depletes the area under the gate oxide (channel) of the charges present in the lowly doped substrate as shown in Figure 8.

Figure 8. NMOSFET in depletion, bulk charges are removed from the channel region.

2.3.3 Inversion/ON-state As the gate voltage passes the threshold voltage, the charge type of the channel is inverted and the carrier concentration of the same type as the source and drain increases. As a bias is put over the S-D terminals, current is transported through the channel, Figure 9. As gate bias is returned to 0 V the device stops conducting, returning to the OFF-state.

Figure 9. NMOSFET in ON-state, when the source and drain are biased differently, current is transported through the charge-inverted channel.

2.3.4 Leakage There are several sources of leakage in a MOSFET, all undesirable as the leakage currents cause an Ohmic power loss as electrical energy is converted to thermal energy and then dissipates. The dissipated power does not contribute to the function of the circuit and thus decreases its computational efficiency. If the gate oxide is not insulating enough, there can be a leakage from the gate either into the source or drain through the channel or into the substrate below. If the source and drain are not properly separated, direct leakage between them can take place which can completely ruin the functionality of the device. This effectively removes the ability to turn the device off. Even for a zero gate bias the device will conduct. There can also be leakage between S-D and the substrate (body), if there is a large amount of threading dislocation defects that facilitate current transport along the boundaries of the resulting regions.

If the contact between the power supply and the electrodes is not electrically sound, the increased resistance of these junctions will cause a voltage drop that results in additional thermal power loss. Additionally, it will affect the external voltage needed to operate the system properly. The aim should always be to minimize these parasitic resistances. One method of decreasing the contact resistance is to form a silicide (Ni-silicide is a common type) at the contact areas which will provide a better electrical interface (metal-silicide-semiconductor) than available for metal-semiconductor alone. A model can be made of the transistor where the different circuit elements are replaced with resistances as shown in Figure 10.

Figure 10. Schematic of a MOSFET as source and drain resistances separated by an ideal switch (left) and showing the source resistance specifically (right). Image from [24].

2.4 MOSFET I-V characteristics The most important features of the transistor are how well the gate control works and how the S-D current scales for different bias across the S-D terminals. If the current characteristics are examined, there are three main concepts to grasp. The subthreshold behavior shows how the device behaves for bias lower than the threshold voltage. Above threshold and for a low drain bias the behavior is called the linear region. For a high drain bias this is called the parabolic region as the device goes into saturation. When the behavior for the different regions have been calculated, measured or simulated there are number of defining characteristics that can be extracted to judge the function of the device.

2.4.1 Threshold voltage, Vt Threshold voltage is the gate voltage at which the device turns on increasing the current exponentially. It can be calculated with the following equations from [24]. 2 | | = + 𝑑𝑑 𝑠𝑠 𝑠𝑠𝑠𝑠 𝑡𝑡 𝑓𝑓𝑓𝑓 𝑠𝑠𝑠𝑠 � 𝑞𝑞𝑁𝑁 𝜀𝜀 𝜑𝜑 𝑉𝑉 𝑉𝑉 𝜑𝜑 − 𝑜𝑜𝑜𝑜 = 2 𝐶𝐶

𝜑𝜑𝑠𝑠𝑠𝑠 − 𝜑𝜑𝑏𝑏 11

= ln 𝐵𝐵 𝑑𝑑 𝑏𝑏 𝑘𝑘 𝑇𝑇 𝑁𝑁 𝜑𝜑 � 𝑖𝑖 � : Flat band voltage. This depends of 𝑞𝑞the difference𝑛𝑛 in work function/electron. affinity between the gate electrode and the channel. 𝑓𝑓𝑓𝑓 𝑉𝑉 : Dielectric constant of the substrate. For Si 11.9 = 11.9 * 8.85 * 10-14 F/cm. 2 : Oxide capacitance per unit area = /Tox [F/cm ]. 𝑠𝑠 0 𝜀𝜀 : Donor dopant level in the channel. 𝜀𝜀 𝑜𝑜𝑜𝑜 𝑜𝑜𝑜𝑜 𝐶𝐶 : Intrinsic dopant level in Si, given as𝜀𝜀 ~1010 cm-3 in literature. 𝑁𝑁𝑑𝑑 2.4.1.1𝑛𝑛𝑖𝑖 Calculation of threshold voltage Vt can be extracted by sweeping the gate bias from low to high (negative and positive respectively) while keeping the Vd bias low (0.1 or 0.05 V commonly used). From the resulting linear curve, the maximum slope can be found and an extrapolated line can be drawn from this slope. When the line results in Id = 0 A, the corresponding Vg is the threshold voltage. Numerically, this can be done by approximating the derivative of measurement data to find the maximum slope and then using the slope to extrapolate a straight line.

2.4.2 ON-current The ON-current is the maximum current conducted through the S-D at the high S-D bias and operating gate bias. As the transistor has a capacitance storing energy when it is turned on and for a short time after turning off, the ON- current affects how quickly the transistor can charge and discharge said capacitance and thus how fast it can operate. Typical values are around 10-5 – 10-4 A. For theoretical calculations, the ON-state is divided into three regions. ON-current can be directly extracted as the maximum current of the device.

2.4.2.1 Linear region | | < �𝑉𝑉𝑔𝑔 − 𝑉𝑉𝑡𝑡�

𝑉𝑉𝑑𝑑 𝑚𝑚 = ( ) 2 𝑊𝑊 𝑚𝑚 𝐼𝐼𝑑𝑑 − 𝐶𝐶𝑜𝑜𝑜𝑜𝑜𝑜 𝜇𝜇𝑝𝑝𝑝𝑝 𝑉𝑉𝑔𝑔 − 𝑉𝑉𝑡𝑡 − 𝑉𝑉𝑑𝑑 𝑉𝑉𝑑𝑑 𝐿𝐿 3 = 1 + 𝑇𝑇𝑜𝑜𝑜𝑜𝑜𝑜 𝑚𝑚 𝑊𝑊𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 2 2 = 𝜀𝜀𝑠𝑠 𝜑𝜑𝑏𝑏 𝑊𝑊𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 � 𝑞𝑞𝑁𝑁𝑑𝑑 : Oxide equivalent capacitance. Takes into account the effects of the maximum accumulation layer thickness in the channel and the gate depletion region𝐶𝐶𝑜𝑜𝑜𝑜𝑜𝑜 thickness. From literature assumed to have a combined effect of about 3 nm which is added to to form [24]. : The bulk-charge factor. 𝑇𝑇𝑜𝑜𝑜𝑜 𝑇𝑇𝑜𝑜𝑜𝑜𝑜𝑜 𝑚𝑚 12

: Effective hole mobility or hole surface mobility in the channel. Affected negatively by an increased gate voltage. The mobility is material specific and is 𝑝𝑝𝑝𝑝 usual𝜇𝜇 ly taken from empirical studies.

2.4.2.2 Parabolic region | | > �𝑉𝑉𝑔𝑔 − 𝑉𝑉𝑡𝑡� The device will go into saturation for high drain bias and higher gate voltages 𝑉𝑉𝑑𝑑 𝑚𝑚 [24]. For this, the saturation current can be calculated from:

= ( ) , 2 𝑊𝑊 2 𝐼𝐼𝑑𝑑 𝑠𝑠𝑠𝑠𝑠𝑠 − 𝐶𝐶𝑜𝑜𝑜𝑜𝑜𝑜 𝜇𝜇𝑝𝑝𝑝𝑝 𝑉𝑉𝑔𝑔 − 𝑉𝑉𝑡𝑡 2.4.2.3 Subthreshold behavior 𝑚𝑚𝑚𝑚 Subthreshold slope (SS) is a measure of the speed with which the device can react and ramp up the voltage when the input is changed. It is measured as the inverse of the slope of the linear region of the I-V plot when plotted with a semi logarithmic (base 10) scale for the current and presented in units of mV/decade. Typical values are around 60-100 mV/decade. The subthreshold slope and current can be calculated with the following equations [24]. The value can be extracted from data by numerically determining the slope.

= 2.3 𝑚𝑚𝑘𝑘𝐵𝐵𝑇𝑇 𝑆𝑆𝑆𝑆 [ 𝑞𝑞 ] = ( ) [ ] ∆𝑉𝑉𝑔𝑔 𝑚𝑚𝑚𝑚 𝑆𝑆𝑆𝑆 ∆𝑙𝑙𝑙𝑙𝑙𝑙10 𝐼𝐼𝑑𝑑 𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 = ( 1) 1 , 2 𝑞𝑞�𝑉𝑉𝑡𝑡−𝑉𝑉𝑔𝑔� 𝑞𝑞𝑉𝑉𝑑𝑑 𝑊𝑊 𝑘𝑘𝐵𝐵𝑇𝑇 𝑚𝑚𝑘𝑘𝐵𝐵𝑇𝑇 𝑘𝑘𝐵𝐵𝑇𝑇 𝐼𝐼𝑑𝑑 𝑠𝑠𝑠𝑠𝑠𝑠 − 𝐶𝐶𝑜𝑜𝑜𝑜𝑜𝑜 𝜇𝜇𝑝𝑝𝑝𝑝 𝑚𝑚 − � � 𝑒𝑒 � − 𝑒𝑒 � 2.4.3 OFF-current 𝐿𝐿 𝑞𝑞 When the gate bias is set to zero and there is only a small standby bias over the S-D, the transistor is off. In a real device there is a small current conducted between S-D even when the device is off. This belongs to the leakage currents and should be kept as low as possible for thermal and power consumption reasons. The OFF-current can be read from the graph by taking the current value for low S-D bias at zero gate voltage. Typical values should be around 10- 10 A.

2.4.4 DIBL Drain induced barrier lowering (DIBL) is a measure of how much the drain bias affects the threshold voltage of the device and is a short-channel effect. The DIBL is the difference along the gate voltage axis between low and high drain bias curves, resented in units of mV/V. For numerical processing, the DIBL of a device can be calculated from [24]:

, , = , , 𝑉𝑉𝑡𝑡 ℎ𝑖𝑖𝑖𝑖ℎ 𝑉𝑉𝑉𝑉 − 𝑉𝑉𝑡𝑡 𝑙𝑙𝑙𝑙𝑙𝑙 𝑉𝑉𝑉𝑉 𝐷𝐷𝐷𝐷𝐷𝐷 𝐷𝐷 𝑉𝑉𝑑𝑑 ℎ𝑖𝑖𝑖𝑖ℎ − 𝑉𝑉𝑑𝑑 𝑙𝑙𝑙𝑙𝑙𝑙 13

3 Methods for semiconductor fabrication and characterization

Several common semiconductor fabrication methods were used over the scope of the thesis which are presented in this section of the report.

3.1 Lithography Photolithography (referred to as ‘lithography’) is one of the most central concepts of very large scale integration (VLSI) processes due to its semi-parallel nature. Instead of manipulating a single feature at a time (like in E-beam lithography [26]) it allows the definition of a single layer of one die, containing billions of features in one step. It is not a fully parallel process as a wafer with multiple dies will need one exposure for each die. As wafer sizes increase and the number of dies on a wafer increases the processing time per wafer becomes longer. This can be offset by reduced handling time as fewer wafers are needed for the same number of devices. The general process flow consists of:

1. Coating the wafer with photoresist. 2. Exposing the resist in a pattern defined by the mask set. 3. Developing the resist to remove unwanted remnants. This creates a soft mask layer with the outlay of the mask set. 4. (Optional) Post development bake of the wafer to increase the durability of remaining resist. After these steps are performed, other processing steps such as deposition or etching of material can be performed using remaining resist to control the patterning of the process as a soft mask.

3.1.1 Resist The resist is a polymer which reacts mainly with exposure to light of different wavelengths. Most commonly UV light is used for its short wavelength and as the industry moves towards ever smaller feature sizes, it is expected to go into Deep UV [27]. Depositing the resist is done via spin-coating where a puddle is dispensed in the middle of the rotating wafer. The rotational speed of the wafer determines the final thickness of the resist with 1 being common. Uniform coverage and thickness is important. Often, a pre-deposition technique called HMDS (Hexamethyldisilazane) [28] is utilized which𝜇𝜇𝜇𝜇 improves the adhesion of the resist to the surface of the wafer. The type of resist can be either positive or negative. Negative resist hardens when exposed to light of its corresponding wavelength whereas positive resist becomes more soluble when exposed. Positive resist is mostly used in the industry today and is also what is used throughout this thesis.

3.1.2 Exposure The exposure is done by focusing light of a specific wavelength through a lens column, through the mask set which blocks out select areas. After more correcting optics, the light hits the resist-coated wafer as shown schematically in Figure 11. 14

Figure 11. Schematic of a simplified lens column in a stepper. Image from [29]

To expose multiple dies the stage holding the wafer is moved. This construction is called the “stepper” and allows the highly sensitive lens column to remain fixed while multiple areas on the wafer are exposed. Depending on the size of the features to be patterned and the topography and material of the substrate beneath the resist, the dose and mask have to be adapted to account for interference and reflections that cause unwanted areas to be exposed [29].

3.1.3 Development After exposure, the wafer is put into a developing agent that dissolves the more soluble resist. The development time is very important for the final result. Underdeveloped wafers will have resist left that should have been removed. Overdeveloped wafers, on the other hand, might have fine-structures erroneously removed.

3.1.4 Bake When the resist structure (soft mask) is defined, the wafer is baked in an oven to make it more durable against mechanical damage but also to keep a more well-defined structure during subsequent process steps that might have destructive qualities. Time and temperature of the bake depends on resist type but 30 minutes at about 110 ° is common.

3.2 CVD 𝐶𝐶 Chemical vapor deposition (CVD) is a means for depositing material uniformly on a target. This is done through the use of precursors that react on the sample surface to cause growth. There are multiple different constellations of chambers and pressures used.

Figure 12. Schematic of CVD chamber and process

The reaction chamber is pumped down to low pressure to evacuate contaminated air. The correct temperature for the specific growth is set and the inert carrier gas and precursor with the desired concentration is pumped into the chamber and the reaction ensues as shown in Figure 12.

1. The precursors diffuse from the main flow of gas through the boundary layer covering the target. 2. Precursors adsorb on the surface of the target. 3. Chemical reaction fueled by thermal energy takes place and the desired compound is formed on the surface of the target. 4. Residual byproducts out-diffuse from the target and are carried out by the main gas flow.

The reaction chamber can be hot-walled where the entire chamber is heated or cold-walled where only the substrate is heated. As the reaction is chemical in nature, the temperature needed is lower than for Physical Vapor Deposition (PVD) allowing for a greater variability of materials already on the sample. The process gives fine-grained control over the material composition and growth speed by varying concentration of the precursor and temperature.

3.2.1 Plasma enhanced chemical vapor deposition (PECVD) The reaction of the precursors can be sped up by using a plasma generated over the target either with direct current (DC) or alternating current/radio frequency (AC/RF) signals. The DC approach usually works well for conductive materials but if dielectrics are deposited the plasma can be extinguished as electrode conductivity goes down. AC/RF works well for dielectric deposition. An example of a reaction chamber is shown in Figure 13.

PECVD has the advantage of keeping the substrate at a lower temperature than regular CVD and the deposition rate is usually higher. This comes at the cost of across-target uniformity and usually results in more volatile toxic byproducts.

Figure 13. Schematic of PECVD reaction.

3.2.2 Atomic layer deposition (ALD) For a greater degree of process control when it comes to the thickness of the grown films, an alternating cleansing of the chamber between each growth step can be adopted. In this case, the reactive gases are pumped into the chamber, form a monolayer thick deposit and the chamber is then vacated again using the inert carrier gas. This prevents nucleation and provides a crucial level of control when features such as parts of the gate stack are formed.

3.3 Epitaxy Epitaxial growth is a method to grow a lattice-matched crystal layer on top of another. One of the benefits is that a structure can be defined that does not pose an abrupt junction, continuing the crystal properties across the boundary. Another advantage is that layers can be grown with a small amount of strain, changing the qualities of the layer. This can be used to increase the mobility of a carrier in the strained material or be used for bandgap engineering

3.3.1 Homoepitaxy Homoepitaxy is the process of epitaxially growing the same type of material as the substrate consists of. This can be used, for example, as a buffer layer if a very high-quality crystal structure is required for an active layer.

3.3.2 Heteroepitaxy Consists of growing a different material than the substrate. The grown material is usually a compound to either lattice match the growth or produce a well- defined strain. For too large a strain or for thick layers, there will be relaxations 17

in the crystal which generates defects in the form of mostly threading dislocations.

3.3.3 Vapor phase epitaxy (VPE) Being a form of CVD as opposed to solid-phase and liquid-phase epitaxy, several advantages can be enjoyed. One advantage of VPE is that the compositional control of heteroepitaxial growths can be very finely tuned by changing the partial pressure of the involved gases. Dopants can also be added in situ and the concentration once again controlled by the partial pressure of the dopant. Using low- or reduced-pressure VPE (RP-VPE) over atmospheric pressure allows for better film uniformity and less unintentional impurities. This is mainly because the mass transport to the surface in the RP-VPE chamber decreases with the reduced pressure, making the growth more dependent on the speed of reaction which in turn provides a more homogenous growth of the film [30]. While ultra-high vacuum VPE (UHV-VPE) further improves the quality of a grown film and may be preferable for high quality device production [31] the need to pump down to a much lower pressure means that for rapid processing and trials, RP-VPE can be more desirable. The example layout of an RP-VPE system is shown in Figure 14.

Figure 14. Schematic of the ASM Epsilon 2000 Reduced Pressure Chemical Vapor Deposition (RPCVD) tool. Image from [32].

3.3.4 Selectivity Epitaxial growth should only take place on the substrate compatible with the precursor(s). The growth should be of the same type as the substrate whether amorphous, poly-crystalline or crystalline. If a Si substrate has SiO2 hard mask 18

features on it, growth should only take place on the Si substrate as can be seen in Figure 15. If the concentration and gas flow is high, there can be unwanted accumulation of amorphous material even on the hard mask [33]. If the vertical growth of the epi layer extends over the edge of the hard mask, lateral overgrowth over the mask can take place. Depending on the situation, this can either be useful in the case of forming Si-on-insulator (SOI) structures [34]. In the case of gate last MOSFET fabrication, it can present problems such as forming a short circuit between source and drain and should be avoided.

Figure 15. SiGe grown on Si substrate. The growth stops abruptly on making contact with the SiO2 dummy gate (center) and field oxide (top) showing the selectivity of the growth. The encircled areas show smaller crystallites of between 30 – 100 nm in size that accumulate in unwanted places, polycrystalline or amorphous in nature.

3.4 Physical vapor deposition (PVD) During PVD the material to be deposited is evaporated from the source by intense heating. The difference in relative pressure between source and target chambers causes the gasified material to shoot out and impinge upon the surface of the sample. The sample is rotated during the deposition to achieve a uniform deposition thickness. The tool can have either a single source element per chamber or multiple such as shown in Figure 16. PVD is best for depositing single elements and primarily metals. It can be used to deposit alloys but the difference in the thermal behavior of the constituent

elements (gas phase transition, etc.) is a limiting factor. Some metals with a very high melting point can be thermally expensive to deposit.

Figure 16. Schematic of PVD chamber. Image from [35]

3.5 Dry etching One common method of etching is reactive ion etching (RIE) [36] where ions, usually in the form of plasma harboring a reactance with the material to be etched, dislodge pieces of the material. An advantage of RIE over other methods such as sputtering [37] is that it has a high selectivity to the materials being etched which means it can be used for End point etching where the etching stops once the desired material is etched away. Dry etching is often highly anisotropic meaning it has directional etching characteristics. It can therefore be used to define structures such as deep and narrow trenches. A marked disadvantage is that dry etching is much more prone to causing damage to the structure of the material being etched than wet etching. Residual material can also be left behind causing impurities in the remaining material. In some instances, there can be high intra-wafer variability of the etch rate depending of the construction of the machine. Usually, the etching at the edges is faster.

3.6 Wet etching Wet etching is a way to remove material during the fabrication process using liquid chemicals. Hydrofluoric acid (HF) can be used to etch SiO2, Piranha (a mixture of sulfuric acid and hydrogen peroxide) can be used to etch metal and organic material, etc. In many cases, wet etching is isotropic (same etch rate regardless of crystalline orientation) which can be a detriment if a high depth to width ratio is needed. If the wafer is coated with resist, the chemicals can traverse along the interface between wafer and resist thereby etching in very unpredictable places. The subsequent rinse performed to separate the etching chemical from the sample cannot remove the chemicals stuck under the resist, giving them more time to act on the material. This also poses a potential risk to operators when handling the sample during subsequent steps. 20

An advantage of wet etching as a chemical process is that it can often be made highly material specific and from this does not pose the same threat of damaging underlying layers as dry etching might do.

3.7 Thermal oxidation While silicon dioxide can be deposited quickly with CVD, the density of the oxide is relatively low and its dielectric qualities can be lacking for thin layers. An alternative is to thermally oxidize the surface of the sample. There is a marked difference in deposition/growth speed, typical CVD deposition of oxide happens at one or a few nanometers per second [38]–[40]. Dry thermal oxidation typically takes place at about 0.01 nm per second [41]. This low growth rate allows for extremely fine control and high quality but the time required makes the growth of thicker oxides prohibitive.

Figure 17. Schematic of dry oxidation oven. Image from [42].

Oxidation is performed by loading the wafers into an oven with a layout shown in Figure 17 at a temperature between 800 and 1200 ° . The chosen ambient is then pumped into the chamber and the process runs. During the oxidation process the ambient can either be water vapor (wet 𝐶𝐶oxidation) or molecular oxygen (dry oxidation). Wet oxidation results in a higher growth rate but generally a lower density oxide and inferior quality. The time required to grow a certain thickness of oxide can be calculated with the Deal-Grove model [43]. Another feature of thermally grown oxide is that it consumes part of the substrate to form the oxide. For Si the oxide ratio to material consumed is about 2:1 but for other materials this can vary.

3.8 Silicide Silicides are the result of non-transition metals that react with Si to form better conducting composites [44]–[46]. The bonding structure ranges from covalent to ionic and meta-like in nature. The advantage of silicides is that they can provide a favorable interface between metal contacts and semiconductor materials. This decreases the parasitic resistance in the circuit and thereby the power consumed. Silicides are formed by depositing the metal on the semiconductor and then doing a high temperature anneal to form the compound while consuming some of the Si in the process.

3.9 Gate stack The design of the gate stack has become more crucial over the years as devices are shrinking. This is because the gate oxide is something that has approached the physical limit where tunneling starts to become a real problem for SiO2 at 1-2 nm. During this project, the gate stack is characterized with an in-situ doped polysilicon (IDP) gate.

3.9.1 Gate electrode The material used for the gate electrode has changed multiple times over the evolution of the different technology nodes. During the early years in the 1970’s, metal was used as the gate electrode. Subsequently the industry moved away from Al towards the use of heavily doped poly-Si instead. The change increased the thermal budget, avoiding Al diffusing as well as forming unwanted compounds with Si during annealing [47] and afforded easier manufacturing since poly-Si can be deposited with CVD. A drawback of the poly-Si is that even when highly doped, its resistivity is much higher than that of metal and therefore causes a slower charge/discharge process for the capacitance presented by the gate stack. There is also an undesired depletion effect in the polysilicon surface that affects and increases the equivalent oxide thickness through gate depletion [48].

3.9.2 Dielectrics In larger devices, SiO2 is an excellent gate oxide due to its ease of manufacturing, thermal stability, insulating properties and excellent interface to Si. As devices are scaled down and the gate oxide thickness is decreased, the required electrical (for SiO2 the same as the physical) thickness becomes small enough, around 1-2 nm, that direct tunneling from the gate electrode through the oxide into the channel takes place at an alarming rate. The way to solve this is to use so called high-K dielectrics. These materials have a higher dielectric constant than SiO2, effectively making them worse insulators. To get the same electrical behavior, a thicker oxide is needed which circumvents the problem with the physical thickness. HfO2 is probably the most well-known of these materials and was patented for use in the gate stack by Wallace, Stoltz and Wilk [49] at Texas Instruments in 2000 and has a dielectric constant between 4-6 times higher than that of SiO2 which sits at 3.9 relative permittivity.

3.10 Annealing Annealing consists of heating the sample to a high temperature the magnitude of which depends on the material and purpose. If the sample is crystalline in nature, heating it above a certain material specific temperature causes recrystallization. If the sample is doped, the annealing causes the dopants to become electrically active. Dopants can also diffuse through the material due to the elevated temperature. In some cases, this is desirable as it is part of the doping procedure [50] but for thin layers and detailed structures, the diffusion of dopants can be highly unwanted. The annealing can take place either in an oven over a span of tens of minutes or hours but can also be performed faster using Rapid Thermal

Annealing (RTA) [51] using high output lamps or lasers. This is done in cases where prolonged exposure to elevated temperatures would either cause unwanted diffusion in the material or features would directly be damaged by it. For long annealing times in a reactive ambient, unwanted thermal oxide can be formed.

3.10.1 Forming gas anneal (FGA) Forming gas is usually a mix of H (5%) and N (95%) that can be manufactured by thermal cracking of ammonia [52]. The annealing process is performed by baking the wafer at around 300 degrees C for 30 minutes in forming gas ambient. This has the advantage of driving out fixed charges from the gate dielectric and can usually significantly improve the gate control and the performance of the device, examples of which can be seen in [53].

3.11 Measurements of transistor characteristics For the electrical characterization of the devices fabricated during the scope of this project, a standardized semi-automatic probe station was used. The probe station was aligned to a reference die on the wafer and the mask layout was fed into the system. After lateral and vertical alignment, the probe station could then find discrete devices on each die on the wafer automatically using only the known device coordinates.

3.11.1 I-V measurements One of the most common measurements is to sweep the gate voltage while keeping the drain voltage constant to see the drain current response as the resistance in the channel decreases as inversion takes place. By monitoring all connected pads of the MOSFET (source, drain, bulk and gate) all the currents and voltages for each terminal can be determined and a qualitative picture of the device behavior can be constructed. Monitoring all the currents in the system also allows for the extraction of several device resistances as well as leakage currents to determine the quality of the devices.

3.11.2 Yield Using the probe station to automatically measure all devices of a certain type on a wafer, the behavior of the devices can be inspected manually and a measure of the yield (working devices/total devices) can be quantified.

3.12 Theoretical calculations for comparison with real devices As a first-instance comparison of the fabricated devices to benchmark values, theoretical calculations for regular planar MOSFETs can be carried out based on the doping concentrations, oxide thickness and general physical dimensions of the devices using the equations presented earlier under the MOSFET theory section. While theoretical calculations can usually be quite far from the workings of a fabricated device, they nonetheless serve to give a first impression of the validity of the process. The theoretical calculations then open up for more advanced means of checking the data such as simulations.

3.13 Simulation of MOSFETs Simulations of transistor characteristics can be a useful tool for evaluating the measured qualities of fabricated MOSFETs in between purely theoretical values and the real-world scenario. Compared to analytical calculations the iterative approach can be used to solve systems of equations far too complex for manual handling. By parametrizing models, they can quickly be used to test new ideas and material compositions.

3.13.1 COMSOL Multiphysics COMSOL Multiphysics from COMSOL, Inc. is a suite of simulation modules all under a larger umbrella. Electrical, mechanical and other types of simulations can be run on the same structure. Models are built in a CAD-like interface to which boundary conditions and meshing tools are applied. It is a very powerful simulation suite and has a Semiconductor Module that enables simulation of rudimentary MOSFETs. Parametric sweeps of the gate voltage can be performed to simulate MOSFET behavior. A limiting factor is that the Semiconductor Module requires all materials that are used to have a complete set of semiconductor material parameters. Outside of pure I-V characteristics, one can also plot the carrier concentration during the different states of the MOSFET.

3.14 SEM Scanning Electron Microscopy (SEM) can be used to image much smaller structures than optical microscopy by using electrons rather than photons as information carriers due to their smaller wavelength [54]. This leads to the possibility of much higher resolution images compared to optical microscopes as seen in Figure 18. Instead of the optical lenses in a microscope, electromagnetic lenses are used to focus the beam of electrons from the source to the sample. The electron beam rasterizes the target area and the detected electron intensity is used to construct an image. The use of an electron beam necessitates the use of high vacuum as the electrons are very likely to impact with gas molecules either on their way from source to sample or from the sample to the detector otherwise. For high acceleration voltages, sensitive samples can suffer damage from the high kinetic energy conferred by impinging electrons. Impinging electrons can either backscatter from the sample, generating backscattered electrons (BSE) or create ionizing impacts that lead to a cascade of electrons being released from the sample as secondary electrons (SE). Insulating samples will suffer from charging effects and to avoid charging, one method consists of detecting the BSE only as these have a much higher energy than the SE. It is also possible to use Variable Pressure SEM (VP-SEM) which utilizes a higher pressure than regular SEM to increase the discharge rate of the sample [54]. Because an SEM image is not a direct representation of what the sample looks like but a statistical picture of the electron intensity, the images need closer scrutiny than optical images to determine what is truly shown. The depth of focus for an SEM is generally longer than for an optical one which gives rise to a more three-dimensional look for good samples. The sample can also be tilted to allow inspection of topography, shown in Figure 18. 24

Figure 18. Optical microscope image at 100x (left) and SEM image (right) at ~270 000 x of similar structures. Additions have been made to the optical image to show where the SEM is focused. In addition to the much higher resolution, the SEM allows for tilting the sample to examine cross sections or topography as well as compositional analysis for thicker samples.

4 Fabrication of gate last MOSFETs

Four batches representing variations of the fabrication process were manufactured to optimize the process flow for gate last MOSFETs. These are referenced as Batch 1-4 (B1-B4) in subsequent text. The batches were fabricated chronologically with some parallel processing of Batch 3 and 4 as shown in Figure 19. Section 4.3 shows the MOSFET fabrication process flow for Batch 2 through an image series. Tool names are used for reference, further details on which can be found in Appendix A. Section 4.4 - 4.7 describes the fabrication specifics of Batch 1 - 4, giving details on when the batches deviate from the process flow in 4.3.

Figure 19. Schematic of the order of processing the batches. The second part of batch 4 had to be delayed to allow for definition of Boron doped IDP recipe for the gate electrode.

4.1 Mask set The mask used was a combined mask set that could be used either for diode or transistor fabrication. A pre-defined reticle was used; therefore, no changes could be made to the mask design for optimization in this thesis. Of the available mask layers, the following were used: Substrate (SUB), dummy gate (DG), gate (G), contact (CT) and metal 1 (M1) corresponding to lithographic steps.

4.2 Device layout An example of the mask layout for the SUB layer can be seen in Figure 20. The alignment marks were used to fit subsequent layers to the substrate layer during lithography. The measurement structures were used to measure the thickness of oxide after deposition and etching. They were also used for step height measurement and calculation of values that couldn’t be directly measured such as the S-D epitaxial growth thickness. The transistor area consisted of two rows and twenty columns for a total of 40 devices of various dimensions per die. The first row had transistors with a 400 nm overlap of the gate stack over the S-D electrodes on both sides. The second row instead had a 200 nm overlap on both sides. Columns 1-10 contained devices with a channel width of 40 µm and varying channel lengths as follows (values in µm): 0.6, 0.8, 1.0, 2, 3, 4, 6, 8, 10, 50. Columns 11-20 contained devices with a width of 10 µm with the same range of channel lengths. On each 100 mm (4”) wafer, there were 101 complete dies which was used when calculating the yield. The Vernier scales were used to gauge the misalignment of a freshly exposed lithography step to the substrate. The construction of the scales made it possible to detect much smaller deviations than would be 26

possible unaided [56]. The resolution targets were used to gauge the quality of the exposure during processing. The best resolution expected from the stepper was in the range of 0.5-0.55 µm. The diode area was not used for this project. In Figure 21 all the CAD layers in 4.1 are shown for a single transistor. This is a schematic of what the finished device should look like for a 0.6 µm device with a gate width of 40 µm from the first row.

Figure 20. SUB mask layer showing a whole die with encircled structures. Image taken from a KLayout [55] viewing of the mask CAD-files. The structures used purely for measurement here are large diodes. Two alignment marks and the first column of transistors are shown magnified as an inset.

Figure 21. All CAD layers of the finished device with terminal names shown on the contacts, as shown in KLayout.

4.3 Process flow The image series below shows the process steps used for fabrication of MOSFETs in this thesis. The process shown in the figures represents Batch 2. Step 3.4 thus means processing step 3, sub-step 4. Some sub-steps like thickness measurement, resist baking, etc. are left out for brevity.

Step 1.1 Deposition of 500 nm PECVD SiO2 in P5000. Step 2.2-3 Resist spin coat in Maximus and exposure of SUB layer in NSR.

Step 2.4 Development in Maximus removes exposed resist. Step 3.1 Dry etching in P5000 removes 480 nm of PECVD oxide.

3.2-3 Strip resist in O3 plasma and wet etch in 1% HF, SSEC, down to Step 4.1 Re-deposition of 100 nm PECVD oxide in P5000 for uniform substrate. across-wafer thickness.

Step 5.2-3 Spin coat resist in Maximus and exposure of dummy gate (DG) Step 5.4 Development in Maximus removes resist exposed in NSR. layer aligned to SUB in NSR.

Step 6.1 Dry etch in P5000 to shape the DG. 10 nm left to avoid etch Step 6.4 Strip resist in O3 plasma. damage on future S-D areas on substrate.

Step 7.1 HF 1% etch in SSEC to expose S/D areas on substrate. Etch 20 Step 7.3 Selective epitaxial growth of SiGe on the exposed Si substrate. nm to clear.

Step 8.1 Dry etch step to remove most of DG. HF 1% etch in SSEC to Step 8.2 Wet etching, 1% HF, to remove the last of the DG without etch remove the dummy gate completely while avoiding etch damage to SUB. damage to the active area.

Step 9.1 Gate oxide with a thickness of 5 nm thermally grown in Thermco Step 10.1-2 100 nm of Phosphorous doped IDP deposited in CTR-200. 5200. RTA performed to anneal.

Step 11.2-3 Resist deposited in Maximus and GATE layer exposed in NSR Step 11.4 Exposed resist removed by developing in Maximus. aligned to SUB.

Step 12.1 poly-Si dry etched (endpoint) in P5000 to define the gate area. Step 12.2 Strip resist in O3 plasma.

Step 13.1-2 20 nm PECVD SiO2 and 30 nm SiN deposited in P5000 as Step 14.1 SiN dry etched (endpoint) to expose oxide. spacers.

Step 15.1 SiO2 wet etched to open up contacts to gate, source and drain. Step 15.2 10 nm of Ni deposited in Endura.

Step 15.3 RTA performed for Ni-silicide formation. Step 15.4 Remaining Ni etched in SSEC (Piranha).

Step 16.1 Interlayer dielectric deposited in P5000, 400 nm of PEVCD SiO2. Step 17.2-3 Resist deposited in Maximus and VIA1 layer exposed in NSR.

Step 17.4 Exposed resist removed by development in Maximus. Step 18.2 VIA1 layer dry etched (endpoint) in P5000.

Step 18.3 Strip resist in O3 plasma. HF 1% wet etch in SSEC to remove Step 19.2 100 nm of TiW and 500 nm of Al deposited in Endura. oxide residue from electrode surfaces.

Step 20.2-3 Resist deposited in Maximus and METAL1 layer exposed in Step 20.4 Exposed resist is removed by development in Maximus. NSR.

Step 21.3 METAL1 layer etched to separate the contacts for source, drain, Step 21.5 – 22.1 Strip resist in O3 plasma. FGA performed. gate and body (body contact not shown here).

4.4 Batch 1 – Trial wafer, PMOSFETs with n-doped IDP gate Batch 1 (B1) consisted of a trial wafer with gate last PMOSFETs using Phosphorous (n-type) doped IDP as the gate electrode. At the time of manufacturing, no recipe for Boron (p-type) doping the IDP was available. As a result, the threshold voltage was expected to be larger in magnitude than what is normal for a PMOSFET. Source and drain areas were epitaxially grown Si0.75Ge0.25. The purposes of B1 was to provide a baseline for yield and device functionality.

4.4.1 Batch 1 processing specifics Compared to 4.3, Batch 1 did not have the etch down and re-deposition of the DG. The DG was defined by etching down to 80 nm instead of 20 nm in Step 3.1 and then carrying on to Step 5.2 directly to define the DG. This caused a variation of DG height across the wafer. While the center of the wafer had a DG of ~70 nm, at the edges it could be as low as 30 nm due to edge-fast dry etching. Removing the DG was done with wet etching in 1% HF for 130 s, not with a combination of dry/wet etching as described in the image series in Step 8.1 – 8.2.

4.5 Batch 2 – PMOSFETs with n-doped IDP gate Batch 2 (B2) consisted of two wafers with different dummy gate heights of 80 nm and 160 nm. Manufactured devices were gate last PMOSFETs with Phosphorous (n-type) doped IDP as gate electrode. Source and drain areas were epitaxially grown Si0.75Ge0.25. The purpose was to improve the yield from Batch 1 and examine the effect of the dummy gate height on yield.

4.5.1 Batch 2 processing specifics Processing was carried out as described in 4.3.

4.6 Batch 3 – NMOSFETs with n-doped IDP gate Batch 3 (B3) consisted of two wafers with gate last NMOSFETs and Phosphorous (n-type) doped IDP as gate electrode. Threshold voltage was expected to be closer to theory due to the correct dopant type being used for the gate unlike B1 and B2. Source and drain areas were epitaxially grown Si0.75Ge0.25. The purpose of Batch 3 was to evaluate the process’ transferability to n-type transistors, examine the threshold voltage and investigate the yield. I- V behaviour was expected to be symmetrical with B2 except for the lower magnitude of the threshold voltage. It was also intended to investigate the beneficial effects of removing the dry etch from Step 8.1 on PMOSFETs.

4.6.1 Batch 3 processing specifics Batch 3 was fabricated mostly in accordance with 4.3 except for the following parts. Several machines in the facility were down for maintenance which forced the use of alternatives. The gate oxide was deposited with ALD instead of being thermally grown in Step 9.1. This is known to provide a worse interface and oxide density which can result in more interface traps and leakage current. While metal deposition in step 19.2 was done in a different tool, the result was 34

considered equivalent in thickness and uniformity. Wet etch rates for 1% HF were inconsistent during processing due to problems with tank chemistry for the tool used. As etch rates were seen to fluctuate between 50% and 150% of the nominal value this caused uncertainty in steps where the etching could not be explicitly measured. The dummy gate was removed with wet etching only in 1% HF for 180 s instead of the dry/wet combination in Step 8.1 - 8.2. During fabrication, the irregularities in wet etch rates could have caused oxide to be left on areas to be silicided resulting in no silicide being formed.

4.7 Batch 4 – PMOSFETs with p-doped IDP gate Batch 4 (B4) consisted of one wafer with PMOSFETs and Boron (p-type) doped IDP as the gate electrode. Threshold voltage was expected to be closer to theory due to the correct dopant type being used for the gate unlike B1 and B2. Source and drain areas were epitaxially grown Si0.75Ge0.25. The purpose of B4 was to investigate how the Boron doped IDP affected the performance of devices compared to B1 and B2. It was also meant to investigate the effect of removing the dry etch component of dummy gate removal in Step 8.1.

4.7.1 Batch 4 processing specifics Batch 4 was fabricated mostly in accordance with 4.3. The IDP was Boron doped and deposited in another tool as well as the dummy gate being removed with wet etching in 1% HF for 180 s only. Like Batch 3, Batch 4 also suffered from inconsistent wet etch rates in 1% HF during Step 1 – 6.4, the tank chemistry problem was then remedied.

Figure 22. SEM image of a finished device, 0.8 µm channel length, 40 µm channel width. Contacts to the specific electrodes are marked.

5 Results and discussion

Chapter 5 is split up between the different batches presented in Chapter 4. The descriptions contain information on measured data, simulation results for comparison and comments on process improvements after each batch was finished. All devices were electrically characterized in the Cascade 12000 probe station using the semi-automatic mapping feature programmed in the Keithley companion software.

5.1 Device definitions Devices in this chapter are referred to by their channel length and width. Devices referred to as 1 µm devices thus have a channel length of 1 µm. All devices for Batches 1 and 2 have a width of 10 µm. All devices in Batch 3 and 4 have a width of 40 µm. As shown in 4.3 the gate overlaps the source and drain, the size of this overlap is 400 nm for all measured devices presented in this chapter. This means that the lithographic gate length is the channel length plus 0.8 µm. Low Vd was -0.1 V and 0.1 V for PMOSFETs and NMOSFETs respectively, likewise high Vd was -1 V and 1 V.

5.2 Batch 1 characterization and analysis - PMOSFETs For Batch 1, 1 µm, 10 µm and 50 µm devices were mapped and the resulting data plotted. Batch 1 suffered from low yield especially for devices with short gate lengths. For 1 µm devices yield was ~7% and 10 µm devices ~45%. For the 50 µm devices, yield was improved to ~85%. For sub 1 µm channel length, no working devices were found. Data analysis showed that there was a direct current from source to drain for non-working devices, only slightly modulated for higher gate bias, resulting in a short circuit current of ~10-3 A for high drain bias. No substantial gate leakage could be seen.

Figure 23. I-V curves for the first wafer with 1 µm (left) and 10 µm (right) devices at high drain bias (1 V). Low yield of 7 and 46 percent respectively.

Table 1. Electrical parameters for select devices from Batch 1. Lc [µm] Avg. Vt Avg. Ion Avg. Ioff Avg. DIBL Avg. SS Avg. Ig, Avg. Ib, high Yield [V] [A] [A] [mV/V] [mV/dec] high Vd [A] Vd [A] 1 -1.42 4.36*10-4 4.41*10-12 411 90 3.6*10-12 7.93*10-10 7 % 10 -1.39 3.27*10-5 7.14*10-12 459 84 1.24*10-7 9.68*10-8 46%

5.2.1 Batch 1 calculation of values How to generally calculate the electrical characteristics for the devices from data has been mentioned in 2.4. Below are the specifics of how parameters were extracted from data for this chapter.

5.2.1.1 Calculation of Vt A function was written in MATLAB which provided a numerical approximation of the derivative of a curve by examining the differences between subsequent vector entries for the Vdlow datasets. This function was given manual input to only examine the linear region of the data range to avoid rapid shifts in the noise region. After determining the maximum slope, a straight line was fitted to this slope and extrapolated down to zero current. The corresponding Vg value was extracted as the threshold voltage. The average for all working devices was then calculated.

5.2.1.2 Extraction of Ion The ON-current of a device was extracted as the absolute value of the maximum current value for the Vdhigh datasets using MATLAB’s max() operator. The average for all working devices was then calculated.

5.2.1.3 Extraction of Ioff The vector entry for Vg = 0 V was extracted and the corresponding drain current for Vdlow was taken as the OFF-current. The average for all working devices was then calculated.

5.2.1.4 Calculation of DIBL The corresponding “threshold voltage” for Vd,high was calculated as in 5.2.1.1 and the two values were then used in:

, , = , , 𝑉𝑉𝑡𝑡 ℎ𝑖𝑖𝑖𝑖ℎ 𝑉𝑉𝑉𝑉 − 𝑉𝑉𝑡𝑡 𝑙𝑙𝑙𝑙𝑙𝑙 𝑉𝑉𝑉𝑉 𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 𝑑𝑑 ℎ𝑖𝑖𝑖𝑖ℎ 𝑑𝑑 𝑙𝑙𝑙𝑙𝑙𝑙 This gave the numerically calculated𝑉𝑉 DIBL for− 𝑉𝑉 all devices and the average value for all working devices was then calculated. In some cases, what appeared numerically to be DIBL could actually have been skewed by gate induced leakage.

5.2.1.5 Average gate and bulk currents To give a rough estimation of the leakage currents, the average bulk and gate currents were calculated. First, the average value for each device over the whole range of gate voltages was calculated. Second, the average of all working devices was calculated.

5.2.1.6 Calculating SS SS was calculated through a MATLAB function that examined the slope of the linear looking region of the log10 plot of the I-V characteristics as in the equation below. This gave the numerically calculated SS for all devices and the average value for all working devices was then calculated.

[ ] = ( ) [ ] ∆𝑉𝑉𝑔𝑔 𝑚𝑚𝑚𝑚 𝑆𝑆𝑆𝑆 5.2.1.7 Yield ∆𝑙𝑙𝑙𝑙𝑙𝑙10 𝐼𝐼𝑑𝑑 𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 Yield was taken as number of working devices per wafer / 100 instead of 101. While the latter represents the actual number of devices of each type per wafer, this method provided an acceptable accuracy while not resulting in fractions of percentages.

5.2.1.8 Extraction of Rsd The Rs+Rd (Rsd) values were approximated with the Terada-Muta method [57]. The total extrinsic series resistance, of the circuit was calculated as:

𝑅𝑅𝑚𝑚= 𝑑𝑑 𝑉𝑉 The discrete values of were then𝑅𝑅𝑚𝑚 plotted against the mask gate length 𝐼𝐼𝑑𝑑 (taken from the CAD files for the mask set, the channel length plus 0.8 µm for 𝑚𝑚 𝑚𝑚 the devices presented here)𝑅𝑅 for several values of Vg. Straight lines were fitted𝐿𝐿 to the data-points using the least squares method and the intersection of the lines gave the total resistance Rsd as well as the according to Figure 25. The result for Batch 1 was a of ~900 nm and𝑒𝑒𝑒𝑒𝑒𝑒 an Rsd in the sub 1000 Ωµm region, Figure 27 (right). Definitions of the dimensions∆𝐿𝐿 are shown in Figure 24. 𝑒𝑒𝑒𝑒𝑒𝑒 ∆𝐿𝐿

Figure 24. Definitions of dimensions used for and received from the Terada-Muta method for extracting Rsd.

The values of Rm can be calculated either from discrete devices (only using a single die) or from an average across multiple devices. The first method requires the selected dies to have working devices of all gate lengths, making it difficult to use for wafers with a low yield where the working devices were spread out. For that reason, average current values were used supported by the normal distribution of current amongst devices, see Figure 26 (left).

Figure 25. Terada-Muta method for extracting Rsd, image from [57]. Prefix for unit written as KΩ in source instead of kΩ. Not normalized by channel width.

Figure 26. Current distribution at Vg = -2 V for 1 µm devices on Batch 2 (80 nm DG). Batch 2 was used as an example due to its high yield that provided a good overview.

Figure 27. Measured data points and fitted lines for determination of Rsd from average current values for Batch 1. The left part shows an overview of all data points while the right part shows the intersection in detail with markers.

5.2.2 Batch 1 post-fabrication changes As working devices were localized towards the center of the wafer, it was determined that the edge fast dry etching could cause the height of the DG on edge devices to become low enough that lateral overgrowth of crystalline SiGe during the epi step [33], [34] could take place. The process was changed so that all oxide on the active areas was first etched away. Subsequently 100 nm was redeposited before defining the DG as seen in 4.3, Step 3.1 -4.1. Due to deposition being more uniform than etching across the wafer this was determined to give more well-defined DG heights, helping avoid overgrowth.

5.3 Batch 2 characterization and analysis - PMOSFETs As the changes in processing made from Batch 1 had the largest effect on the shorter channel devices, the characterization focused initially on these devices.

5.3.1 80 nm dummy gate height (80DG) For the 80DG, yield was significantly improved to ~95% for all monitored channel lengths, examples shown in Figure 28. Electrical parameters from the 80DG part of Batch 2 are shown in Table 2. Rsd for the 80 DG was calculated in the same way as for Batch 1 with the result shown in Figure 29. The result was a of ~430 nm and Rsd in the sub 1000 Ωµm region.

∆𝐿𝐿𝑒𝑒𝑒𝑒𝑒𝑒

Figure 28. I-V curves for the 0.6 µm (left) and 1 µm (right) devices for the 80DG at high drain bias (1 V). 94% and 96% yield respectively.

Table 2. Electrical parameters for the 80DG wafer from Batch 2, select devices. Lc [µm] Avg. Vt Avg. Ion Avg. Ioff Avg. DIBL Avg. SS Avg. Ig, Avg. Ib, high Yield [V] [A] [A] [mV/V] [mV/dec] high Vd [A] Vd [A] 0.6 -1.73 1.59*10-4 3.69*10-11 303 97 1.07*10-7 3.11*10-8 94% 0.8 -1.72 1.31*10-4 5.15*10-11 318 96 2.2*10-9 3.3*10-8 98% 1 -1.72 1.11*10-4 6.73*10-11 326 94 2.14*10-9 3.51*10-8 96% 2 -1.73 6.10*10-5 1.50*10-10 339 92 2.64*10-9 4.52*10-8 97% 3 -1.73 4.21*10-5 1.68*10-10 341 93 1.42*10-8 3.64*10-8 94% 4 -1.72 3.30*10-5 3.45*10-11 351 82 1.59*10-7 2.56*10-8 93% 6 -1.72 2.27*10-5 5.28*10-11 353 77 7.62*10-6 7.56*10-6 96% 8 -1.72 1.72*10-5 3.63*10-11 352 74 3.11*10-8 3.74*10-8 98% 10 -1.72 1.37*10-5 4.15*10-11 350 74 7.65*10-8 7.65*10-6 98%

Figure 29. Measured data points and fitted lines for determination of Rsd from average current values for Batch 2, 80DG. The left part shows an overview of all data points while the right part shows the intersection in detail with markers.

5.3.2 160 nm dummy gate height (160DG) For the 160DG, yield was between 30-40% for 0.6 to 1.0 µm devices, overview shown in Figure 30. Unlike Batch 1, yield did not improve markedly with increasing channel length. Electrical parameters from the 160DG part of Batch 2 are shown in Table 1. Rsd for the 160 DG was calculated in the same way as for Batch 1 with the result shown in Figure 29. The result was a of ~1 µm and Rsd in the 10-15 kΩµm region, indicating that the interface between VIA and S-D was much worse than 𝑒𝑒𝑒𝑒𝑒𝑒 for both Batch 1 and the 80DG. This gives∆𝐿𝐿 further proof of the adverse effects of the extended dry etch of S-D that the 160DG was subjected to.

Figure 30. I-V curves for the 0.6 µm (left) and 1 µm (right) devices for the 160DG at high drain bias (1 V). 37% and 44% yield respectively.

Figure 31. Measured data points and fitted lines for determination of Rsd from average current values for Batch 2, 160DG. The left part shows an overview of all data points while the right part shows the intersection in detail with markers.

Table 3. Electrical parameters for the 160DG wafer from Batch 2, select devices. Lc [µm] Avg. Vt Avg. Ion [A] Avg. Ioff Avg. DIBL Avg. SS Avg. Ig, Avg. Ib, high Yield [V] [A] [mV/V] [mV/dec] high Vd [A] Vd [A] 0.6 -1.72 1.91*10-4 7.81*10-10 281 107 2.57*10-6 7.53*10-7 37% 0.8 -1.74 1.29*10-4 1.09*10-9 284 107 2.52*10-9 1.43*10-6 34% 1 -1.74 1.07*10-4 8.04*10-10 305 106 2.23*10-9 1.29*10-6 44%

5.3.3 Batch 2 calculation of values Electrical parameters were calculated in the same fashion as in 0. In addition, for the 80DG the logarithmic scaling of the ON-current in relation to 1/Lgate was calculated from values in Table 2 and presented in Figure 32. This shows the expected linear scaling with transistor gate length from the W/L factor seen in theoretical equations.

Figure 32. Logarithmic scaling of ON-currents with 1/ Lg for the 80DG.

Figure 33. Schematic of dry etch step during DG removal casing damage to source and drain.

5.3.4 Low yield for 160DG Since the uniform DG height and dose adjustment proved to increase the yield for the 80DG, similar behavior was expected for the 160DG. However, the introduced dry etch step for DG removal also etched the SiGe source and drain material, see Figure 33. Based on the tool documentation, Si etching for the used program should have taken place at less than 10 nm/minute. SiGe could potentially etch much faster as the CF4 component of the etchant attacks Ge much faster than Si [58] and no in-depth study has been made for the tool used. This could have led to deep etch damage to the S-D epitaxial growth and potentially the removal of the deposited material altogether. As the 160DG was subjected to 45 s of dry etching instead of 18 s for the 80DG, this could have put it over the threshold for when the damage became critical.

5.3.5 Spread of values As can be seen from the curves in Figure 30 and Figure 28, the working devices from Batch 2 showed a much larger spread in the Id magnitudes for subthreshold Vg than those from Batch 1. It was suspected that this was due to the dry etch of source and drain areas. The generally reduced ON-current could also have been because of less qualitative S-D areas and reduced quality of the contact at the etch-damaged S-D.

5.3.6 Batch 2 in-process analysis During manufacturing of Batch 2, analysis of microscope- and SEM images showed that for both the 80 nm DG (80DG) and the 160 nm DG (160DG), there was a tapering of the resist structure used to define the DG close to the upper and lower edges of the transistors as shown in Figure 34. This effect was determined to come from lithography, specifically interference either from reflections against the oxide walls, the substrate or the formation of standing optical waves in the trench surrounding the location of the DG. It was also discovered that the length of the DG (thickness of the vertical stripes in Figure 34), was lower than the mask design. This was examined in SEM and the resist was determined to be ~640 nm wide when it should have been 1 µm, shown in Figure 35. As no mask redesign could be done, the exposure dose of the stepper was adjusted to mitigate these issues.

Figure 34. Tapering on 80DG wafer (left) and 160DG wafer (right). Image taken in optical microscope at 100x. Tapered areas of the dummy gates are encircled in red.

Figure 35. 1 µm device examined in SEM. Image to the left shows only the structure where tapering is evident. Image to the right includes scales showing the thickness to be 600 nm to 700 nm instead of the 1 µm specified in the mask. Images taken after exposure with original 170 mJ/cm2 dose.

Figure 36. Dummy gate resist structures for 1 µm devices after reducing exposure dose to 125 mJ/cm2. 1 µm MOSFET. Tapering can still be noticed but at a reduced magnitude.

A focus-exposure matrix (FEM) was set up on a dummy wafer in the stepper in an 8 x 8 grid where the rightmost column had the original dose (170 mJ/cm2). Columns further left used a decreased dose. The middle row had zero alteration to the focal distance and was the one used as no focal adjustment was desired. From this method, the best dose for the DG layer was determined to be 125 mJ/cm2 and for the G layer 135 mJ/cm2. After exposure, the wafers were examined with SEM and the tapering was seen to be much smaller in magnitude, shown in Figure 36. The width of the resist strip not affected by interference from the corners improved from ~650 nm to ~880 nm. After etching the DG in Step 6.4, samples were again examined with SEM and the DG width, where not affected by tapering, was ~1.09 µm as can be seen in Figure 37. Tapered areas had a width of ~860 nm. This increase in the DG and thus channel length closer to specifications was also indicated by the differences in between Batch 1 and Batch 2 (80DG) seen previously.

∆𝐿𝐿𝑒𝑒𝑒𝑒𝑒𝑒

Figure 37. The 1 µm device after etching, images shown are from 80DG and shows just the structure (left) and the image with overlay showing scales (right).

5.3.7 Batch 2 post-fabrication changes Since the 80DG with a uniform re-deposited oxide thickness and tweaked dose had a high yield (~95%) it was set up as the backbone for future processing. Based on 5.3.4 and 5.3.5 the dry etch to remove the DG was replaced with wet etching in 1% HF only. This resulted in a wet etch step 50 seconds longer than in Batch 1 (180 s vs. 130 s).

5.4 Batch 3 characterization and analysis - NMOSFETs During characterization, no devices exhibited transistor-like behavior. Due to this no values could be calculated for the characteristics in 0. Source and drain -8 currents were constant with regards to Vg, ~5*10 A for low drain bias (0.1 V) 7 and ~5*10- A for high drain bias (1 V), scaling linearly with VD and showing no -14 gate modulation. Gate current varied from noise levels at ~10 A for VG = 0 V to ~5*10-12 A for 2.5 V. As the devices show no gate modulation, the low gate current indicated a well-insulated gate electrode or the absence of a gate altogether. On visual inspection through optical microscope, Figure 39, as well as SEM, the gate could be seen but was less pronounced than for the working devices in Batch 2. While the bulk current, as seen in Figure 38, appeared to be almost equal to the drain current which indicated leakage through the bulk, its magnitude was similar to that of the working devices in Batch 2. As the gate lithography and etch was carried out according to specifications and subsequent etch steps were not capable of attacking the gate electrode to any significant degree, it was determined that the problem must have been with the gate electrode deposition.

Figure 38. Drain (left), bulk (center) and gate (right) currents for one of the wafers in Batch 3. 1 µm devices with a channel width of 40 µm.

Figure 39. Working device from Batch 2 (left) and non-working from Batch 3 (right) under 100x magnification. While the gate is clearly visible for Batch 2 as the blue/turquoise strip, it can only be faintly seen for Batch 3 (areas encircled red). The differences in color of the surrounding areas are due to a variation in dielectric thickness for the two samples and might further add to the difficulty of seeing the gate. Images are of 1 µm devices with a channel width of 40 µm.

Figure 40. Drain (left), bulk (center) and gate (right) currents for Batch 3, 1 µm devices with a channel width of 40 µm.

5.5 Batch 4 characterization and analysis - PMOSFETs During characterization, no devices showed transistor-like behavior. Due to this no values could be calculated for the characteristics in 0. Gate currents were consistently at noise levels of sub-10-13 A for the probes indicating a non- contacted or missing gate. For 40 µm wide devices with channel lengths of 1 µm, source and drain currents were constant and in the region of 10-2 to 10-1 A for ~75% of the devices, indicating a severe short circuit the two terminals as 47

this was between three and four orders of magnitude higher than the ON- current from working devices in Batch 1 and 2. The rest of the devices only exhibited currents in the region of 10-6 A, fully explained by leakage to the bulk as seen in Figure 40. As the metal lines could be seen in SEM to be well defined with no metal residue on the surface of the device, it was determined that the short circuit must be deeper in the device. Unlike Batch 3, Figure 39, no gate could be seen for Batch 4.

5.6 Troubleshooting Batch 3 and 4 After the lack of functional devices from Batches 3 and 4, electrical characterization was carried out on the non-functional wafers. It was determined that the gate voltage had no marked effect on the transistors, indicating a non-functional or missing gate in both cases. As no etch steps after gate definition could have any marked effect on the IDP it was determined that the problem must have been with the deposition. The other processing difference between Batch 2 and Batch 3 – 4 was in the removal of the DG. For Batch 2 (80DG), a combination of dry (18 s) and wet (55 s) etching in 1% HF was used. For Batch 3-4 only wet etching in 1% HF for 180 s was used. This was studied in detail with SEM on sacrificial wafers and it was discovered that a trench with a width of ~100 nm was etched around the S-D areas if wet etching in 1% HF for 180 s was used as the only means of removing the DG. A dry etch step (18 s) and subsequent shorter wet etch (55 s) meant a trench with only ~50 nm of width as can be seen in Figure 42. For the wet only removal, there also appeared to be faster etching of the edge of the FOX that rests against the substrate creating a cavity as can be seen in Figure 41 (right). After gate deposition and etch the wide trench would not have been filled completely by the deposition of the spacers while the narrow trench would be, shown in Figure 43 - Figure 46. This could lead to subsequent etching down to the substrate for the wider trench and therefore silicidation of trench surface, S-D drain sides and even the gate, forming the severe shorts seen in Batch 4. The reason that Batch 3 exhibit much lower currents could be attributed to the previously mentioned problems with silicide formation. If no silicide was formed, the aforementioned silicide short circuit would not be present.

Figure 41. Dry + wet removal of DG (left) and wet removal only (right) for 0.6 µm devices from the same wafers as in Figure 42. 48

Figure 42. Dry + wet removal of DG (left) and wet removal only (right). The trench to the side of S-D areas is twice as wide for wet removal only at ~100 nm. Images are of 0.6 µm devices.

Figure 43. Schematic of how trenching would affect the sides of source and drain (2) as well as the top of the device creating a freestanding IDP fin (1).

Figure 44. Schematic of the proposed problem with the wider 100 nm trench resulting in exposed substrate.

Figure 45. Schematic for a narrow trench. Substrate is not exposed.

Figure 46. Schematic of the problem shown in Figure 44 but seen from the top of the device. In this instance, a wide trench could also lead to the under-etching of the spacer leaving the side of the gate exposed for contact.

5.7 Theoretical calculations and simulations To judge the plausibility of the measured values, both theoretical calculations based on textbook formulas and simulations in COMSOL Multiphysics were carried out and comparisons with measurement data can be seen in Figure 47.

Figure 47. Theoretical, simulated and measured values for PMOSFET 1 µm (left) and 10 µm (right) devices. Width for both devices is 40 µm.

5.7.1 Theoretical calculations Based on the doping levels and known dimensions of the devices from the mask, calculations were made from the formulae in 2.4 to determine theoretical values and set up a model for the current characteristics of the transistors fabricated.

Table 4. Device area doping levels. Device part Doping Active layer (n-type epi on bulk p-Si) 1017 cm-3 IDP (n-type poly-Si, Boron) 1018 cm-3 IDP (n-type poly-Si, Phosphorous) 1017 cm-3 SiGe S/D (p-type and n-type) 1020 cm-3

Table 5. Physical characteristics for theoretical calculations Device characteristic Value Channel length 0.6 – 50 µm Channel width 10 and 40 µm Tox, gate oxide thickness 5 nm

As the IDP gate and active layer had similar doping levels of the same dopant type for n-type active layer and Phosphorous-doped IDP gate, flat band voltage was treated as negligible. From the values in Table 4, Table 5 and equations from 2.4, the theoretical threshold voltage was calculated as -1.01 V for the PMOSFETs. Depletion in the poly-Gate was not considered. Throughout, equations for PMOSFETs were used which was not entirely correct since that assumed a p+ doped IDP gate whereas this work used a medium n-type doped IDP gate for all batches except 4. After Vt was calculated, equations were set up for the source-drain current for the different regions of the transistor, also using the equations from 2.4.

Figure 48. Empiric and fitted values of the surface/effective mobility for Si, image from [24].

To acquire a value for the surface mobility, the graph in Figure 48 was used to fit the extreme values of Vg (1 V and -2.5V) and a linear approximation of the value was made from there. The theoretical subthreshold slope was calculated to be 68 mV/dec.

5.7.1.1 Current model and limitations The equations from 2.4 were used to set up a MATLAB model of the S-D current for the PMOSFET. 1 µm devices and 10 µm channel width PMOSFETs from Batch 2 were calculated to be compared with corresponding measurement values and are shown in Figure 47. The theoretical current model was rudimentary and rested on several assumptions.

• That transistor equations for PMOSFETs could be used right away even though the gate was n-type IDP. • Linear approximation of the effective mobility from Figure 48. • Uncertain values for IDP and substrate doping as these could not be quantified from electrical measurements directly on the gate due to size

constraints. Nor was any in-depth material analysis such as secondary ion mass spectrometry (SIMS) carried out. • Uncertain approximation of channel and gate effects on the equivalent oxide/capacitance for the gate. • No overlap of the gate was taken into account in the equations.

5.7.2 Simulations COMSOL Multiphysics with the semiconductor module was used to set up a simulation example. COMSOL did not have data for SiGe semiconductors but from literature most of the values could be found for the material to be defined (Band gap, electron and hole mobilities, dielectric constant). Effective density of states was approximated from literature based on measured values. For epitaxially grown SiGe with a Ge content of about 25%, SiGe was considered a Si-like material giving [59]:

~ 2.8 10 19 −3 𝐶𝐶 For the valence band, it was linearly𝑁𝑁 approximated∙ 𝑐𝑐𝑐𝑐 as [59]:

= 4.32 10 (0.81 0.47 ) ~ 1.554 10 3 15 2 19 −3 𝑁𝑁𝑉𝑉 � ∙ 𝑇𝑇 � − 𝑥𝑥 ∙ 𝑐𝑐𝑐𝑐 A 2D model with an out-of-plane depth corresponding to the transistor width was built. For the 1 µm long channel the layout and gate definition is shown in Figure 49 and Figure 50 respectively. For comparison with measured devices the gate voltage was swept from -2.5 V to 1 V at Drain bias -0.1 V and -1 V to match the setup of the probe station.

Figure 49. Transistor layout, grey area is the active layer of n-type Si on the bulk p-type wafer. Wafer not included in the model, only the active area. The shaded blue areas indicated the locations of source and drain.

Figure 50. Outline of the boundary defined as the gate. Gate work function is determined from analytical calculations and the oxide thickness is known from the process flow.

5.7.2.1 Limitations in the simulation The simulation resulted in data more consistent with measurements than the analytical current model as well as smoother transitions between different regions of operation. 53

• There was no way to explicitly define the oxide quality/type. A boundary is defined as the gate layer and this is then given the values for the oxide thickness and dielectric qualities. • No way to integrate surrounding oxide, COMSOL requires all explicit materials to be semiconductors which limits the variation that can be had in the simulations. • The need to trust in material parameters provided by COMSOL or assign them oneself. Very limited list of semiconductor materials available. More advanced models could have been constructed through Synopsys [60] but as the focus of this thesis was on fabrication and characterization rather than modelling, this was not attempted.

6 Conclusions and future venues

In conclusion, several batches of gate last P- and NMOSFETs with SiGe source and drain grown epitaxially were fabricated, characterized and analyzed. For the wafer with optimal processing parameters (Batch 2, 80DG), a yield of ~95% for all device sizes was seen. Several changes were made to the process line over the course of this project.

1. The introduction of a re-deposition of the dummy gate (DG) oxide instead of just etching down to the final DG height. This was done to greatly improve the uniformity of the DG height across the wafer as edge fast etching could otherwise cause too low dummy gates to be formed at the edges. 2. Adjustment of the exposure dose for the DG and gate (G) lithographic steps to 125 mJ/cm2 and 135 mJ/cm2 respectively. This was done because interference/reflections from the sidewalls or substrate caused the DG to be severely malformed at the edges, showing tapering that could make the DG far thinner than it should be. This could be accounted for in future redesign of the mask. 3. The tweaking of the etching parameters when removing the DG. It was discovered that an overly long wet etch step, while avoiding etch damage to the source and drain, could result in a wide trench being etched down to the substrate all around the S-D areas. In combination with the silicidation steps this could be responsible for the short circuits experienced on non-working devices in Batch 4.

During the fabrication of Batches 1-3, Phosphorous was used to dope the IDP gate electrode for all devices as this was initially the only working recipe available. However, for PMOSFET devices, this can negatively impact the threshold voltage as it is the wrong doping type for the gates of such devices. Trials were made with Boron-doped IDP gate electrodes but failed to produce working devices in Batch 4. Such trials should continue to produce a working recipe for Boron doped IDP. Through imaging in SEM, it was determined that the epitaxial growth of the S-D areas on the Si bulk was highly selective. For well-defined DG heights, no overgrowth was seen. This means that the DG height could be reduced from the current 80 nm closer to the ~40 nm thickness of the epitaxially grown SiGe to reduce the etch time needed in 3). This could in turn help mitigate the trenching problem through dummy gate height optimization. It is recommended that further investigations be made into the effectiveness of the Ni-silicide used to decrease the S-D-G-B contact resistances as silicidation proved to be a problematic step coupled with the trenching issue mentioned in 3). Setting up a split with identical devices except for silicidation could provide valuable information after Rsd has been extracted for the different configurations. These devices should also be studied with SEM in detail to see the changes to topography. Rsd should also be studied more in depth as the values here were based on average current values. An interesting idea would be to characterize Rsd for discrete devices and then investigate the spread and distribution across the wafer for these values. The low Rsd generally seen indicates that the interface of the epitaxial growth was very good.

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