Field Effect Transistors
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PN Junction Is the Most Fundamental Semiconductor Device
Fundamentals of Microelectronics CH1 Why Microelectronics? CH2 Basic Physics of Semiconductors CH3 Diode Circuits CH4 Physics of Bipolar Transistors CH5 Bipolar Amplifiers CH6 Physics of MOS Transistors CH7 CMOS Amplifiers CH8 Operational Amplifier As A Black Box 1 Chapter 2 Basic Physics of Semiconductors 2.1 Semiconductor materials and their properties 2.2 PN-junction diodes 2.3 Reverse Breakdown 2 Semiconductor Physics Semiconductor devices serve as heart of microelectronics. PN junction is the most fundamental semiconductor device. CH2 Basic Physics of Semiconductors 3 Charge Carriers in Semiconductor To understand PN junction’s IV characteristics, it is important to understand charge carriers’ behavior in solids, how to modify carrier densities, and different mechanisms of charge flow. CH2 Basic Physics of Semiconductors 4 Periodic Table This abridged table contains elements with three to five valence electrons, with Si being the most important. CH2 Basic Physics of Semiconductors 5 Silicon Si has four valence electrons. Therefore, it can form covalent bonds with four of its neighbors. When temperature goes up, electrons in the covalent bond can become free. CH2 Basic Physics of Semiconductors 6 Electron-Hole Pair Interaction With free electrons breaking off covalent bonds, holes are generated. Holes can be filled by absorbing other free electrons, so effectively there is a flow of charge carriers. CH2 Basic Physics of Semiconductors 7 Free Electron Density at a Given Temperature E n 5.21015T 3/ 2 exp g electrons/ cm3 i 2kT 0 10 3 ni (T 300 K) 1.0810 electrons/ cm 0 15 3 ni (T 600 K) 1.5410 electrons/ cm Eg, or bandgap energy determines how much effort is needed to break off an electron from its covalent bond. -
Junction Field Effect Transistor (JFET)
Junction Field Effect Transistor (JFET) The single channel junction field-effect transistor (JFET) is probably the simplest transistor available. As shown in the schematics below (Figure 6.13 in your text) for the n-channel JFET (left) and the p-channel JFET (right), these devices are simply an area of doped silicon with two diffusions of the opposite doping. Please be aware that the schematics presented are for illustrative purposes only and are simplified versions of the actual device. Note that the material that serves as the foundation of the device defines the channel type. Like the BJT, the JFET is a three terminal device. Although there are physically two gate diffusions, they are tied together and act as a single gate terminal. The other two contacts, the drain and source, are placed at either end of the channel region. The JFET is a symmetric device (the source and drain may be interchanged), however it is useful in circuit design to designate the terminals as shown in the circuit symbols above. The operation of the JFET is based on controlling the bias on the pn junction between gate and channel (note that a single pn junction is discussed since the two gate contacts are tied together in parallel – what happens at one gate-channel pn junction is happening on the other). If a voltage is applied between the drain and source, current will flow (the conventional direction for current flow is from the terminal designated to be the gate to that which is designated as the source). The device is therefore in a normally on state. -
The P-N Junction (The Diode)
Lecture 18 The P-N Junction (The Diode). Today: 1. Joining p- and n-doped semiconductors. 2. Depletion and built-in voltage. 3. Current-voltage characteristics of the p-n junction. Questions you should be able to answer by the end of today’s lecture: 1. What happens when we join p-type and n-type semiconductors? 2. What is the width of the depletion region? How does it relate to the dopant concentration? 3. What is built-in voltage? How to calculate it based on dopant concentrations? How to calculate it based on Fermi levels of semiconductors forming the junction? 4. What happens when we apply voltage to the p-n junction? What is forward and reverse bias? 5. What is the current-voltage characteristic for the p-n junction diode? Why is it different from a resistor? 1 From previous lecture we remember: What happens when you join p-doped and n-doped pieces of semiconductor together? When materials are put in contact the carriers flow under driving force of diffusion until chemical potential on both sides equilibrates, which would mean that the position of the Fermi level must be the same in both p and n sides. This results in band bending: - + - + + - - Holes diffuse + Electrons diffuse The electrons will diffuse into p-type material where they will recombine with holes (fill in holes). And holes will diffuse into the n-type materials where they will recombine with electrons. 2 This means that eventually in vicinity of the junction all free carriers will be depleted leaving stripped ions behind, which would produce an electric field across the junction: The electric field results from the deviation from charge neutrality in the vicinity of the junction. -
Graphene Field-Effect Transistor Array with Integrated Electrolytic Gates Scaled to 200 Mm
Graphene field-effect transistor array with integrated electrolytic gates scaled to 200 mm N C S Vieira1,3, J Borme1, G Machado Jr.1, F Cerqueira2, P P Freitas1, V Zucolotto3, N M R Peres2 and P Alpuim1,2 1INL - International Iberian Nanotechnology Laboratory, 4715-330, Braga, Portugal. 2CFUM - Center of Physics of the University of Minho, 4710-057, Braga, Portugal. 3IFSC - São Carlos Institute of Physics, University of São Paulo, 13560-970, São Carlos-SP, Brazil E-mail: [email protected] Abstract Ten years have passed since the beginning of graphene research. In this period we have witnessed breakthroughs both in fundamental and applied research. However, the development of graphene devices for mass production has not yet reached the same level of progress. The architecture of graphene field-effect transistors (FET) has not significantly changed, and the integration of devices at the wafer scale has generally not been sought. Currently, whenever an electrolyte-gated FET (EGFET) is used, an external, cumbersome, out-of-plane gate electrode is required. Here, an alternative architecture for graphene EGFET is presented. In this architecture, source, drain, and gate are in the same plane, eliminating the need for an external gate electrode and the use of an additional reservoir to confine the electrolyte inside the transistor active zone. This planar structure with an integrated gate allows for wafer-scale fabrication of high-performance graphene EGFETs, with carrier mobility up to 1800 cm2 V-1 s-1. As a proof-of principle, a chemical sensor was achieved. It is shown that the sensor can discriminate between saline solutions of different concentrations. -
Lecture 16 the Pn Junction Diode (III)
Lecture 16 The pn Junction Diode (III) Outline • Small-signal equivalent circuit model • Carrier charge storage –Diffusion capacitance Reading Assignment: Howe and Sodini; Chapter 6, Sections 6.4 - 6.5 6.012 Spring 2007 Lecture 16 1 I-V Characteristics Diode Current equation: ⎡ V ⎤ I = I ⎢ e(Vth )−1⎥ o ⎢ ⎥ ⎣ ⎦ I lg |I| 0.43 q kT =60 mV/dec @ 300K Io 0 0 V 0 V Io linear scale semilogarithmic scale 6.012 Spring 2007 Lecture 16 2 2. Small-signal equivalent circuit model Examine effect of small signal adding to forward bias: ⎡ ⎛ qV()+v ⎞ ⎤ ⎛ qV()+v ⎞ ⎜ ⎟ ⎜ ⎟ ⎢ ⎝ kT ⎠ ⎥ ⎝ kT ⎠ I + i = Io ⎢ e −1⎥ ≈ Ioe ⎢ ⎥ ⎣ ⎦ If v small enough, linearize exponential characteristics: ⎡ qV qv ⎤ ⎡ qV ⎤ ()kT (kT ) (kT )⎛ qv ⎞ I + i ≈ Io ⎢e e ⎥ ≈ Io ⎢e ⎜ 1 + ⎟ ⎥ ⎣⎢ ⎦⎥ ⎣⎢ ⎝ kT⎠ ⎦⎥ qV qV qv = I e()kT + I e(kT ) o o kT Then: qI i = • v kT From a small signal point of view. Diode behaves as conductance of value: qI g = d kT 6.012 Spring 2007 Lecture 16 3 Small-signal equivalent circuit model gd gd depends on bias. In forward bias: qI g = d kT gd is linear in diode current. 6.012 Spring 2007 Lecture 16 4 Capacitance associated with depletion region: ρ(x) + qNd p-side − n-side (a) xp x = xn vD VD − qNa = − QJ qNaxp ρ(x) + qNd p-side −x −x n-side (b) p p x xn xn = + > > vD VD vd VD-- − qNa x < x |q | < |Q | p p, J J = − qJ qNaxp = ∆ ∆ρ = ρ − ρ qj qNa xp (x) (x) (x) + qNd X p-side d n-side (c) x n xn − − xp xp x q = q − Q > j j j 0 − qN = −qN x − −qN a − = − ∆ a p ( axp) qj qNd xn = − qNa (xp xp) ∆ = qNa xp Depletion or junction capacitance: dqJ C j = C j (VD ) = dvD VD qεsNa Nd C j = A 2()Na + Nd ()φB −VD 6.012 Spring 2007 Lecture 16 5 Small-signal equivalent circuit model gd Cj can rewrite as: qεsNa Nd φB C j = A • 2()Na + Nd φB ()φB −VD C or, C = jo j V 1− D φB φ Under Forward Bias assume V ≈ B D 2 C j = 2C jo Cjo ≡ zero-voltage junction capacitance 6.012 Spring 2007 Lecture 16 6 3. -
Advanced MOSFET Structures and Processes for Sub-7 Nm CMOS Technologies
Advanced MOSFET Structures and Processes for Sub-7 nm CMOS Technologies By Peng Zheng A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Engineering - Electrical Engineering and Computer Sciences in the Graduate Division of the University of California, Berkeley Committee in charge: Professor Tsu-Jae King Liu, Chair Professor Laura Waller Professor Costas J. Spanos Professor Junqiao Wu Spring 2016 © Copyright 2016 Peng Zheng All rights reserved Abstract Advanced MOSFET Structures and Processes for Sub-7 nm CMOS Technologies by Peng Zheng Doctor of Philosophy in Engineering - Electrical Engineering and Computer Sciences University of California, Berkeley Professor Tsu-Jae King Liu, Chair The remarkable proliferation of information and communication technology (ICT) – which has had dramatic economic and social impact in our society – has been enabled by the steady advancement of integrated circuit (IC) technology following Moore’s Law, which states that the number of components (transistors) on an IC “chip” doubles every two years. Increasing the number of transistors on a chip provides for lower manufacturing cost per component and improved system performance. The virtuous cycle of IC technology advancement (higher transistor density lower cost / better performance semiconductor market growth technology advancement higher transistor density etc.) has been sustained for 50 years. Semiconductor industry experts predict that the pace of increasing transistor density will slow down dramatically in the sub-20 nm (minimum half-pitch) regime. Innovations in transistor design and fabrication processes are needed to address this issue. The FinFET structure has been widely adopted at the 14/16 nm generation of CMOS technology. -
Transistor Biasing
Module 2:BJT Biasing Quote of the day "Peace cannot be kept by force. It can only be achieved by understanding”. ― Albert Einstein DC Load line and Bias Point • DC Load Line – For a transistor a straight line drawn on transistor output characteristics. IC – For CE circuit, the load line is a graph of collector current I versus V for a fixed C CE IB + value of R and supply voltage V C CC + VCE – Load Line? VCC VCE I C RC VBE - - V V I R – From Figure VCE=? CE CC C C – If VBE =0 then IC=0, VCE = VCC plot this point on characteristics(A). – Now assume that ICRC = VCC, i.e. IC = VCC /RC then VCE =0. Plot this point on characteristics(B). – Join points A and B by a straight line. DC Load line contd.. VCE VCC I C RC VV IC CC CE IC RC V CC B IC(sat) RC DC load line VVCE(off ) CC V A CE Example 1. Plot the dc load line for the circuit shown in Fig. Then, find the values of VCE for IC = 1, 2, 5 mA respectively. VVIRCE CC C C VCE 10 for I c 0 10 I 10mA c 110 3 IC (mA) VCE (V) 1 9 2 8 5 5 4 Example 2. For the circuit shown and Plot of the dc load line in Fig. find the values of IC for VCE = 0V and VCE for IC = 0. VVIRCE CC C C 5 I C 4.54mA V CC15V For the previous circuit shown observe the Plot of the dc load line with Rc=4.8 K find the values of IC for VCE = 0V and VCE for IC = 0. -
Fundamentals of MOSFET and IGBT Gate Driver Circuits
Application Report SLUA618A–March 2017–Revised October 2018 Fundamentals of MOSFET and IGBT Gate Driver Circuits Laszlo Balogh ABSTRACT The main purpose of this application report is to demonstrate a systematic approach to design high performance gate drive circuits for high speed switching applications. It is an informative collection of topics offering a “one-stop-shopping” to solve the most common design challenges. Therefore, it should be of interest to power electronics engineers at all levels of experience. The most popular circuit solutions and their performance are analyzed, including the effect of parasitic components, transient and extreme operating conditions. The discussion builds from simple to more complex problems starting with an overview of MOSFET technology and switching operation. Design procedure for ground referenced and high side gate drive circuits, AC coupled and transformer isolated solutions are described in great details. A special section deals with the gate drive requirements of the MOSFETs in synchronous rectifier applications. For more information, see the Overview for MOSFET and IGBT Gate Drivers product page. Several, step-by-step numerical design examples complement the application report. This document is also available in Chinese: MOSFET 和 IGBT 栅极驱动器电路的基本原理 Contents 1 Introduction ................................................................................................................... 2 2 MOSFET Technology ...................................................................................................... -
Shults Robert D 196308 Ms 10
AN INVESTIGATION OF THE INFLUENCE OF CIRCUIT PARAMETERS ON THE OUTPUT WAVESHAPE OF A TUNNEL DIODE OSCILLATOR A THESIS Presented to The Faculty of the Graduate Division by Robert David Shults In Partial Fulfillment of the Requirements for the Degree Master of Science in Electrical Engineering Georgia Institute of Technology June, I963 AN INVESTIGATION OF THE INFLUENCE OF CIRCUIT PARAMETERS ON THE OUTPUT WAVESHAPE OF A TUNNEL DIODE OSCILLATOR Approved: —VY -w/T //'- Dr. W. B.l/Jonesj UJr. (Chairman) _A a t~l — Dry 3* L. Hammond, Jr. V ^^ __—^ '-" ^^ *• Br> J. T. Wang * Date Approved by Chairman: //l&U (A* l/j^Z) In presenting the dissertation as a partial, fulfillment of the requirements for an advanced degree from the Georgia Institute of Technology, I agree that the Library of the Institution shall make it available for inspection and circulation in accordance witn its regulations governing materials of this type. I agree -chat permission to copy from, or to publish from, this dissertation may be granted by the professor under whose direction it was written^ or, in his absence, by the dean of the Graduate Division when luch copying or publication is solely for scholarly purposes ftad does not involve potential financial gain. It is under stood that any copying from, or publication of, this disser tation which involves potential financial gain will not be allowed without written permission. _/2^ d- ii ACKNOWLEDGMEBTTS The author wishes to thank his thesis advisor, Dr. W. B„ Jones, Jr., for his suggestion of the problem and for his continued guidance and encouragement during the course of the investigation. -
Photodetectors
Photodetectors • Convert light signals to a voltage or current. • The absorption of photons creates electron hole pairs. • Electrons in the CB and holes in the VB. • A p + n type junction describes a heavily doped p-type material(acceptors) that is much greater than a lightly doped n-type material (donor) that it is embedded into. • Illumination window with an annular electrode for photon passage. • Anti-reflection coating ( Si 3 N 4 ) reduces reflections. Vr (a) SiO 2 R Vout Electrode p+ Iph Photodetectors h" > E + g h e– n E + Antireflection Electrode • The side is on the order of less than a coating p W Depletion region micron thick (formed by planar diffusion ! (b) net into n-type epitaxial layer). eNd x • A space charge distribution occurs about the junction within the depletion layer. –eNa E (x) (c) • The depletion region extends x predominantly into the lightly doped n region ( up to 3 microns max) E max (a) A schematic diagram of a reverse biased pn junction photodiode. (b) Net space charge across the diode in the depletion region. Nd and Na are the donor and acceptor concentrations in the p and n sides. (c). The field in the depletion region. © 1999 S.O. Kasap, Optoelectronics (Prentice Hall) Photodetectors Short wavelengths (ex. UV) are absorbed at the surface, and longer wavelengths (IR) will penetrate into the depletion layer. What would be a fundamental criteria for a photodiode with a wide spectral response? Thin p-layer and thick n layer. What does thickness of depletion layer determine (along with reverse bias)? Diode capacitance. -
Work Function and Process Integration Issues of Metal
WORK FUNCTION AND PROCESS INTEGRATION ISSUES OF METAL GATE MATERIALS IN CMOS TECHNOLOGY REN CHI NATIONAL UNIVERSITY OF SINGAPORE 2006 WORK FUNCTION AND PROCESS INTEGRATION ISSUES OF METAL GATE MATERIALS IN CMOS TECHNOLOGY REN CHI B. Sci. (Peking University, P. R. China) 2002 A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE OCTOBER 2006 _____________________________________________________________________ ACKNOWLEGEMENTS First of all, I would like to express my sincere thanks to my advisors, Prof. Chan Siu Hung and Prof. Kwong Dim-Lee, who provided me with invaluable guidance, encouragement, knowledge, freedom and all kinds of support during my graduate study at NUS. I am extremely grateful to Prof. Chan not only for his patience and painstaking efforts in helping me in my research but also for his kindness and understanding personally, which has accompanied me over the past four years. He is not only an experienced advisor for me but also an elder who makes me feel peaceful and blessed. I also greatly appreciate Prof. Kwong from the bottom of my heart for his knowledge, expertise and foresight in the field of semiconductor technology, which has helped me to avoid many detours in my research work. I do believe that I will be immeasurably benefited from his wisdom and professional advice throughout my career and my life. I would also like to thank Prof. Kwong for all the opportunities provided in developing my potential and personality, especially the opportunity to join the Institute of Microelectronics, Singapore to work with and learn from so many experts in a much wider stage. -
New Applications of Organic Polymers in Chemical Gas Sensors
New Applications of Organic Polymers in Chemical Gas Sensors Neue Einsatzmöglichkeiten organischer Polymere in chemischen Gassensoren Dissertation der Fakultät für Chemie und Pharmazie der Eberhard-Karls-Universität Tübingen zur Erlangung des Grades eines Doktors der Naturwissenschaften 2005 vorgelegt von Mika Harbeck Tag der mündlichen Prüfung: 18.11.2005 Dekan: Prof. Dr. S. Laufer 1. Berichterstatter: PD Dr. U. Weimar 2. Berichterstatter: Prof. Dr. G. Gauglitz Contents 1. Introduction 1 1.1. Introduction to the Field ...................... 1 1.2. Motivation and Scope ....................... 4 1.3. Overview of the Presented Work ................. 5 2. Theoretical Background and Related Work 7 2.1. Sorption Processes ......................... 7 2.2. Electrochemical Aspects of Interfaces .............. 11 2.3. The Chemical and Physical Structure of the Electrical Double Layer................................. 16 2.4. Measuring the Work Function and Surface Potentials ..... 30 2.5. Chemical Sensing with Field Effect Devices ........... 41 3. Experimental Details 51 3.1. Instrumental Equipment ...................... 51 3.2. Materials for the Preparation of the Sensing Layers ...... 59 3.3. Polymer Deposition ......................... 64 3.4. Measurement Procedure ...................... 70 4. Sensitive Layer Morphology: Characterisation and Optimization 73 4.1. Polyacrylic Acid Layers ...................... 74 4.2. Polystyrene Layers ......................... 81 4.3. Poly-(4-vinylphenol) Layers .................... 84 4.4. Poly-(acrylonitrile-co-butadiene) Layers ............. 86 4.5. Poly-(cyanopropyl-phenyl-siloxane) Layers ........... 87 4.6. Summary ............................... 87 5. Response to Analyte Gases 89 5.1. Inert Reference Material and Uncoated Substrates ....... 89 5.2. Polyacrylic Acid Coated Substrates ................ 91 5.3. Polystyrene Coated Substrates .................. 114 5.4. Poly-(4-vinylphenol) Coated Substrates ............. 122 5.5. Poly-(acrylonitrile-co-butadiene) Coated Substrates .....