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Field Effect Transistors Field Effect Transistors Lecture 9 Types of FET • Metal Oxide Semiconductor Field Effect Transistor – MOSFET – Enhancement mode – Depletion mode • Junction FETs • p channel vs n channel 38 Metal Oxide Semiconductor Field Effect Transistor MOSFET (NMOS) Enhancement Mode • Consists of Four terminals – Drain which is n-doped material G S D – Source also n-doped material Oxide – Base which is p-doped material Metal Gate Drain – Gate is a metal and is insulated from the Drain, Source Source and Base by a thin layer of silicon dioxide ~ .05-.1mm thick • Basically, an electric current flowing from drain to source, iD, is controlled by the amount of voltage n+ n+ (electric field) appearing between the gate and base p (note that the base and source are usually tied together and therefore, it is referred to as the gate to source voltage or gate voltage), vGS. Substrate, body or Base • iD flows through a channel of n-type material which B is induced by vGS. The amount of iD is a function of the thickness of the channel and the voltage between drain and source, vDS • However, the thickness of channel is controlled by the level of gate voltage. (The width, .5 to 500 mm, and length, .2 to 10 mm, of the channel is shown in the diagram.) 39 Metal Oxide Semiconductor Field Effect Transistor MOSFET (NMOS) Enhancement Mode • Consists of Four terminals – Drain which is n-doped material – Source also n-doped material G – Base which is p-doped material S D – Gate is a metal and is insulated from the Drain, Oxide Source and Base by a thin layer of silicon Metal Gate Drain dioxide ~ .05-.1mm thick Source • Basically, an electric current flowing from drain to source, iD, is controlled by the amount of voltage (electric field) appearing between the gate and base W (note that the base and source are usually tied n+ L n+ together and therefore, it is referred to as the gate to p source voltage or gate voltage), vGS. • iD flows through a channel of n-type material which is induced by v . The amount of i is a function of Substrate, body or Base GS D the thickness of the channel and the voltage between B drain and source, vDS • However, the thickness of channel is controlled by the level of gate voltage. (The width, .5 to 500 mm, and length, .2 to 10 mm, of the channel is shown in the diagram.) 40 Modes of the NMOS Cutoff iD • vGS = 0 D • pn junctions at the drain n and source are reverse G p B biased due to vDS • i is zero D n + + vGS vDS - S - G D + vDS + S - vGS - 41 Modes of the NMOS Triode Region iD • vGS ≥ Vto a threshold voltage which causes electrons in the base to be D attracted to and holes to be repelled n from the region just below the gate • This process causes a n-type channel to G form below the gate p B • As vDS is increased, iD starts to flow. n For small values of vDS, iD is + + vGS vDS proportional to vDS - S - • In addition, iD is proportional to vGS- Vto, the excess gate voltage • Therefore, the MOSFET can act as a voltage controlled resistor in the Triode Region (e.g., used in AGC circuits) increasing vGS iD vDS 42 Modes of the NMOS Triode Region iD • vGS ≥ Vto a threshold voltage which causes electrons in the base to be D attracted to and holes to be repelled n from the region just below the gate G • This process causes a n-type channel to p B form below the gate n • As vDS is increased, iD starts to flow. + + vGS vDS For small values of vDS, iD is - S - proportional to vDS • In addition, iD is proportional to vGS- Vto, the excess gate voltage • Therefore, the MOSFET can act as a increasing vGS voltage controlled resistor in the Triode iD Region (e.g., used in AGC circuits) vDS 43 Modes of the NMOS Triode Region (Continued) • Since the drain is more positive than the iD source, the voltage difference between the channel and the gate varies along the D channel from drain to source. n • As vDS is further increased, this channel voltage profile causes a tapering of the G p B channel thickness. vGD ≠ vGS • This tapering causes the resistance of the channel to increase (as v increases) and, n DS + + thereby, reduces the rate of increase of iD. vGS S vDS • Furthermore, it can be shown that - - 2 iD = K[2(vGS −Vto )vDS − vDS ] W KP W µ C K = ( )( ) = ( )( n ox ) L 2 L 2 increasing vGS • To summarize: vGS ≥ Vto and vDS< vGS- Vto iD vDS 44 Modes of the NMOS Saturation i • As vDS continues to increase, the voltage D profile continues to taper. When the gate to channel voltage at the drain, vGD, D approaches Vto , the thickness of the channel at the drain is (virtually) zero. n (Note that although the channel thickness G is virtually zero, current flow is not cutoff p B since it is needed to support the channel voltage profile.) n • This phenomenon limits the amount of + + vGS S vDS drain current (i.e., iD is saturated) and - - causes iD to be independent of vDS • Furthermore, it can be shown that 2 iD = K(vGS −Vto ) Triode • Summarize: vGS ≥ Vto and vDS ≥ vGS- Vto iD Saturation vDS 45 Modes of the NMOS iD Triode D n i G D p B Saturation n + + vGS vDS - S - Cutoff vDS 46 NMOS Characteristics 20 vGS = 5v iD mA 15 vGS = 4v 10 v = 3v 5 GS vGS = 2v Note that Vto = 1 0 0 2 4 6 8 10 12 14 16 18 20 vDS Volts Note that for NMOS devices with short channel lengths, a tilt may exist due to the modulation of the channel length by the depletion region surrounding the drain. 47 Load Line of a NMOS Amplifier RD 1k 20 iD mA + M1 VDD Mna me - 20V vGS = 5v Vin sin(2000πt) +- 15 VGG + - 4V 0 10 vGS = 4v Gate Circuit 5 vGS = 3v vGS=+ v in () t VGG vGS = 2v =+sin(2000πt ) 4 0 0 2 4 6 8 10 12 14 16 18 20 4 11 16 vDS Drain Circuit Volts VDD=+ iDDS RD v Inverted and distorted 20=+ivDDS 1000 48 Ion Sensing Field Effect Transistor (ISFET) • Δϕ= RT/F ln (c1/c2) • R is the gas constant, T the absolute temperature (K) and F the Faraday constant and ci, are ion concentrations in the solution and oxide. • Using hydrogen ions can be used to measure pH1 and DNA2 1 Bergveld, P. ISFET, Theory and Practice, IEEE SENSOR CONFERENCE TORONTO, OCTOBER 2003 2 DNA Electronics, Http://dnae.co.uk/tecHnology/overview/ 49 n-channel Junction FET Drain D Gate p n p G Source S 50 N-channel JFET Gate Bias D D D n n n G G G p p p p p p - - + + S S S Zero Bias and depletion layer is thin and 0>vGS>Vto vGS ≤ Vto conduction channel exists Small bias results in larger Larger bias > pinch-off voltage, V , from drain to source depletion layer and smaller to creates overlapping depletion layer channel and no conductive path from drain to source Cutoff Region 51 n-channel JFET Operation D D D vDS= 0 n n n vDS≤ |Vto| vDS> + G + G G + p p p p |Vto| - - p p - S S S Triode Region ID=0 Saturation Region With vGS=0, we increase vDS and enter the Triode Region. As a result ID increases and is proportional to vDS. As vDS increases further, the depletion region between drain and gate grows (with a larger area nearer the drain) and adds more resistance in the channel by narrowing its width. Thus, the rate of drain current increase slows down with increasing vDS. As vDS reaches the pinch-off voltage, Vt0, the drain current, ID saturates (i.e., the FET is in the Saturation Region). Triode With vGS<0, the same phenomenon occurs as vDS is increased. iD However, the non-zero value of vGS increases the resistance in the Saturation channel due to a large depletion layer and therefore, values of ID are smaller both in the Triode and Saturation regions. vDS 52 n-channel JFET Operation D vDS= 0 n G + p p - S As vDS increase ID increases and JFET enters the Triode Region. Triode iD Saturation v Cutoff DS 53 n-channel JFET Operation D vDS= 0 n G + p p - S Triode Region Because the channel is “wide”, ID is proportional to vDS. Triode iD Saturation v Cutoff DS 54 n-channel JFET Operation D n G + vDS≤ |Vto| p p - S Triode Region While vDS increases, the depletion region also grows with a larger area at the drain. As a result, the channel resistance increases and increases in ID are reduced. Triode iD Saturation v Cutoff DS 55 n-channel JFET Operation D n vDS> + G |Vto| p p - S Saturation Region The depletion region increases as vDS increases. As a result, the depletion region is “pinched off” and ID does not increase any further (i.e., ID is saturated). Triode iD Saturation v Cutoff DS 56 n-channel JFET Operation D iD G + + - + vDS vGS - - - + S Triode iD Saturation v Cutoff DS 57 JFET Characteristics 20 vGS = 0v iD mA 15 vGS = -1v 10 v = -2v 5 GS vGS = -3v Note that Vto = -4 0 0 2 4 6 8 10 12 14 16 18 20 vDS Volts Note that for NMOS devices with short channel lengths, a tilt may exist due to the modulation of the channel length by the depletion region surrounding the drain.
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