Field Effect Transistors

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Lecture 9 Types of FET

• Metal Oxide Semiconductor Field Effect Transistor – MOSFET – Enhancement mode – Depletion mode • Junction FETs • p channel vs n channel

38 Metal Oxide Semiconductor Field Effect Transistor MOSFET (NMOS) Enhancement Mode

• Consists of Four terminals – Drain which is n-doped material G S D – Source also n-doped material Oxide – Base which is p-doped material Metal Gate Drain – Gate is a metal and is insulated from the Drain, Source Source and Base by a thin layer of silicon dioxide ~ .05-.1mm thick • Basically, an electric current flowing from drain to

source, iD, is controlled by the amount of voltage n+ n+ (electric field) appearing between the gate and base p (note that the base and source are usually tied together and therefore, it is referred to as the gate to

source voltage or gate voltage), vGS. Substrate, body or Base • iD flows through a channel of n-type material which B is induced by vGS. The amount of iD is a function of the thickness of the channel and the voltage between

drain and source, vDS • However, the thickness of channel is controlled by the level of gate voltage. (The width, .5 to 500 mm, and length, .2 to 10 mm, of the channel is shown in the diagram.) 39 Metal Oxide Semiconductor Field Effect Transistor MOSFET (NMOS) Enhancement Mode • Consists of Four terminals – Drain which is n-doped material – Source also n-doped material G – Base which is p-doped material S D – Gate is a metal and is insulated from the Drain, Oxide Source and Base by a thin layer of silicon Metal Gate Drain dioxide ~ .05-.1mm thick Source • Basically, an electric current flowing from drain to

source, iD, is controlled by the amount of voltage (electric field) appearing between the gate and base W (note that the base and source are usually tied n+ L n+ together and therefore, it is referred to as the gate to

p source voltage or gate voltage), vGS.

• iD flows through a channel of n-type material which is induced by v . The amount of i is a function of Substrate, body or Base GS D the thickness of the channel and the voltage between B drain and source, vDS • However, the thickness of channel is controlled by the level of gate voltage. (The width, .5 to 500 mm, and length, .2 to 10 mm, of the channel is shown in the diagram.)

40 Modes of the NMOS Cutoff

• vGS = 0 D • pn junctions at the drain n and source are reverse G p B biased due to vDS • i is zero D n + + vGS vDS - S -

G D + vDS + S - vGS -

41 Modes of the NMOS Triode Region

• vGS ≥ Vto a threshold voltage which causes electrons in the base to be D attracted to and holes to be repelled n from the region just below the gate • This process causes a n-type channel to G form below the gate p B

• As vDS is increased, iD starts to flow. n For small values of vDS, iD is + + vGS vDS proportional to vDS - S - • In addition, iD is proportional to vGS- Vto, the excess gate voltage • Therefore, the MOSFET can act as a voltage controlled resistor in the Triode

Region (e.g., used in AGC circuits) increasing vGS iD

vDS 42 Modes of the NMOS Triode Region

• vGS ≥ Vto a threshold voltage which causes electrons in the base to be D attracted to and holes to be repelled n from the region just below the gate G • This process causes a n-type channel to p B form below the gate n • As vDS is increased, iD starts to flow. + + vGS vDS For small values of vDS, iD is - S - proportional to vDS

• In addition, iD is proportional to vGS- Vto, the excess gate voltage • Therefore, the MOSFET can act as a increasing vGS voltage controlled resistor in the Triode iD Region (e.g., used in AGC circuits)

vDS 43 Modes of the NMOS Triode Region (Continued) • Since the drain is more positive than the iD source, the voltage difference between the channel and the gate varies along the D channel from drain to source. n • As vDS is further increased, this channel voltage profile causes a tapering of the G p B channel thickness. vGD ≠ vGS • This tapering causes the resistance of the channel to increase (as v increases) and, n DS + + thereby, reduces the rate of increase of iD. vGS S vDS • Furthermore, it can be shown that - - 2 iD = K[2(vGS −Vto )vDS − vDS ] W KP W µ C K = ( )( ) = ( )( n ox ) L 2 L 2 increasing vGS • To summarize: vGS ≥ Vto and vDS< vGS- Vto iD

vDS 44 Modes of the NMOS Saturation i • As vDS continues to increase, the voltage D profile continues to taper. When the gate to channel voltage at the drain, vGD, D approaches Vto , the thickness of the channel at the drain is (virtually) zero. n (Note that although the channel thickness G is virtually zero, current flow is not cutoff p B since it is needed to support the channel voltage profile.) n • This phenomenon limits the amount of + + vGS S vDS drain current (i.e., iD is saturated) and - - causes iD to be independent of vDS • Furthermore, it can be shown that 2 iD = K(vGS −Vto ) Triode • Summarize: vGS ≥ Vto and vDS ≥ vGS- Vto iD Saturation

vDS 45 Modes of the NMOS

i D

Triode D n i G D p B Saturation

n + + vGS vDS - S -

Cutoff vDS

46 NMOS Characteristics

vGS = 5v iD mA 15

vGS = 4v 10

v = 3v 5 GS

vGS = 2v Note that Vto = 1 0 0 2 4 6 8 10 12 14 16 18 20

vDS Volts

Note that for NMOS devices with short channel lengths, a tilt may exist due to the modulation of the channel length by the depletion region surrounding the drain.

47 Load Line of a NMOS Amplifier

RD 1k 20 iD mA

+ M1 VDD Mna me - 20V vGS = 5v Vin sin(2000πt) +- 15 VGG

+ - 4V 0 10 vGS = 4v Gate Circuit

5 vGS = 3v vGS=+ v in () t VGG vGS = 2v =+sin(2000πt ) 4 0 0 2 4 6 8 10 12 14 16 18 20 4 11 16 vDS Drain Circuit Volts

VDD=+ iDDS RD v Inverted and distorted 20=+ivDDS 1000

48 Ion Sensing Field Effect Transistor (ISFET)

• Δϕ= RT/F ln (c1/c2) • R is the gas constant, T the absolute temperature (K) and F the Faraday constant and ci, are ion concentrations in the solution and oxide. • Using hydrogen ions can be used to measure pH1 and DNA2

1 Bergveld, P. ISFET, Theory and Practice, IEEE SENSOR CONFERENCE TORONTO, OCTOBER 2003 2 DNA Electronics, http://dnae.co.uk/technology/overview/

49 n-channel Junction FET

Drain

Gate p n p G

Source S

50 N-channel JFET Gate Bias

D D D

n n n

G G G

p p p p p p

- -

+ +

S S S

Zero Bias and depletion layer is thin and 0>vGS>Vto vGS ≤ Vto conduction channel exists Small bias results in larger Larger bias > pinch-off voltage, V , from drain to source depletion layer and smaller to creates overlapping depletion layer channel and no conductive path from drain to source Cutoff Region 51 n-channel JFET Operation

D D D vDS= 0 n n n vDS≤ |Vto| vDS> + G + G G + p p p p |Vto| - - p p -

S S S Triode Region ID=0 Saturation Region With vGS=0, we increase vDS and enter the Triode Region. As a result ID increases and is proportional to vDS. As vDS increases further, the depletion region between drain and gate grows (with a larger area nearer the drain) and adds more resistance in the channel by narrowing its width. Thus, the rate of drain current increase slows

down with increasing vDS. As vDS reaches the pinch-off voltage, Vt0, the drain current, ID saturates (i.e., the FET is in the Saturation Region). Triode With vGS<0, the same phenomenon occurs as vDS is increased. iD However, the non-zero value of vGS increases the resistance in the Saturation channel due to a large depletion layer and therefore, values of ID are smaller both in the Triode and Saturation regions. vDS 52 n-channel JFET Operation D vDS= 0 n

G + p p -

As vDS increase ID increases and JFET enters the Triode Region.

Triode

iD Saturation

v Cutoff DS

53 n-channel JFET Operation D vDS= 0 n

G + p p -

Triode Region Because the channel is “wide”, ID is proportional to vDS.

Triode

iD Saturation

v Cutoff DS

54 n-channel JFET Operation D n

G + vDS≤ |Vto| p p -

Triode Region

While vDS increases, the depletion region also grows with a larger area at the drain. As a result, the channel resistance increases and increases in ID are reduced.

Triode

iD Saturation

v Cutoff DS

55 n-channel JFET Operation D n vDS> + G |Vto| p p -

Saturation Region The depletion region increases as vDS increases. As a result, the depletion region is “pinched off” and ID does not increase any further (i.e., ID is saturated).

Triode

iD Saturation

v Cutoff DS

56 n-channel JFET Operation

D iD

G + + - + vDS

vGS - - - +

Triode

iD Saturation

v Cutoff DS

57 JFET Characteristics

vGS = 0v iD mA 15

vGS = -1v 10

v = -2v 5 GS

vGS = -3v Note that Vto = -4 0 0 2 4 6 8 10 12 14 16 18 20

vDS Volts

Note that for NMOS devices with short channel lengths, a tilt may exist due to the modulation of the channel length by the depletion region surrounding the drain.

58 Regions of the JFET

• Cutoff: vGS < Vto, iD =0 2 • Triode: vGS ≥ Vto, 0 ≤ vDS< vGS- Vto, iD=K[2(vGS-Vto)vDS-vDS ] 2 • Saturation: vGS ≥ Vto and vDS ≥ vGS - Vto, iD=K(vGS-Vto) – Manufacturer’s parameter: Zero-Bias Saturation Current which is the drain current at saturation when 2 vGS = 0: IDSS= KVto • Breakdown: this region is associated with high values of vDS when the junction between gate and drain breaks down and drain current increases

very rapidly. iD

vDS 59 Device Power Considerations VSS • Static or Quiescent Power VSS – This is power consumed after the device has reached a logic 0 or logic 1. – In general, when a device is in a high state, the device is not A V conducting (i.e., open) and the output is equal to the V OH A OH V (i.e., the supply voltage). In this case, no power is A A OL consumed. – However, when a device is in a low state, the device is conducting (i.e., closed) and the output is equal to the VOL. In this case, there is (static) power being consumed. – Therefore, when designed ICs we need to understand the VSS requirements for the power supply and temperature V characteristics of the devices. SS • Dynamic Power Dissipation – Since the fan out load on a gate has a significant capacitive A component, a non-zero switching time will be experienced. A C During this period the device will dissipated power. – The power dissipated for a device being switch at a frequency f is given below and is highly dependent on f.

Q = CVSS is the charge on the capacitance when high is reached 2 E = QVSS = CVSS is the energy needed to achieve the high state as well as released well switching to the low state 2 P = fCVSS is the power dissipated during the switching periods

60 Complementary MOS CMOS • Taking NMOS (n-channel) and PMOS (p-channel) and using V =5 V them in a complementary fashion (same characteristics) such DD that the static power is always zero (there will, of course, be dynamic power dissipated). S

• Note that VGSP = vi-VDD and VGSN = vi G VDD=5 V PMOS VDD=5 V PMOS OFF PMOS ON D when vi >0 when vi = 0 and =VDD=VH vGSP = -VDD + and vGSP ≈ 0 + vo =VDD = VH But no static power G D vi NMOS vo __ __ S NMOS OFF NMOS ON when when vi = vi = vGSN=0 vGSN > 0 =VH = VDD v = 0 o Capacitance of the gates But no static power

61 Graphical Analysis i mA DN • For CMOS, the load line of 250 vGSN= vi=3 vi=2, vGSP= -3 the NMOS is the characteristic curves of the PMOS. D C 200 • Let view the operation as v v = v =2.5 v =2.5, v = -2.5 i GSN i i GSP goes from 0 to 5 V 150 • Point A: vi=0, the NMOS is cutoff since vi = vGSN < Vton ; the vGSN= vi=2 vi=3, vGSP= -2 100 E B PMOS is conducting since vGSP = vi- VDD= -VDD vGSN= vi=1.5 50 • Point B: vi=2 and is the intersection of vGSN = 2 and vGSP vGSN< Vton vi=5, vGSP= 0 < Vtop A F 0 = -3 where the NMOS is in vDSN V 0 1 2 3 4 5 saturation and the PMOS is in -5 - 4 -3 -2 -1 0 PMOS the triode region.

• Points C through D: vi=2.5 and is the intersection of vGSN = 2.5 and vGSP = -2.5 where the NMOS and the PMOS are both in saturation.

• Point E vi=3 and is the intersection of vGSN = 3 and vGSP = -2 where the NMOS is in the triode region and the PMOS is in the saturation region.

• Point F: vi=5, the NMOS is conducting but the PMOS is cutoff since vGSP< Vtop = vi-VDD= 0

62 Transfer Characteristics

6 vo A • These characteristics approach 5 B the ideal characteristics we 4 C discuss previously.

3 • For vi < Vton, vo = VDD

• For vi > VDD - |Vtop|, vo = 0 2

• The transfer characteristics fall 1 D E F abruptly at vi=VDD/2 0 0 1 2 3 4 5 6 vi

63 CMOS Inverter Truth Table

VDD=5 V

S v i NMOS PMOS v o High 1 ON OFF Low 0 Low 0 OFF ON High 1 G PMOS

+ + G D vi NMOS vo __ __ S

64 CMOS NOR and NAND GATES NOR Gate VDD

A B NA PA NB PB Nside Pside v o P 0 Low 0 Low OFF ON OFF ON OFF ON High 1 A A 0 Low 1 High OFF ON ON OFF ON OFF Low 0 1 High 0 Low ON OFF OFF ON ON OFF Low 0 1 High 1 High ON OFF ON OFF ON OFF Low 0

B P B V Nside = NA + NB DD

C = A + B PB Pside = PA• PB PA

NA NB

Nside = NA• NB A NA C = AB Pside = PA + PB NAND Gate B NB

A B NA PA NB PB Nside Pside v o 0 Low 0 Low OFF ON OFF ON OFF ON High 1 0 Low 1 High OFF ON ON OFF OFF ON High 1 1 High 0 Low ON OFF OFF ON OFF ON High 1 1 High 1 High ON OFF ON OFF ON OFF Low 0

65 +V Dynamic Logic DD

f FAB=+++()K Xφ M1 • In this circuit, only when the clock, f, is high will the output be dependent on the inputs, A, B, …X. A B X • When f is low, M1 is ON, M2 is OFF and … capacitor will be charged to VDD. • When f is high, M1 is OFF, M2 is ON, and the f M2 capacitor will discharge through the NMOS NOR Gate transistors provided that at least on of the inputs is ON.

A B X φ NA NB NX Nφ Pφ Nside Pside v o 0 Low 0 Low 0 Low 0 Low OFF OFF OFF OFF ON OFF ON High 1 0 Low 0 Low 1 High 0 Low OFF OFF ON OFF ON OFF ON High 1 0 Low 1 High 0 Low 0 Low OFF ON OFF OFF ON OFF ON High 1 0 Low 1 High 1 High 0 Low OFF ON ON OFF ON OFF ON High 1 1 High 0 Low 0 Low 0 Low ON OFF OFF OFF ON OFF ON High 1 1 High 0 Low 1 High 0 Low ON OFF ON OFF ON OFF ON High 1 1 High 1 High 0 Low 0 Low ON ON OFF OFF ON OFF ON High 1 1 High 1 High 1 High 0 Low ON ON ON OFF ON OFF ON High 1 0 Low 0 Low 0 Low 1 High OFF OFF OFF ON OFF OFF OFF High 1 0 Low 0 Low 1 High 1 High OFF OFF ON ON OFF ON OFF Low 0 0 Low 1 High 0 Low 1 High OFF ON OFF ON OFF ON OFF Low 0 0 Low 1 High 1 High 1 High OFF ON ON ON OFF ON OFF Low 0 1 High 0 Low 0 Low 1 High ON OFF OFF ON OFF ON OFF Low 0 1 High 0 Low 1 High 1 High ON OFF ON ON OFF ON OFF Low 0 1 High 1 High 0 Low 1 High ON ON OFF ON OFF ON OFF Low 0 1 High 1 High 1 High 1 High ON ON ON ON OFF ON OFF Low 0

66 +V DD One More Example • Using this design, we can design other logic f M 1 F = (AB + C + DE)φ functions. A B C D E P N φ A B C D E M2 M1 NA NB NC NC NE (NA*NB+NC+ND*NE)M2 M1 F 1 0 0 0 0 0 ON OFF OFF OFF OFF OFF OFF OFF OFF ON 1 A D 1 0 0 0 0 1 ON OFF OFF OFF OFF OFF ON OFF OFF ON 1 1 0 0 0 1 0 ON OFF OFF OFF OFF ON OFF OFF OFF ON 1 1 0 0 0 1 1 ON OFF OFF OFF OFF ON ON ON OFF OFF 0 1 0 0 1 0 0 ON OFF OFF OFF ON OFF OFF ON OFF OFF 0 C 1 0 0 1 0 1 ON OFF OFF OFF ON OFF ON ON OFF OFF 0 1 0 0 1 1 0 ON OFF OFF OFF ON ON OFF ON OFF OFF 0 1 0 0 1 1 1 ON OFF OFF OFF ON ON ON ON OFF OFF 0 B E 1 0 1 0 0 0 ON OFF OFF ON OFF OFF OFF OFF OFF ON 1 1 0 1 0 0 1 ON OFF OFF ON OFF OFF ON OFF OFF ON 1 1 0 1 0 1 0 ON OFF OFF ON OFF ON OFF OFF OFF ON 1 1 0 1 0 1 1 ON OFF OFF ON OFF ON ON ON OFF OFF 0 1 0 1 1 0 0 ON OFF OFF ON ON OFF OFF ON OFF OFF 0 1 0 1 1 0 1 ON OFF OFF ON ON OFF ON ON OFF OFF 0 1 0 1 1 1 0 ON OFF OFF ON ON ON OFF ON OFF OFF 0 f M2 1 0 1 1 1 1 ON OFF OFF ON ON ON ON ON OFF OFF 0 1 1 0 0 0 0 ON OFF ON OFF OFF OFF OFF OFF OFF ON 1 1 1 0 0 0 1 ON OFF ON OFF OFF OFF ON OFF OFF ON 1 1 1 0 0 1 0 ON OFF ON OFF OFF ON OFF OFF OFF ON 1 1 1 0 0 1 1 ON OFF ON OFF OFF ON ON ON OFF OFF 0 1 1 0 1 0 0 ON OFF ON OFF ON OFF OFF ON OFF OFF 0 1 1 0 1 0 1 ON OFF ON OFF ON OFF ON ON OFF OFF 0 1 1 0 1 1 0 ON OFF ON OFF ON ON OFF ON OFF OFF 0 1 1 0 1 1 1 ON OFF ON OFF ON ON ON ON OFF OFF 0 1 1 1 0 0 0 ON OFF ON ON OFF OFF OFF ON OFF OFF 0 1 1 1 0 0 1 ON OFF ON ON OFF OFF ON ON OFF OFF 0 1 1 1 0 1 0 ON OFF ON ON OFF ON OFF ON OFF OFF 0 1 1 1 0 1 1 ON OFF ON ON OFF ON ON ON OFF OFF 0 1 1 1 1 0 0 ON OFF ON ON ON OFF OFF ON OFF OFF 0 1 1 1 1 0 1 ON OFF ON ON ON OFF ON ON OFF OFF 0 1 1 1 1 1 0 ON OFF ON ON ON ON OFF ON OFF OFF 0 1 1 1 1 1 1 ON OFF ON ON ON ON ON ON OFF OFF 0

67 Homework • NMOS Transistors – Problems: 5.3, 5.4, 5.6 • Load-line Analysis – Problems: 5.14-17 • JFETs – Problems: 5.56, 5.57, 5.65 • CMOS – Problems: 6.48-6.50 6.69-6.70, 6.71-73