Module 2:BJT

Quote of the day "Peace cannot be kept by force. It can only be achieved by understanding”. ― Albert Einstein DC Load line and Bias Point • DC Load Line – For a a straight line drawn on transistor output characteristics. IC – For CE circuit, the load line is a graph of collector current I versus V for a fixed C CE IB + value of R and supply V C CC + VCE – Load Line? VCC  VCE  I C RC VBE - - V V  I R – From Figure VCE=? CE CC C C – If VBE =0 then IC=0,  VCE = VCC plot this point on characteristics(A).

– Now assume that ICRC = VCC, i.e. IC = VCC /RC then VCE =0. Plot this point on characteristics(B). – Join points A and B by a straight line. DC Load line contd..

VCE  VCC  I C RC

VV IC CC CE IC  RC V CC B IC(sat)  RC DC load line

VVCE(off )  CC V A CE Example 1. Plot the dc load line for the circuit shown in

Fig. Then, find the values of VCE for IC = 1, 2, 5 mA respectively.

VVIRCE CC C C

VCE  10 for I c  0

10 I  10mA c 110 3

IC (mA) VCE (V) 1 9 2 8 5 5

4 Example 2. For the circuit shown and Plot of the dc load line in Fig. find the values of IC for VCE = 0V and VCE for IC = 0.

VVIRCE CC C C

5 I C 4.54mA V CC15V For the previous circuit shown observe the Plot of the dc load line with Rc=4.8 K find the values of IC for VCE = 0V and VCE for IC = 0.

I C 3.125mA V CC15V DC Bias Point • DC Bias point or Q point

– Identifies the transistor current IC and voltage VCE when no input is applied to the base terminal of the transistor. ~Vi – When an ac signal is applied to the transistor

base, IB varies according to the instantaneous =+20 amplitude of signal. This causes IC to vary and consequently produces a variation in VCE. – Now consider the circuit . IC=1mA – Assume the Bias conditions shown in fig. i.e.

values of IB,IC & VCE. IB=20A + – What is RC=? VCE + - 10V – The 10 K load line drawn for this circuit is VBE - shown in the next slide. Fig. DC Load line for transistor with a bias point at VCE=10V and IC =1mA. The transistor may be biased to any point on the DC Load Line.

IC(mA) IB=40A 2.0 1.95 mA

IB=30A 1.6 IB=+20A Q- Point 1.2

IB=20A 0.8

IB=10A IB=-20A 0.4

I =0 V 0.05 mA B CE 0 0 4 8 12 16 20

VCE=-9.5V VCE=+9.5V 19.5V 0.5V Selection of Q point • Note the collector current swings do not exceed the limits of operation(saturation and cutoff). However, as you might already know, applying too much ac voltage to the base would result in driving the collector current into saturation or cutoff resulting in a distorted or clipped waveform. Selection of Q point Optimum Q-point with operation.

IC

IC(sat)

IB = 50 A IB IICB β

IB = 40 A

Q-Point IC(sat)/2 IB = 30 A

IB = 20 A

IB = 10 A

IB = 0 A VCE VCC/2 VCC

VVIRCE CC C C

11 Effect of Emitter resistance RE • Consider this Fig.

• In this case RE is the DC load and the output equation will be

VCC VCE  IE RE • Now consider the below fig. • Collector and emitter are both present , and total dc load in

series with transistor is(RC + RE)

VCC  VCE  I C RC  I E RE

 IC  IE

VCC VCE  IC RC  RE  Assignment questions 1) Problem 4.6 & 4.7 from David Bell exercise. 2) Draw the circuit and sketch the input and output characteristics. Also explain active region, cutoff region and saturation region by indicating them on the characteristic curve. 3) Draw the common base circuit and sketch the input and output characteristics. Also explain active region, cutoff region and saturation region by indicating them on the characteristic curve. 4) Determine the operating point for a silicon transistor biased by base bias method with β = 100, RB = 500KΩ RC = 2.5KΩ and VCC = 20V. Also draw the DC load line. Base Bias Method • Circuit operation & Analysis – The circuit arrangement shown in Fig is known as base bias and also as fixed IC current bias. – The Base current is constant and IB + determined by VCC and RB. V – From fig voltage drop across R is + CE B VBE - - VB =IBRB also VB = (VCC-VBE ) since VCC = VB +VBE . – Therefore the base current IB is

VCC VBE I B  I CQ  hFE I B RB

– You know that IC is I C   I B  can be replaced by hFE Base Bias Method contd.. V  V  I R This collector current can be used with CC CE C C V V  I R to calculate VCE. CEQ CC CQ C

• Effect of hFE(max) and hFE(min) – Practically the precise current is normally not known. – The transistor is usually identified by its type, number and maximum and minimum values of current gain that can be obtained from manufacturer’s data sheet. – In circuit analysis it is convenient to use a

typical value of hFE. Which value of hFE do I use?

Transistor specification sheet may list any combination of the following hFE: max. hFE, min. hFE, or typ. hFE. Use typical value if there is one. Otherwise, use

hFE(ave) h FE (min) h FE (max)

Consider the next example to observe the effect of maximum and minimum value of hFE

16 Example 1. The base bias circuit shown in Fig has RB =470K, RC=2.2K

1)Determine the values of VCE ,IC andIB for hFE=100. 2Calculate the maximum and minimum levels of

VCE, IC when hFE(max) =50 and hFE(min) = 200. Plot load line =+18V VCC VBE 18 0.7 I B  I B  I B  36.8A RB 470

I C I  3.68mA IC  hFE IB IC 10036.8A C

3 3 VCE VCC  IC RC VCE 18 3.6810 2.210  IB + V + CE VBE - - VCE  9.9V 17 Example 1 contd.

• For hFE(min) = 50: I 1.84mA IC  hFE IB IC  5036.8A C

3 3 VCE VCC  IC RC VCE 18 1.8410 2.210  VCE 13.95V

• For hFE(max) = 200: I  7.36mA IC  20036.8A C

3 3 VCE 18 7.3610 2.210  VCE 1.8V • Plot the DC load line and mark Q point for three

values of hFE. • Because of this uncertainty of Q point this method is rarely used. Fig. DC Load line for transistor with different hFE plotted for Example 1

IC(mA)

10

Q- Point for hFE=200

8 7.36 mA

6 Q- Point for hFE=100

3.68 mA4 Q- Point for hFE=50

1.84 mA2

VCE 0 0 2 4 6 8 10 12 14 16 18 13.95V 1.8V 9.9V Example 2. Determine the operating point for a silicon transistor biased by base bias method with

β = 100, RB = 500KΩ RC = 2.5KΩ and VCC = 20V. Also draw the DC load line.

V V 20 0.7 =+20V I  CC BE B I B  3 I B  38.6A RB 50010

I C I  3.86mA IC  hFE IB IC 10038.6A C

3 3 VCE VCC  IC RC VCE  20 3.8610 2.510  IB + VCE + VBE - - VCE 10.35V 20 Example 2.

V 20 I  CC   8mA IC c(sat) 3 Rc 2.510

VCC I c(sat)  8mA IC(sat)  RC Q- Point 3.86mA

VVCE(off )  CC = 20V

VCE 10.35V Base bias characteristics.

Circuit recognition: A single

(RB) between the base terminal and VCC. No emitter resistor.

Advantage: Circuit simplicity. Disadvantage: Q-point shift with temp. Applications: Switching circuits only.

22 Base bias characteristics. (2)

Load line equations:

VCC I c(sat)  Rc

VCE(OFF )  VCC

Q-point equations:

VCC VBE I B  RB

I CQ  hFE I B

VCEQ  VCC  I CQ RC

23 Design of Base bias circuit To design the circuit means to compute the values of resistors RB and RC for the required specifications i.e. (ICQ,VCEQ and available hFE)

Design equations:

I CQ  hFE I B

VCC VBE RB  I B

VCC VCEQ RC  I CQ

24 Example 3. Design a base bias circuit as in fig below to have

β = 100, VCE = 7 V, IC = 5mA and VCC = 20V.

3 I C 510 =+20V I  B I B   I B  50A hFE 100

V V 20  0.7 IC CC BE RB  RB  6 I B 5010

 RB  386K IB + VCE Use 390KΩ standard value + VBE - - VCC VCE 20  7 RC  RC  3 I C 510

RC  2.6K

Use 2.2K standard value 25 Voltage Divider method • Voltage-divider bias is the most widely used type of bias circuit. Only one power supply is needed and voltage-divider bias is more + + V stable(less variation with ) + + CE - V - than other bias types. For BE + VC this reason it will be the VB primary focus for study. VE - - - Voltage Divider method • It is seen from the fig that along with the resistor

RC there is an emitter resistor RE connected in series with transistor. • Therefore the total load in series with transistor

is(RC + RE), and this must be used when drawing the DC load line.

• Resistors R1 and R2 constitute a voltage divider that divides the voltage VCC to produce base voltage VB

• I2 is much larger than IB so VB is largely unaffected by IB. Voltage Divider method (approx. analysis) • Writing the equation looking from O/P of the circuit

VCC VCE  IC RC  IE RE

VCE VCC  IC RC  IE RE + +  I  I C E V + + CE - V  V  I R  R  V - CE CC C C E BE + VC V • We can also write VCEQ as B VE VCE  VC VE - - • Both equations can be used -

to find VCEQ. Example 1 Analyze the voltage-divider bias circuit shown in fig to determine the emitter voltage, collector voltage and collector-emitter voltage .

3 VCC  R2 181210 VB  VB  3  4.8V R1  R2 331210

VE VB VBE VE  4.8 0.7  4.1V

VB VBE 4.1 I E   4.1mA I E  3 RE 110

VCE VCC  IC RC  RE  IC  IE  4.1mA

3 3 VCE 18 4.110 1.2 110  8.98V

VCE VC VE VC VCE VE

VC  8.98 4.1 13.08V Example 2 Analyze the voltage-divider bias circuit shown in fig to determine the emitter voltage, collector voltage and collector- emitter voltage. Also draw Dc load line and mark Q point.

3 VCC  R2 151210 V  VB  3  5.294V B 22 1210 R1  R2 V  5.294  0.7  4.594V VE VB VBE E

VB VBE 4.594 I   2.088mA E I E  3 RE 2.210

VCE VCC  IC RC  RE   I C  I E  2.088mA

3 3 VCE 15 2.08810 2.7  2.210  4.7688V

VCE VC VE VC VCE VE

VC  4.7688  4.594  9.3628V Fig. DC Load line for transistor with different hFE plotted for Example 2 V I  CC  3.061mA C(sat) VCE(off ) VCC 15V RC  RE

IC(mA)

5

4 3.061 mA 3 Q- Point

2.08 mA 2

1

VCE 0 0 2 4 6 8 10 12 14 16 18 4.76V 15V Voltage Divider method (Exact analysis) To analyze voltage divider circuit precisely, the voltage divider must be replaced by its Thevenin equivalent circuit (VT in series with RT)as illustrated below . R  R VCC  R2 1 2 V  RT  R1 || R2  Where T and R  R R1  R2 1 2

Thevenin equivalent circuit

+ IB V + CE + - V - RT BE V  R + V  CC 2 V T T - R1  R2 . - Voltage Divider method (Exact analysis) Now writing the equation around the base & emitter terminals

VT  I B RT VBE  RE I E

VT  IBRT VBE  RE IC  IB  + VT  I B RT VBE  RE hFE IB  I B 

VT  I B RT VBE  IB RE hFE 1 VC VT VBE I B  RT  RE hFE 1 - VCE VCC  IC RC  IE RE

VCE VC VE VC VCE VE DC load line for voltage divider bias Load lone points can be obtained from output

equation VCE VCC  IC RC  IE RE IC I B  VCE VCC  IC RC IC  IB RE hFE

 I   C  VCE VCC  IC RC  IC  RE  hFE   1    VCE VCC  IC RC  IC 1 RE  hFE    1     VCE VCC  IC RC  RE 1  V  h  CC   FE  IC  1 h   FE  RC  RE   VCE  VCC  hFE  IC 0 VCE 0 Example 3 Exactly analyze the voltage-divider bias circuit shown

in fig to determine the IC ,emitter voltage, collector voltage and collector-emitter voltage when hFE=100. Solution: First we should find Thevenin equivalent voltage and resistance

V  R 3 V  CC 2 181210 T VT  3 R1  R2 331210

VT  4.8V

R1  R2 RT  R1 || R2  R1  R2 33103 12103 R  RT  8.8K T 3312103 The Thevenin equivalent circuit with voltage and

resistance is shown below. Now to find IB we have V V 4.8  0.7 I  T BE B I B  3 3  37.3A RT  RE hFE 1 8.810 110 1001 I  h I I 10037.3106  3.73mA Thevenin C FE B C equivalent circuit IE  IC  IB I E  3.73mA  37.3A 1.2K + I E  3.76mA VE  I E RE IB V 3 3 V  3.77V + CE VE  3.7710 110 E - VBE - V V  I R V V V 8.8K C CC C C C CE E 4.8V 1K . VC 183.731.2 VCE VC VE

VC 13.52V VCE 13.523.77 VCE  9.75V Dc load line for example 3

VCE  VCC 18V Load line points for hFE=100 IC 0 V CC 18 I C  I   8.145mA 1 h  C  FE  3 3 1100  RC  RE 1.210 110  h     FE   100  12 IC(mA)

10 8.145 mA 8

6 Q- Point 3.73 mA4

2

VCE 0 0 2 4 6 8 10 12 14 16 18 9.75V 15V Repeat the example with hFE=50 and hFE=200. Now for hFE=50. V V 4.8  0.7 T BE  68.56A I B  I B  3 3 RT  RE hFE 1 8.810 110 50 1 I  h I I  5068.5610 6  3.428mA Thevenin C FE B C equivalent I  3.428mA  68.56A circuit IE  IC  IB E 1.2K + I E  3.49mA VE  I E RE IB VCE 3 3 V  3.428V + VE  3.42810 110 E - VBE - V V  I R V V V 8.8K C CC C C C CE E 4.8V 1K . VC  18  3.4281.2 VCE VC VE

VC  13.884V VCE  13.884  3.428 VCE  10.426V Plot load line and see the variations Now for hFE=200.

V V 4.8  0.7 T BE 19.54A I B  I B  3 3 RT  RE hFE 1 8.810 110 200 1 I  h I I  20019.5410 6  3.91mA Thevenin C FE B C equivalent  I  3.91mA 19.54A circuit IE  IC  IB E 1.2K + I E  3.93mA VE  I E RE IB VCE 3 3 V  3.91V + VE  3.9110 110 E - VBE - V V  I R V V V 8.8K C CC C C C CE E 4.8V 1K . VC  18  3.911.2 VCE VC VE

V  13.308V V  9.398V C VCE  13.308  3.91 CE Plot load line and see the variations Dc load line for example 3 Load line points for hFE=100,50,200 VCC I  8.145mA I  8.11mA I  C,hFE 100 C,hFE 50 C 1 h  R  R  FE  C E   I C,h  8.163mA VCE  VCC 18V  hFE  FE 200 IC 0 12 IC(mA)

10 8.145 mA 8

Q- Point, hFE=200 6

Q- Point, hFE=100 Q- Point, h =50 3.73 mA4 FE

2

VCE 0 0 2 4 6 8 10 12 14 16 18 9.75V 15V Voltage divider bias characteristics

Approx. analysis Exact analysis Load Line equations: Load Line equations: V VCC CC I  IC(sat)  C(sat) R  R 1 h  C E R   FE R C  h  E VCE(off )  VCC  FE  V V Q-point equations: CE(off ) CC Q-point equations: VCC  R2 VB  VT VBE R1  R2 I  B R  R h 1 V V T E FE B BE I  I I  h I I E  CQ E CQ FE B RE I E  I c  I B V  V  I R  R CEQ CC CQ  C E  VCEQ  VCC  I C RC  I E RE 42 Design of Voltage Divider method • To design the circuit means to compute the

values of resistors R1, R2, RE and RC for the required specifications + + V i.e. (I ,V ,V ,V + + CE CQ CEQ CC E - VBE - and available hFE) + VC • We have VB VE V V  I R  I R CC CE CQ C E E - - -

VCC  R2 VB  VE VBE VB  R1  R2 VB  I 2 R2 VE  I E RE Design equations for voltage divider method

V  I R • Better rule to select • Use E E E where I = 10I I = 0.1I I  I OR I  I 1 1 CQ 2 2 CQ E C E c  hFE  • Then R2 can be V R  E computed from I2. E I E

VB  I 2  R2 • Voltage across RC VB  VE VBE V V V V • Use the equation Rc CC CE E below for getting R 1 I C RC  VCC VCE VE

VCC  R2 R2 VCC VB  VB  R1  VCC VCE VE R1  R2 VB RC  I C Example 4 Design the voltage-divider bias circuit to operate from

a 12 V supply with collector-emitter voltage 3V, VE=5V and IC=1mA, when VBE=0.7V.

• Better rule to select IC=10I2 I2=0.1mA

• Then R2 can be computed from I2.

V B  I 2  R 2 VB  VE VBE V B  5  0 . 7  5 . 7 V

VB 5.7  R 2  57K  R2   3 I 2 0.110

V CC  R 2 • Use this equation for getting R1 V B  R 1  R 2

3 R2 VCC VB  5710 12 5 . 7  R1  R1   R 1  63K  VB 5 . 7 Example 4

V V  I R E I  I OR I  I 1 1 • Use E E E RE  E C E c  hFE  I E 5 I  1mA  h is not provided R   R  5K E FE E 110 3 E

V V V V • Voltage across RC Rc CC CE E

VCC VCE VE I C RC  VCC VCE VE RC  I C

12 35 R  C 110 3

 RC  4K Assignment questions 1.With a neat circuit diagram explain the fixed Bias circuit.

2.In Voltage Divider Bias circuit, VCC=15V, R1=22K, R2=12K, RE=2.2K, RC=2.7K & hFE=50 . Calculate the values of IC,VE, Vc and VCE. Also draw DC load line and mark the Q- point. Assume VBE=0.7V. 3.Explain the approximate analysis of voltage divider bias circuit. Assignment questions on transducers • Explain the working of LVDT. Explain briefly strain gauges. • Explain i) Hall Effect ii) Seebeck Effect iii) Peltier Effect. • Design an adder circuit using an op-amp to obtain

an output voltage of V0 = 2[0.1V1+0.5V2+2V3], where V1,V2 and V3 are input . Draw the circuit diagram.

First implement adder V0  0.1V1  0.5V2  2V3 

Then implement inverting amplifier to get V0=-2V01

V01

ADDER Inverting amplifier with

RF=2R1 i.e. gain 2