EE 462: Laboratory Assignment 5 Biasing N- channel MOSFET Transistor

by Dr. A.V. Radun and Dr. K.D. Donohue (2/21/07) Updated Spring 2008 by Stephen Maloney Department of Electrical and Computer Engineering University of Kentucky Lexington, KY 40506

I. Instructional Objectives • Analyze the metal oxide semiconductor (MOS) field effect transistor (FET) (MOSFET) using a DC load line • Design a circuit to set a DC operating point for a MOSFET • Measure the operating points in a DC biased FET circuit • Become more familiar with programming in LabVIEW (See Horenstein 5.2, 7.3.1, and 7.3.3)

II. Background

Transistors are nonlinear devices; however, over certain operating regions they can be approximated with linear models. To ensure a transistor operates in its linear region, a DC level is added to its input signal. The design of this DC level is referred to as biasing the transistor. The DC current and voltage values are referred to as the transistor’s DC operating point (or its bias point) (or its quiescent point). Once a transistor is biased in a linear region, small changes for the input currents and voltages around the bias point will cause the outputs to change in a linearly proportional manner (approximately). It is assumed that the variation of the transistor's currents and voltages are small enough such that they do not move the system into nonlinear operation regions (triode region or cutoff).

The simplest common source MOSFET amplifier biasing scheme is shown in Fig. 1. Since only the DC operating point is of interest right now, the time varying part of the input signal is omitted. The actual signal would be an AC signal added to the VGG (Gate to Ground DC signal). The transfer characteristic (output as a function of the input) for this circuit can be derived. Apply KVL in Fig. 1 to obtain:

Vout = VDD − RDID , (1)

then using a relationship between ID and the gate voltage VGG when the MOSFET is in the saturated (forward active) region, Eq. (1) becomes:

K p 2 K p Vout = VDD − RD ()VGG − Vtr where = K (2) 2 2 (Horrenstein uses K and Spice uses Kp).

and Vtr is the threshold voltage between the cutoff and triode operation region.

+ ID RD

D VDD R + G G

Vout - VGG S -

Fig. 1 Basic common source amplifier biasing.

The operating points of VGG and Vout are the DC or quiescent values at the input and output, respectively. Ideally, for a certain value of VGG, Vout should always result in a corresponding value that does not change. However this relationship will change due to temperature variations or manufacturing variability. Unfortunately the MOSFET's transconductance parameter Kp cannot be controlled well during manufacturing. In addition, Kp also varies with temperature. Some transistor’s Kp can vary by more than a factor of 3. Note that Kp is not directly specified in the data sheet but rather the transconductance gm is specified. The relationship between the MOSFET’s transconductance gm and Kp will be addressed in future labs. Since Kp varies significantly, a circuit biased correctly for one transistor may not be biased correctly for another transistor, even for one with the same manufacture and part number. Therefore, a more robust biasing scheme than the one shown in Fig. 1 is needed, such that the MOSFET's quiescent operating point is less sensitive to changes in Kp.

Insensitivity of the MOSFET's quiescent operating point can be achieved by adding a resistor RS into the source branch of the circuit as shown in the Fig. 2. An analysis of this new circuit, similar to before, results in the following equations:

VGG = VGS + I D RS (3)

K K p p I = ()V − V 2 = ()V − I R − V 2 = D 2 GS tr 2 GG D S tr (4)

K K p p 2 2 ()()V − V 2 − K R V − V I + R I 2 GG tr p S GG tr D 2 S D Note that Eq. (4) can be manipulated into a quadratic for drain current ID

⎛ 2()V −V 2 ⎞ (V −V )2 I 2 ⎜ GG tr ⎟I GG tr 0 (5) D − + 2 D + 2 = ⎜ RS ⎟ ⎝ RS K p ⎠ RS

ID RD +

D + R VDD G G

Vout VGG S -

RS -

Fig. 2 Basic common source amplifier with reduced Kp sensitivity.

2 Notice in Eq. (5) that when RS goes to zero (multiply through by RS and take limit as RS go to zero), Eq. (5) simplifies to:

K p I = ()V −V 2 (6) D 2 GS tr

which is the same relationship for the circuit in Fig. 1. (Why should this be expected?) One the other hand, if the RS is large (relative to 2), then Eq. (5) can be approximated by:

2()V −V ()V −V 2 I 2 − GG tr I + GG tr = 0 (7) D D 2 RS RS

Notice that in Eq. (5), Kp only appeared in one term, whose effect was minimized (relative to the other terms) by a large RS value. The quadratic in Eq. (7) is a perfect square and can be rewritten as:

2 ⎛ V −V ⎞ V −V () or ( GG tr ) (8) ⎜ I − GG tr ⎟ = 0 I = ⎜ D R ⎟ D R ⎝ S ⎠ S

Thus if RSKp is large, ID is practically independent of Kp as desired. The general solution for ID valid for any Kp is:

2 ⎛ ⎞ ⎛ ⎞ 2 ⎜ ()V − V 1 ⎟ ⎜ ()V − V 1 ⎟ ()V − V (9) I = ⎜ GG tr + ⎟ − ⎜ GG tr + ⎟ − GG tr D R 2 R 2 2 ⎜ S R K ⎟ ⎜ S R K ⎟ R ⎝ S p ⎠ ⎝ S p ⎠ S

From Eq. (9), the approximation of Eq. (8) can also be obtained by letting Rs get large (limit as Rs approaches infinity).

The circuit of Fig. 2 is still not most efficient because it requires two DC power supplies: one for VGG and another for VDD. The circuit in Fig. 3 remedies this. The Thévenin equivalent for the circuit consisting of VDD, R1, and R2 in Fig. 3 gives the biasing circuit in Fig. 2 where VGG = Vth and RG = Rth. With these Thévenin equivalents substituted into the circuit, the circuit is identical to the circuit in Fig. 2 with the exception that the bias voltage VGG is now dependent on VDD. The VGG voltage is now controlled by the proper choice of R1 and R2. This eliminates the need for a separate power supply to control VGG. The gate current into the MOSFET is zero so the gate voltage is thus determined by only VDD and the R1 and R2 voltage divider.

ID RD +

R 1 D

+ VDD G

Vout S R 2 - RS -

Fig. 3 Basic common source amplifier biasing with reduced Kp sensitivity and employing a single DC voltage.

The DC Operating point of this circuit is stable for two primary reasons: • The gate voltage is determined only by the voltage divider R1 and R2, since insignificant current flows into the transistor gate, and is therefore independent of the transistor parameters (especially Kp). • The source resistor RS stabilizes the DC operating point through negative feedback. If Kp increases for any reason, such as temperature change, the subsequent rise in source current increases the voltage drop across RS, thereby increasing VS and thus decreasing VGS (since the gate voltage VGG is constant). The decrease in VGS will counteract the attempted increase in IS (≈ID).

III. Pre-Laboratory Exercise

The MOSFET you will be using in the lab is the ZVN3306A with a Kp (in SPICE) specified at 0.1233 A / V2 (it can be as small as a third of this value) and the nominal value of the threshold voltage is Vtr = 1.8. But you have already estimated these values in Lab 2. Therefore use the values you estimated for computing the circuit parameters in the pre-lab exercises. You are to use RD = 1000 Ω, RS = 470 Ω, and VDD= 12 V. Note that you must use Matlab to solve some of the pre-lab problems.

Setting Transistor Quiescent Point 1. Derive the equation for the DC load line for the MOSFET circuit in Fig. 3 (with R1, R2 and the source resistor RS used for added circuit stability) by relating the current ID to the variables VDD, VDS, RD, and RS (Kirchhoff’s voltage law). Be sure to sketch the circuit and the ID vs. VDS graph, which should contain sketched curves and a sketch of the load line, with end points labeled symbolically (no numbers are required on the sketch or in the equation derived above). For an example of these kind of curves see Figure 6.9 on page 323 in Horenstein. 2. Determine the quiescent operating point IDQ and VDSQ such that it is at the midpoint of the DC load line (to enhance the likelihood of a symmetrical output voltage swing). Determine voltage drops over RS and RD at this design point. 3. Write a program in Matlab to plot the DC load line superimposed with the characteristic curves (ID versus VDS) of the N-channel MOSFET for an arbitrary value of VGS. Use m-files from lab lecture to help with this part. Modify your program to determine a value of VGS iteratively, so the intersection of the characteristic curve and load line is close to the desired operating point. Hand in a printout of the program (with comments), a plot of the load line and characteristic curve at the determined VGS value, and indicate the value of VGS (you can include this value in the title of the graph or simply handwrite it on the plot with clear indication of what it is). 4. Plot the drain characteristic curves measured in Lab 2 with the load line. Does this graph suggest a similar value of VGS as in the previous problem? (You will have to use a rough estimation based on an interpolation between the measured traces to determine what VGS results in a trace close to your desire quiescent point). Discuss the similarities or differences in the number you obtained. Decide which is more accurate. 5. For the quiescent drain-source voltages and current computed in the previous problems, use Eq. (6) to compute the gate to source voltage (VGS) at the designed quiescent operating point, and use Eq. (8) to compute the gate-to-ground voltage (VGG) (same as voltage across R2). Compare and comment on this value of VGS relative to the value you found by iteration in previous problems. 6. Determine the ratio between R1 and R2 that will result in the VGG value of the last problem and maintain this operating point. In addition, determine actual values for R1 and R2 that will also result in IR1 = IDQ/100.

Effects of Kp Variations 7. Use the quiescent VGG computed in the previous problem to compute the resulting operating point (IDQ and VDSQ) for the cases when Kp is 1/2 and 1/3 its design value (using Eq. (9)).

SPICE Simulation 8. Create a SPICE model for the circuit in Fig. 3 with the values given above and your computed R1 and R2. Use the MOSFET ZVN3306A model and change the Kp and Vtr values to values estimated in Lab 2. Perform a SPICE operating point analysis to determine the voltage from the drain to the ground and the drain current. Then use SPICE operating point analysis to determine the drain source voltage (VDSQ) and the drain current (IDQ) when Kp has been decreased to 1/2 and 1/3 of its design value.

IV. Laboratory Exercise

1. Measure quiescent points: Construct the MOSFET common source amplifier (Fig. 3) using the Pre-lab values for R1, R2, RS, RD and VDD. Measure the circuit's quiescent operating point by measuring VDSQ, the exact value of RD and the voltage across RD or RS in order to calculate IDQ. Measure the quiescent operating point using the multi- meter on the DC settings. (Discussion: Compare these values with those predicted in the pre-lab exercises)

2. Observe effect of increasing power supply voltage: Increase VDD to 15 V and measure the circuit’s quiescent operating point as in the previous procedure. (Discussion: How did the quiescent operating point change and how did the circuit’s load line change? Is this what you would have expected? Did the circuit's quiescent operating point stay at the midpoint of the load line? Explain.)