EXAMENSARBETE INOM TEKNIKOMRÅDET ELEKTROTEKNIK OCH HUVUDOMRÅDET TEKNISK FYSIK, AVANCERAD NIVÅ, 30 HP STOCKHOLM, SVERIGE 2017 Fabrication and characterization of gate last Si MOSFETs with SiGe source and drain BJÖRN CHRISTENSEN KTH SKOLAN FÖR INFORMATIONS- OCH KOMMUNIKATIONSTEKNIK Abstract The continuous evolution of digital technology we enjoy today is the result of ever shrinking, faster and cheaper transistors that make up the ubiquitous integrated circuits of our devices. Over the decades, the industry has gone from purely geometrical scaling to innovative solutions like high-k dielectrics combined with metal gates and FinFETs. A possible future is the use of high mobility materials such as Germanium for the active areas of a transistor instead of Silicon. As a step towards building devices on Ge, we characterize a gate last process with epitaxial deposition of Si0.75Ge0.25 source and drain areas on bulk Si wafers. Devices fabricated are proof-of-concept PMOSFETs and NMOSFETs with channel widths of 10 µm and 40 µm and channel lengths between 0.6 µm and 50 µm. The gate electrode of the fabricated devices is in- situ doped polycrystalline Silicon. The devices are electrically characterized through I-V measurements and exhibit a yield of 95%. Keywords MOSFET fabrication, gate last, SiGe source and drain, IDP gate, epitaxy. Abstract Den konstanta utvecklingen av digital teknik som vi åtnjuter idag drivs av den ständiga utvecklingen av transistorer. Dessa blir mer kompakta, snabbare och kostar mindre för varje generation och bygger upp de integrerade kretsar som driver all vår vardagsteknik. Under ett tidsspann på flera decennier har krympningen gått från enbart geometrisk skalning till mer innovativa lösningar. Gate-oxiden har gått från rent kiseldioxid till material med lägre relativ permittivitet vilket möjliggjort en tunnare ekvivalent elektrisk tjocklek än vad som varit möjligt för kiseloxid. FinFet eller så kallade ’tri-gate’ transistorer har ersatt den plana varianten för att öka den ledande arean utan att enheterna sväller ut över substratet. En framtida möjlighet är även att använda material med högre mobilitet för elektroner och hål än kisel där en möjlig kandidat är Germanium. Som ett steg mot målet at bygga Germanium-transistorer tillverkar vi här gate last transistorer med source och drain i in-situ dopad kisel-germanium. Dessa konceptenheter används för att definiera och utveckla tillverkningsprocessen och tillverkas i flera omgångar. Varje skiva innehåller transistorer med en bredd på 40 µm och 10 µm. Kanallängden på transistorerna går mellan 0.6 µm och 50 µm för båda bredderna och av varje enhet finns 101 stycken per kiselskiva (100 mm diameter). Gate-elektroden består i samtliga fall av in-situ dopat poly-kristallint kisel. Enheterna karaktäriseras därefter genom elektriska mätningar och mätdata analyseras och sammanställs. Det visas genom dessa mätningar att ett utfall om över 95% fungerande enheter kan uppnås med processen. Nyckelord MOSFET fabrication, gate last, SiGe source and drain, IDP gate, epitaxy. Acknowledgements I would like to extend my sincere and heartfelt thanks to Professor Mikael Östling for providing this research opportunity, Associate Professor Per-Erik Hellström for his supervision and Konstantinos Garidis for his invaluable guidance throughout the project. I would also like to thank Associate Professor Gunnar Malm, Christian Ridder, Laura Zurauskaite, Ganesh Jayakumar, Mattias Ekström and Ahmad Abedin at ICT for stimulating discussions, problem solving and shared frustration over tool breakdowns. Table of Contents 1 Introduction ............................................................................................................ 1 1.1 Historical scaling and some modern-day comparisons ................................. 1 1.2 More than Moore ...................................................................................................... 3 1.3 Purpose ....................................................................................................................... 3 1.4 Goal ............................................................................................................................... 4 1.4.1 Why gate last? ................................................................................................................................. 4 1.4.2 Why SiGe? ......................................................................................................................................... 5 1.4.3 Benefits .............................................................................................................................................. 5 1.5 Delimitations ............................................................................................................. 5 1.6 Outline ......................................................................................................................... 6 2 Semiconductor and transistor theory ............................................................. 7 2.1 Semiconductor theory ............................................................................................. 7 2.2 MOSFET function ...................................................................................................... 8 2.3 Examples of MOSFET operation............................................................................ 8 2.3.1 OFF-state ........................................................................................................................................... 9 2.3.2 Depletion ........................................................................................................................................... 9 2.3.3 Inversion/ON-state ................................................................................................................... 10 2.3.4 Leakage ........................................................................................................................................... 10 2.4 MOSFET I-V characteristics .................................................................................. 11 2.4.1 Threshold voltage, Vt................................................................................................................ 11 2.4.1.1 Calculation of threshold voltage ................................................................................... 12 2.4.2 ON-current .................................................................................................................................... 12 2.4.2.1 Linear region Vd < Vg - Vtm......................................................................................... 12 2.4.2.2 Parabolic region Vd > Vg - Vtm .................................................................................. 13 2.4.2.3 Subthreshold behavior ....................................................................................................... 13 2.4.3 OFF-current .................................................................................................................................. 13 2.4.4 DIBL .................................................................................................................................................. 13 3 Methods for semiconductor fabrication and characterization .............. 14 3.1 Lithography .............................................................................................................. 14 3.1.1 Resist ................................................................................................................................................ 14 3.1.2 Exposure ......................................................................................................................................... 14 3.1.3 Development ................................................................................................................................ 15 3.1.4 Bake .................................................................................................................................................. 15 3.2 CVD ............................................................................................................................. 15 3.2.1 Plasma enhanced chemical vapor deposition (PECVD) ......................................... 16 3.2.2 Atomic layer deposition (ALD) ........................................................................................... 17 3.3 Epitaxy ....................................................................................................................... 17 3.3.1 Homoepitaxy ................................................................................................................................ 17 3.3.2 Heteroepitaxy .............................................................................................................................. 17 3.3.3 Vapor phase epitaxy (VPE) ................................................................................................... 18 3.3.4 Selectivity ....................................................................................................................................... 18 3.4 Physical vapor deposition (PVD) ....................................................................... 19 3.5 Dry etching ............................................................................................................... 20 3.6 Wet etching............................................................................................................... 20 3.7 Thermal