Master thesis 2009
A Guideline for Material Design of Gate Oxide in Further Scaled MOSFET ~Improvement of electrical properties by
CeO2/La2O3 stack structure~
Supervisor
Professor Hiroshi Iwai
Department of Electronics and Applied Physics
Interdisciplinary Graduate School of Science and Engineering
Tokyo Institute of Technology
07M36123
Miyuki Kouda
1 CONTENTS
Chapter 1 Introduction…………………………………………………1 1.1 Background of This Study…………………………………………………...2 1.2 Scaling Method………………………………………………………...……3
1.3 Scaling Limits of Traditional SiO2 Gate Dielectric………………………..4 1.4 Requirements for High-k Dielectric Gate Insulator………………………6
1.5 Fixed Charges in La2O3……………………………………………………..9 1.6 The Method for Charge Reduction…………………………….…………12 1.7 Propose of This Work…………………………………………………...…14
Chapter 2 Fabrication and Characterization Methods…….……….15 2.1 Experimental Procedure ………………………………………………….16 2.1.1 Fabrication Procedure for nMOS Capacitors………………………………16 2.1.2 Fabrication Procedure for nMOSFETs………………………………….….17 2.1.3 Silicon Surface Cleaning Process ………………………………….………..18 2.1.4 Electron-Beam Evaporation Method………………………………………..19 2.1.5 Rapid Thermal Annealing (RTA) Method …………………...……………..20 2.2 Measurement Methods…………………………………………………….21 2.2.1 Capacitance-Voltage(C-V) Measurement…………………………..………21 2.2.2 Gate Leakage Current – Voltage (J-V) Characteristics…………………...25 2.2.2.1 Schottky Effect….……………………………………………25 2.2.2.2 Poole-Frenkel Effect………………………...……………….27 2.2.2.3 Fowler-Nordheim Tunneling Effect…………………………30 2.2.2.4 Image-force Effect…...... 31 2.2.3 Threshold Voltage…………………………………………………………….32 2.2.4 Subthreshold Slope…………………………………….……………………..33 2.2.5 Mobility Extraction Technique ~Split C-V Measurement~………………..34 2.2.6 Charge Pumping methods…………………………………………………....37 2.2.7 XPS Measurement……………………………………………...…………….40
Chapter 3 Characteristics of MOS Capacitor…………………………42 3.1 Introduction…………………………………………….………………….43 3.2 Analysis of Leakage Current…………………………………………….43
2 3.2.1 Leakage Mechanism of Each Layered Capacitors…………………………43
3.2.1.1 CeOX Single Layered Capacitor …………………….…….43
3.2.1.2 La2O3 Single Layered Capacitor ……………………………..45 3.2.1.3 Stack Structured Layer………………………………………46 3.2.1.4 Conclusion……………………………………………………..49 3.2.2 Leakage current value………………………………………………………..50 3.2.2.1 The Trap Density in Film……………………………………..50 3.2.2.2 Compared Leakage Current Value………………………….51 3.2.2.3 Conclusion……………………………………………………..53 3.3 Fixed Charge in Dielectric Film…………………………………… ……………54 3.3.1 Calculation Method of Fixed Charge………………………………..………54 3.3.2 Quantifying Fixed Charge in Each Film …………………………….……57
3.3.3 Comparison of the Each Qit …………………………………………………59
3.3.4 Change of Vfb Value …………………………………………………….……62
3.3.5 Physical Thickness-Related Vfb Values Rapidly Change ……………….…63 3.3.6 Conclusion……………………………………………………………….……64
Chapter 4 Characteristic of MOSFET………………………….……65 4.1 Introduction………………………………………………………..………66
4.2 Drain current (Id) - Drain voltage (Vd) characteristics…………...……..66 4.3 The Effective Mobility ……………………………………………….……68 4.4 Characterization of Interface States by Charage Pumping Method……68 4.5 Consideration of Film Structure…………………………………………..70 4.6 Conclusion…………………………………………………………….……72
Chapter 5 Analysis of Theoretical Calculation…………..…………..73 5.1 Introductions……………………………………………………………….74 5.2 First-principles rationale …………………………………………………74 5.3 Density-Functional Theory (DFT)………………………………..………75 5.4 Local Density Approximations (LDA) …………………………………...76 5.5 Charge Defects Calculation…………………………………….…………78 5.5.1 Formation Energy …………………………………………………………..79
5.5.2 Concentration of Charge Defects in La2O3……………………..………….82 5.5.3 Expansion into the Other Materials………………………………………..86 5.6 The Decision of Sample Structure Used Oxygen Potential Diagram….88
3 5.7 Conclusion………………………………………………………………...89
Chapter 6 Conclusion……………………………………………...... 90 6.1 Results of This Study……………………………………………………..….91 6.2 Furture Works……………………………………………...………….…….92
References……………………………………………………………..…93
Acknowledgement……………………………………………………….95
4
Chapter 1 Introduction
1.1 Background of This Study 1.2 Scaling Method
1.3 Scaling Limits of Traditional SiO2 Gate Dielectric 1.4 Requirements for High-k Dielectric Gate Insulator
1.5 Fixed Charges in La2O3 1.6 The Method for Charge Reduction 1.7 Propose of This Work
5 1.1 Background of This Work
Today, the modern human society are becoming affluent for high technology electric products such as personal computer, mobile phones, video game machines, digital cameras, and human-like robot. These products are used various ultra-large-scale integration (ULSI). The Metal-Oxide-Semiconductor Field Effect Transistors
(MOSFETs) are the basic building block of the current ULSI integrated circuits (ICs).
The performance of silicon ULSI depends on the capability of the MOSFET, especially the processing speed and electrical power dissipation which are hanged on the geometrical size of MOSFET.
Gordon Moore who is one of the founder of Intel Corporation, predicted that exponential growth in the number of transistors per integrated circuit and predicted this trend would continue, in a popular article written in 1965[1]. Figure1.1 shows Moore’s original prediction. His prediction is popularly known as “Moore’s Law”. Moore’s Law states that the number of transistors on integrated circuits doubles approximately every 24 months, resulting in higher performance at lower cost. This simple statement is the foundation of semiconductor and computing industries. It is the basis for the exponential growth of computing power, component integration that has stimulated the emergence of generation after generation of PCs and intelligent devices. As a practical matter, figure1.2 shows that the number of transistors on the intel’s Central Processing Unit (CPU), with the first microprocessor, 4004, to the recent Pentium R 4 microprocessor. The total number of transistors on microprocessor was increased double every 18-24 months. It was applied well to the Moore’s Law. [2]
6 1.2 Scaling Method
The downsizing has been accomplished by the scaling method. In this method, horizontal and vertical dimensions such as oxide thickness and supply voltage are decreased by the factor S, but Si-substrate impurity doping density is increased by the factor S.
W
W/S tox
tox/S N L N D D L/S ND*S N *S N A A
Fig.1.1 Scaling method
Table. 1.1 Scaling of MOSFET by a scaling factor of S. Quantity Before After scaling scaling Channel length L L’ = L/S Channel width W W’ = W/S Device area A A’ = A/S2
Gate oxide thickness tox tox’ = tox/S
Gate capacitance per Cox Cox’ = S*Cox unit area
Junction depth xj xj’ = xj/S
Power supply voltage VDD VDD’ =
VDD/S
Threshold voltage VT0 VT0’ = VT0/S
Doping densities NA NA’ = S*NA
ND ND’ = S*ND
7 1.3 Scaling Limits of Traditional SiO2 Gate Dielectric
As mentioned in the previous section, the MOS transistors, which are main part of
LSI system, must be miniaturized to obtain better performance and bring down costs.
And the gate dielectric, which separates the gate electrode from carrier passage, must also be thinner following the scaling law. Silicon dioxide (SiO2) has been used for transistor gate dielectrics for nearly 30 years because SiO2 is compatible with silicon substrate:
SiO2 formed perfect gate dielectric material for silicon. For three decade, SiO2 has successfully scaled from a thickness of 100 nm 30 years ago to a mere 1.2nm at the present. However, as transistor geometries scale to the point where the traditional SiO2 gate dielectric film becomes just a few atomic layers thick, direct tunneling current leakage and the resulting increase in power dissipation and heat become critical issues.
This direct tunneling current leakage is proportional to the equation as follow.
I ∝ exp{-(mφ)·D} (1.1)
Whrer, m: electron effective mass,φ:barrier height, D:physical thickness of gate oxide.
This equation indicates that the thicker gate dielectric film becomes, the lower gate tunneling current. Conversely, if a thickness of gate dielectric film becomes thinner, the gate tunneling current leakage increases. Figure 1.2 shows the relationships between gate leakage current density and EOT (Equivalent Oxide Thickness). The gate leakage current
2 density reaches 600 [A/cm ] as a thickness of SiO2 thins down to 1nm. Furthermore, the gate leakage current becomes 1 [kA/cm2] in the case of 0.8nm. As shown in table 1.2,
EOT value in high performance logic technology will get 1nm in 2007. Consequently,
SiO2 as a gate oxide film reaches its limit so that new materials for gate dielectrics are required to continue geometrical scaling down of MOS transistors. Figure 1.2: The
8 relationships between the gate leakage current density and EOT. Gate leakage current continues to increase as far as SiO2 is used for gate dielectric.
Fig.1.2 The relationships between the gate leakage current density and EOT.
Gate leakage current continues to increase as far as SiO2 is used for gate dielectric.
Table 1.2 ITRS 2007 up date
Year of Production 2005 2007 2010 2014 2018
Physical Gate Length 32 25 18 11 7 (nm) EOT (nm) 1.1 0.9 0.7 0.6 0.5
Gate Leakage 5.20*102 5.20*102 5.20*103 5.20*103 5.20*104 Current Density (A/cm2)
9 1.4 Requirements for High-k Dielectric Gate Insulator
The replacing SiO2 to high-k material for gate insulator is good solution to decrease tunnel leakage current.
The direct-tunneling leakage current (JDT) flowing through a gate insulator film is determined by the tunneling probability of carrier. The tunneling probability of carrier
(DDT) is shown in below equation where physical thickness of insulator (d), electron effective mass in the gate insulator film (m*) and barrier height of insulator (φb).
1 4 d( 2m * ) 2 J D exp{ b } DT DT h
Relationship between physical thickness of SiO2 (dEOT) and physical thickness of high-k gate insulator (d) obtained by the same gate capacitance value (C) is shown in below equation where dielectric constant of SiO2 (εox) and high-k gate insulator
(εhigh-k). C high k ox d d EOT