Bicmos Logic Gates

BiCMOS Logic Gates

University of Connecticut 224 BiCMOS - Best of Both Worlds?

n CMOS circuitry exhibits very low power dissipation, but n Bipolar logic achieves higher speed and current drive capability.

n BiCMOS achieves low standby dissipation like CMOS, but high speed and current drive capability like TTL and ECL.

n The disadvantage of BiCMOS is fabrication complexity (up to 30 masking steps, compared to about 20 for bipolar logic or CMOS). This translates into higher cost and longer design cycles. $

n Notable examples of the BiCMOS technology are the Intel P6 (a.k.a. Pentium Pro) which appeared in 1996, and its successor the P7. University of Connecticut 225 BiCMOS Inverter

VDD n P1 and N1 perform the logic function. P1 n QP and QO are low- Q P impedance output drivers. N3 n N2 and N3 remove base charge from the bipolar

VOUT transistors during switching.

VIN N1 QO

University of Connecticut 226 BiCMOS Inverter

VDD VIN = 0.

QP N3

VOUT

VIN N1 VIN = VDD. QO

University of Connecticut 227 BiCMOS Inverter VTC

VOUT • The BiCMOS inverter shown CMOS 3.0 here exhibits reduced logic swing (VDD - 2VBEA) compared to CMOS (VDD). BiCMOS • Reduction of the supply 2.0 voltage will make this problem more severe.

1.0 VDD = 3.3V 2 K = 40m A / V VT = 1V

b F = 50 VBEA = 0.7V 0.0 0.0 1.0 2.0 3.0

VIN

University of Connecticut 228 BiCMOS NAND Gate

VDD With both inputs high:

PA PB

NB3

NA3

VOUT With VA high, VB low: V B NB1

VA NA1 QO

University of Connecticut 229 How Fast is BICMOS?

n For highly-capacitive off-chip V DD loads, fast switching is possible due to the high current driving

P1 capability of the bipolar

QP transistors. The speed is limited by the parasitic capacitances of N3 the QP, which must be driven by the P1 - N3 CMOS circuit. VOUT n For on-chip loads presenting very VIN N1 little capacitance, BiCMOS offers QO no advantage if C < C N2 L BCP n BiCMOS integrated circuits are really CMOS on the inside!

University of Connecticut 230 BiCMOS Applications

n Modern BiCMOS, invented by Intel, hit the market in 1992. n Ever-increasing clock frequencies on motherboards of PC’s and workstations may require that the VLSI / ULSI chips be made in BiCMOS. (Witness the Intel, AMD, and Cyrix mP chips.) n Central Processing Units (CPU’s) of “minisupercomputers” can be implemented in BiCMOS, with packing density and dissipation advantages over ECL. (e.g., the Cray Research “Baby Cray” J916 Computer) n TTL will soldier on in motherboard SSI and MSI applications, where BiCMOS does not boast an advantage.

n But … the BiCMOS party may be over when supply voltages drop below 1.8 V. BJT’s have a fixed turn-on voltage; MOSFET thresholds can be reduced to at least 0.3V for room temperature operation. University of Connecticut 231 The Problem with BiCMOS

n For standard BiCMOS, the logic swing is VDD - 2VBEA. n Supply voltages are continually being reduced, because

2 P » C LVDD

n When VDD is reduced to 1.8V, standard BiCMOS will provide a logic swing of only 0.4V; this isn’t acceptable! We can provide shunt elements which increase the voltage swing of BiCMOS, but … n Turning off the BJT’s isn’t the answer! If the supply voltage is 1.8V, the BJT’s can only conduct for

0.7V £ VOUT £ 1.1V

n In this case the BJT’s can not effectively boost the switching speed. University of Connecticut 232 Full-Rail BiCMOS Inverter w/ Resistive Shunts

VDD • This BiCMOS design provides a rail-to-rail voltage swing.

• For VOUT < VBEA, N1 and R2 P1 conduct, bringing VOL all the way to QP 0.

R1 • For VBEA < VOUT < VDD - VBEA, one VOUT or both BJT’s conducts.

• For VDD - VBEA < VOUT, P1 and R1 conduct, bringing VOH all the way to VIN N1 V . Q DD O • It is not practical to fabricate this R2 circuit with resistors, but a similar circuit can be made using an active

shunt for QO.

University of Connecticut 233 BiCMOS Inverter w/ Active Shunt

VDD • This BiCMOS design provides a voltage swing of VDD - VBEA. • For VOUT < VBEA, N3 and N2 P1 conduct, bringing VOL all the way to QP 0.

• For VBEA < VOUT < VDD - VBEA, one VOUT or both BJT’s conducts.

N3 • The base-emitter junction of QP is not shunted, so VOH = VDD - VBEA. VIN N1 QO

University of Connecticut 234 Full Rail BiCMOS Inverter w/ Paralleled CMOS Output

VDD • The parallel CMOS

PO inverter provides rail-to-rail operation. P1 • For VOUT < VBEA, NO QP conducts, bringing VOL all N3 the way to 0.

• For VBEA < VOUT < VDD - VOUT VBEA, one or both BJT’s conducts. VIN N1 • For VDD - VBEA < VOUT, PO QO conducts, bringing VOH all N2 the way to VDD.

University of Connecticut 235 Buffered CMOS

University of Connecticut 236 CMOS - Single Stage

tOX =100 Angstroms VDD = 1.8V ' 2 VT = -0.6V kP = 80m A/V 2.2m m/ 0.5m m V V OUT ' 2 IN kN = 200m A/V VT = 0.6V 0.9m m/ 0.5m m CL

tP =

A =

University of Connecticut 237 CMOS - Single Stage / 50pF

VDD = 1.8V V = -0.6V T KP = 2.2m m/ 0.5m m VOUT VIN KN = VT = 0.6V 0.9m m/ 0.5m m 50pF

tP =

University of Connecticut 238 CMOS - Three Stages / 50pF

VDD = 1.8V

2.2/ 0.5 11/ 0.5 55/ 0.5 VOUT VIN 0.9/ 0.5 4.5/ 0.5 22/ 0.5 50pF

K1 = K2 = K3 =

CL1 = CL2 = CL3 =

tP1 = tP2 = tP3 =

tP =

University of Connecticut 239 CMOS - Six Stages / 50pF

VDD = 1.8V

2.2/ 0.5 11/ 0.5 55/ 0.5

VIN WIRED 0.9/ 0.5 4.5/ 0.5 22/ 0.5 TO THE NEXT PAGE!

K1 = K2 = K3 =

CL1 = CL2 = CL3 =

tP1 = tP2 = tP3 =

University of Connecticut 240 CMOS - Six Stages / 50pF

VDD = 1.8V

275/ 0.5 1375/ 0.5 6875/ 0.5 VOUT

WIRED FROM THE 110/ 0.5 550/ 0.5 2750/ 0.5 50pF PREVIOUS PAGE! K = K = K4 = 5 6 C = C = CL4 = L5 L6 t = t = tP4 = P5 P6

tP =

University of Connecticut 241 GaAs Direct-Coupled FET Logic (DCFL)

University of Connecticut 242 DCFL Inverter

• DCFL gates are similar to NMOS circuits, but are implemented with GaAs MESFET’s rather than Si MOSFET’s. VDD • The advantage of DCFL is speed - it is up to 3 times faster than CMOS. • The disadvantages of DCFL are fabrication complexity and cost. VOUT • GaAs 75 mm wafer - $100

VIN • Si 200 mm wafer - $10 • Si 300 mm wafers - coming soon! • GaAs technology is less established compared to Si technology, and the fabrication of enhancement type MESFET’s is difficult.

University of Connecticut 243 DCFL Inverter - Basic Operation

VIN = LOW.

VDD

VOUT V IN NO VIN = HIGH.

University of Connecticut 244 DCFL NOR Gate

VA = VB = VOL.

VDD

VOUT VA = VDD or VB = VDD. VA V NOA B NOB

DCFL NAND gates are not practical due to restrictions imposed on VDD, VOL, and the enhancement device threshold voltages.

University of Connecticut 245 Buffered DCFL NOR Gate

VDD

VOUT

VA VB VA VB

The added source follower provides a low-impedance output driver for off-chip loads.

University of Connecticut 246 DCFL Characteristics

Compare the 1999 state-of-the art for GaAs DCFL and Si CMOS:

GaAs DCFL vs. Si CMOS: 0.25 mm technology

GaAs DCFL Si CMOS

propagation delay 35 ps 75 ps

dissipation 30 mW (DC) 1 mW / MHz

SRAM embedded in VLSI 32 kB 128 kB

• GaAs exhibits higher electron mobility than Si. • Due to the GaAs electron velocity characteristic, DCFL can operate at a reduced supply voltage without a penalty in switching speed. University of Connecticut 247 DCFL Applications

n For a given minimum linewidth, GaAs DCFL circuitry is about 2 to 3 times faster than Si CMOS because of the difference in electron mobilities. n The extra speed comes at a premium, because GaAs technology is less developed and DCFL is expensive. n DCFL applications are at the high end, where the extra cost can be justified. Examples are the Cray Y-MP and the Vitesse Semiconductor GaAs microprocessor, which boasts 1.2 M transistors [see Ira Deyhimy, “Gallium Arsenide Joins the Giants,” IEEE Spectrum, pp. 33-40, February 1995]. n At the present time, the area of fastest growth for GaAs DCFL is communications. n A factor of three isn’t much, though, when you consider the rapid advancement of Si CMOS / BiCMOS technology.

University of Connecticut 248