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SOI-CMOS Device Technology Yasuhiro FUKUDA*, Shuji ITO**, Masahiro ITO**

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SOI-CMOS Device Technology Yasuhiro FUKUDA*, Shuji ITO**, Masahiro ITO** Special Edition on 21st Century Solutions Special Edition on 21st Century Solutions SOI-CMOS Device Technology Yasuhiro FUKUDA*, Shuji ITO**, Masahiro ITO** Abstract In recent years, the mobile communication market represented by the mobile telephone has been showing remarkable growth. This market has been making tough demands for semiconductor integrated circuits, which are mounted components, to consume less power, have higher integration, have multi-function capability, and be faster. We at Oki have been working on developing complete depletion type SOI devices in order to meet these needs. We have already implemented 0.35 ␮m and 0.2 ␮m SOI-CMOS devices1. This article explains SOI-CMOS device technology and discusses current developments. SOI Device Structure 1. A low operating voltage is possible since the threshold voltage (Vt) can be set low without increasing the off- The term SOI means Silicon On Insulator structure, which leak current. (Reduced S value) consists of devices on silicon thin film (SOI layers) that 2. Development of high-speed, low power consumption exists on insulating film. Figure 1 illustrates an outline CMOS devices is possible since the load capacitance CL sketch of bulk, partial depletion type and complete deple- is reduced. (Reduced junction capacitance) tion type SOI-MOS (Metal Oxide Semiconductor) tran- 3. Reduced signal transmission loss during high-speed sistor structure. In the case of bulk CMOS devices, P/N operation. (Reduced junction capacitance) type MOS transistors are isolated from the well layer. In 4. Realizing high-frequency component performance, in- contrast, SOI-CMOS devices are separated into Si sup- cluding passive devices, is possible since high-resistance porting substrate and buried oxide film (BOX). Also, these Si wafers can be used as supporting substrates. (Totally devices are structured so each element is completely iso- isolated structure) lated by LOCOS (Local Oxidation of Silicon) oxide film 5. Reduced operation errors such as cross talk via the and the operating elements area (called the SOI layer) is substrate. (Totally isolated structure) completely isolated by insulators. Also, elements that have 6. It is possible to prevent operation errors including latch a thin SOI layer (normally <50 nm) and have all body areas up phenomena. (Totally isolated structure) under the channel depleted, are called complete depletion type SOI. Conversely, elements that have a thick SOI layer Source (P-) Gate Drain (P-) (normally >100 nm) and have some areas at the bottom of Gate LOCOS the body area that are not depleted, are called partial Oxide Film depletion type SOI. N- N- Characteristics of SOI-CMOS Devices N Well As indicated below in Table 1, the S value that indicates the sub-threshold characteristics is unique in that only the S Si Substrate (P type) Depletion Layer value of complete depletion type SOI transistors is the low Bulk CMOS Structure value of 60 - 70 mV/dec. (The S value is the gate voltage at Source (P-) Gate Drain (P-) Source (P-) Drain (P-) the sub-threshold area that changes the drain current by one LOCOS Gate digit with the drain voltage held constant.) Also, as illus- Oxide Film LOCOS trated in Figure 1, the source, drain, substrate, and the PN Oxide Film junction formed between wells in bulk transistors do not Body Body exist as complete depletion type transistors. Also, the junc- tion capacity is very small. Since a PN junction exists at the Buried Oxide Film (BOX) Buried Oxide Film (BOX) bottom of the body in partial depletion type transistors, it Depletion Layer Depletion Layer is located exactly between them. The advantages of the S value, reduced junction capacitance, and the totally iso- Si Supporting Substrate (P type) Si Supporting Substrate (P type) lated structure are as follows. Partial Depletion Type SOI Complete Depletion Type SOI Transistor Transistor * Silicon Solutions Company, VLSI R&D Center, Advanced VLSI Device/Process R&D Dept.-1, General Manager Figure 1: Comparison Between Bulk CMOS and ** Silicon Solutions Company, VLSI R&D Center, AdvancedVLSI Device/Process R&D SOI-CMOS Structures Dept.-1, SOI Circuit R&D Team-2, Team Leader 54 March 2001 OKI Technical Review 185 Vol. 68 L=0.20mm W=10.0mm Minimum Operating Cycle Time 1.E-02 (Normalization: Tcyc = 1/Bulk: Vcc = 2.5 V) Vd=-2.0V Vd=2.0V Comparative Evaluation Using 1.E-04 m] Same Mask µ 1.8 A/ Pc Nc µ 1.E-06 Bulk 1.4 1.E-08 SOI 70mv/dec Drain Current: Id[ 1.E-10 -70mv/dec 1.0 1.E-12 -2.0 -1.0 0.0 1.0 2.0 0.6 Gate Voltage: Vg[V] 0.51.5 2.5 Power Supply Voltage: Vcc(V) Figure 2: 0.2 µm SOI Transistor Sub-threshold Characteristics Figure 3: Power Supply Voltage Dependency of Minimum Processor Operating Cycle Time 7. Improved soft error durability by injecting radiation. (SOI layer thin film) In this photograph, it is possible to confirm that the SOI layer Since we are considering expanding into the mobile is very thin by using the gate metal as a comparison. We communication market, we are aiming to develop one-chip developed the advanced fabrication technology and process low power consumption CMOS-LSI with combined analog technology that makes this possible. and digital logic. We have therefore adopted complete depletion type SOI structure transistors as our develop- Expansion into Digital Devices ment of low power consumption devices that use the low S value to make low power operation possible. On the other We will verify the fundamental characteristics that would hand, the following issues accompany complete isolation or result if we use this transistor in a digital CMOS device. thin-film SOI layers. Figure 3 compares the power supply voltage dependency of 1. Source drain withstand voltage reduced by parasitic the minimum operating cycle time for a processor manufac- bipolar transistor operation (floating body potential tured using this process with that of an equivalent device. effect due to complete isolation) Compared to bulk CMOS devices, SOI-CMOS devices can 2. Increased transistor parasitic resistance (thin-film SOI have reduced power supply voltage while maintaining oper- layer) ating performance, and can greatly reduce power consump- 3. Reduced tolerance to electrostatic discharge (ESD) (thin- tion. The reduction of junction capacitance in SOI struc- film SOI layer) ture transistors prominently appears as a performance com- Next we would like to introduce the performance of 0.2 parison. We have already developed low power consump- ␮m SIO-CMOS devices we developed using complete depletion type SIO structure transistors to overcome these issues and take advantage of the previously mentioned advantages. 0.2␮m SOI-CMOS Device Development We developed 0.2 ␮m SOI-CMOS devices by stipulating the Gate Metal power supply voltage specifications to be 1.8 V. In consider- Embedded Contact ation of the complete depletion type transistor characteristics and the current wafer variations, we specified 50 nm as the Thin SOI Film SOI layer thickness. We decided to employ the Co (Cobalt) Layer Silicide structure since we found that it is the most stable 2 means of reducing transistor parasitic resistance. Figure 2 BOX Film illustrates the transistor sub-threshold characteristics. This P Type figure illustrates the characteristics of complete depletion Supporting type SOI transistors when both P and N type MOS transistors Substrate have a threshold voltage of 0.25 V, and the S value becomes 70 mV/dec. Photograph 1 shows a transistor cross-section. Photograph 1: Cross-section Photograph 55 Special Edition on 21st Century Solutions Bulk CMOS SOI CMOS Transistor 0.0 Partial Complete Transistor Depletion Type Depletion Type -0.5 SOI S Value (mV/dec) 80 to 90 80 to 90 60 to 70 -1.0 Junction Capacitance 1 0.1 to 1 0.1 (Relative Value) -1.5 -2.0 Parasitic Thyrister Yes No No Structure Bulk -2.5 Table 1: Transistor Performance Comparison -3.0 Transfer Coefficient: s21 (dB) Transfer tion 256 kb SRAM using the above characteristics and will -3.5 expand it as mixed logic components. 123456 Frequency (GHz) Expansion into High-frequency Devices Figure 5: Frequency Dependency of SPDT Switch Transfer Coefficient Using the advantages of reduced junction capacitance and completely isolated structure, we are studying how to apply and expand into high-frequency devices used in communica- 10 tion LSIs. Next, we would like to discuss SOI-CMOS device High-resistance Substrate performance as an RF (Radio Frequency) circuit component 8 (>1K⍀cm) that is required to operate at high frequencies. Figure 4 illustrates a fundamental RF circuit block. The SPDT (Single 6 Pole Double Throw) switch functions to separate transmis- sion from reception and is required to reduce signal transmis- 4 Normal Substrate sion loss as much as possible. Figure 5 illustrates the frequency (20-30⍀cm) dependency of the SPDT switch transfer coefficient in SOI/ 2 bulk MOS transistors. Since the junction capacity is small Imag(Zin)/Real(Zin) Q Value with SOI, it is possible to minimize signal transmission loss 0 even in high-frequency areas. Also, in the case of RF circuits, 012345678 many passive devices such as inductors and capacitors are used (GHz) for impedance matching and frequency selection. There is much signal loss with normal Si substrates due to the high Figure 6: Q Value Frequency Dependency conductivity. The Q value of passive devices manufactured on with Spiral Inductor this substrate decreases. Figure 6 illustrates the Q value frequency dependency when a spiral inductor is manufac- complete isolation structure, it is possible to use a high- tured on a Si substrate with a different resistance via an resistance substrate as the supporting substrate. It is also equivalent insulating film.
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