CCD and CMOS Sensor Technology Technical White Paper Table of Contents
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Discrete Cosine Transform Based Image Fusion Techniques VPS Naidu MSDF Lab, FMCD, National Aerospace Laboratories, Bangalore, INDIA E.Mail: [email protected]
View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by NAL-IR Journal of Communication, Navigation and Signal Processing (January 2012) Vol. 1, No. 1, pp. 35-45 Discrete Cosine Transform based Image Fusion Techniques VPS Naidu MSDF Lab, FMCD, National Aerospace Laboratories, Bangalore, INDIA E.mail: [email protected] Abstract: Six different types of image fusion algorithms based on 1 discrete cosine transform (DCT) were developed and their , k 1 0 performance was evaluated. Fusion performance is not good while N Where (k ) 1 and using the algorithms with block size less than 8x8 and also the block 1 2 size equivalent to the image size itself. DCTe and DCTmx based , 1 k 1 N 1 1 image fusion algorithms performed well. These algorithms are very N 1 simple and might be suitable for real time applications. 1 , k 0 Keywords: DCT, Contrast measure, Image fusion 2 N 2 (k 1 ) I. INTRODUCTION 2 , 1 k 2 N 2 1 Off late, different image fusion algorithms have been developed N 2 to merge the multiple images into a single image that contain all useful information. Pixel averaging of the source images k 1 & k 2 discrete frequency variables (n1 , n 2 ) pixel index (the images to be fused) is the simplest image fusion technique and it often produces undesirable side effects in the fused image Similarly, the 2D inverse discrete cosine transform is defined including reduced contrast. To overcome this side effects many as: researchers have developed multi resolution [1-3], multi scale [4,5] and statistical signal processing [6,7] based image fusion x(n1 , n 2 ) (k 1 ) (k 2 ) N 1 N 1 techniques. -
Invention of Digital Photograph
Invention of Digital photograph Digital photography uses cameras containing arrays of electronic photodetectors to capture images focused by a lens, as opposed to an exposure on photographic film. The captured images are digitized and stored as a computer file ready for further digital processing, viewing, electronic publishing, or digital printing. Until the advent of such technology, photographs were made by exposing light sensitive photographic film and paper, which was processed in liquid chemical solutions to develop and stabilize the image. Digital photographs are typically created solely by computer-based photoelectric and mechanical techniques, without wet bath chemical processing. The first consumer digital cameras were marketed in the late 1990s.[1] Professionals gravitated to digital slowly, and were won over when their professional work required using digital files to fulfill the demands of employers and/or clients, for faster turn- around than conventional methods would allow.[2] Starting around 2000, digital cameras were incorporated in cell phones and in the following years, cell phone cameras became widespread, particularly due to their connectivity to social media websites and email. Since 2010, the digital point-and-shoot and DSLR formats have also seen competition from the mirrorless digital camera format, which typically provides better image quality than the point-and-shoot or cell phone formats but comes in a smaller size and shape than the typical DSLR. Many mirrorless cameras accept interchangeable lenses and have advanced features through an electronic viewfinder, which replaces the through-the-lens finder image of the SLR format. While digital photography has only relatively recently become mainstream, the late 20th century saw many small developments leading to its creation. -
Hybrid Memristor–CMOS Implementation of Combinational Logic Based on X-MRL †
electronics Article Hybrid Memristor–CMOS Implementation of Combinational Logic Based on X-MRL † Khaled Alhaj Ali 1,* , Mostafa Rizk 1,2,3 , Amer Baghdadi 1 , Jean-Philippe Diguet 4 and Jalal Jomaah 3 1 IMT Atlantique, Lab-STICC CNRS, UMR, 29238 Brest, France; [email protected] (M.R.); [email protected] (A.B.) 2 Lebanese International University, School of Engineering, Block F 146404 Mazraa, Beirut 146404, Lebanon 3 Faculty of Sciences, Lebanese University, Beirut 6573, Lebanon; [email protected] 4 IRL CROSSING CNRS, Adelaide 5005, Australia; [email protected] * Correspondence: [email protected] † This paper is an extended version of our paper published in IEEE International Conference on Electronics, Circuits and Systems (ICECS) , 27–29 November 2019, as Ali, K.A.; Rizk, M.; Baghdadi, A.; Diguet, J.P.; Jomaah, J. “MRL Crossbar-Based Full Adder Design”. Abstract: A great deal of effort has recently been devoted to extending the usage of memristor technology from memory to computing. Memristor-based logic design is an emerging concept that targets efficient computing systems. Several logic families have evolved, each with different attributes. Memristor Ratioed Logic (MRL) has been recently introduced as a hybrid memristor–CMOS logic family. MRL requires an efficient design strategy that takes into consideration the implementation phase. This paper presents a novel MRL-based crossbar design: X-MRL. The proposed structure combines the density and scalability attributes of memristive crossbar arrays and the opportunity of their implementation at the top of CMOS layer. The evaluation of the proposed approach is performed through the design of an X-MRL-based full adder. -
Three-Dimensional Integrated Circuit Design: EDA, Design And
Integrated Circuits and Systems Series Editor Anantha Chandrakasan, Massachusetts Institute of Technology Cambridge, Massachusetts For other titles published in this series, go to http://www.springer.com/series/7236 Yuan Xie · Jason Cong · Sachin Sapatnekar Editors Three-Dimensional Integrated Circuit Design EDA, Design and Microarchitectures 123 Editors Yuan Xie Jason Cong Department of Computer Science and Department of Computer Science Engineering University of California, Los Angeles Pennsylvania State University [email protected] [email protected] Sachin Sapatnekar Department of Electrical and Computer Engineering University of Minnesota [email protected] ISBN 978-1-4419-0783-7 e-ISBN 978-1-4419-0784-4 DOI 10.1007/978-1-4419-0784-4 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2009939282 © Springer Science+Business Media, LLC 2010 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com) Foreword We live in a time of great change. -
Temperature Compensation Circuit for ISFET Sensor
Journal of Low Power Electronics and Applications Article Temperature Compensation Circuit for ISFET Sensor Ahmed Gaddour 1,2,* , Wael Dghais 2,3, Belgacem Hamdi 2,3 and Mounir Ben Ali 3,4 1 National Engineering School of Monastir (ENIM), University of Monastir, Monastir 5000, Tunisia 2 Electronics and Microelectronics Laboratory, LR99ES30, Faculty of Sciences of Monastir, University of Monastir, Monastir 5000, Tunisia; [email protected] (W.D.); [email protected] (B.H.) 3 Higher Institute of Applied Sciences and Technology of Sousse (ISSATSo), University of Sousse, Sousse 4003, Tunisia; [email protected] 4 Nanomaterials, Microsystems for Health, Environment and Energy Laboratory, LR16CRMN01, Centre for Research on Microelectronics and Nanotechnology, Sousse 4034, Tunisia * Correspondence: [email protected]; Tel.: +216-50998008 Received: 3 November 2019; Accepted: 21 December 2019; Published: 4 January 2020 Abstract: PH measurements are widely used in agriculture, biomedical engineering, the food industry, environmental studies, etc. Several healthcare and biomedical research studies have reported that all aqueous samples have their pH tested at some point in their lifecycle for evaluation of the diagnosis of diseases or susceptibility, wound healing, cellular internalization, etc. The ion-sensitive field effect transistor (ISFET) is capable of pH measurements. Such use of the ISFET has become popular, as it allows sensing, preprocessing, and computational circuitry to be encapsulated on a single chip, enabling miniaturization and portability. However, the extracted data from the sensor have been affected by the variation of the temperature. This paper presents a new integrated circuit that can enhance the immunity of ion-sensitive field effect transistors (ISFET) against the temperature. -
LDMOS for Improved Performance
> Submitted to IEEE Transactions on Electron Devices < Final MS # 8011B 1 Extended-p+ Stepped Gate (ESG) LDMOS for Improved Performance M. Jagadesh Kumar, Senior Member, IEEE and Radhakrishnan Sithanandam Abstract—In this paper, we propose a new Extended-p+ Stepped Gate (ESG) thin film SOI LDMOS with an extended-p+ region beneath the source and a stepped gate structure in the drift region of the LDMOS. The hole current generated due to impact ionization is now collected from an n+p+ junction instead of an n+p junction thus delaying the parasitic BJT action. The stepped gate structure enhances RESURF in the drift region, and minimizes the gate-drain capacitance. Based on two- dimensional simulation results, we show that the ESG LDMOS exhibits approximately 63% improvement in breakdown voltage, 38% improvement in on-resistance, 11% improvement in peak transconductance, 18% improvement in switching speed and 63% reduction in gate-drain charge density compared with the conventional LDMOS with a field plate. Index Terms—LDMOS, silicon on insulator (SOI), breakdown voltage, transconductance, on- resistance, gate charge I. INTRODUCTION ATERALLY double diffused metal oxide semiconductor (LDMOS) on SOI substrate is a promising Ltechnology for RF power amplifiers and wireless applications [1-5]. In the recent past, developing high voltage thin film LDMOS has gained importance due to the possibility of its integration with low power CMOS devices and heterogeneous microsystems [6]. But realization of high voltage devices in thin film SOI is challenging because floating body effects affect the breakdown characteristics. Often, body contacts are included to remove the floating body effects in RF devices [7]. -
A High Full Well Capacity CMOS Image Sensor for Space Applications
sensors Article A High Full Well Capacity CMOS Image Sensor for Space Applications Woo-Tae Kim 1 , Cheonwi Park 1, Hyunkeun Lee 1 , Ilseop Lee 2 and Byung-Geun Lee 1,* 1 School of Electrical Engineering and Computer Science, Gwangju Institute of Science and Technology, Gwangju 61005, Korea; [email protected] (W.-T.K.); [email protected] (C.P.); [email protected] (H.L.) 2 Korea Aerospace Research Institute, Daejeon 34133, Korea; [email protected] * Correspondence: [email protected]; Tel.: +82-62-715-3231 Received: 24 January 2019; Accepted: 26 March 2019; Published: 28 March 2019 Abstract: This paper presents a high full well capacity (FWC) CMOS image sensor (CIS) for space applications. The proposed pixel design effectively increases the FWC without inducing overflow of photo-generated charge in a limited pixel area. An MOS capacitor is integrated in a pixel and accumulated charges in a photodiode are transferred to the in-pixel capacitor multiple times depending on the maximum incident light intensity. In addition, the modulation transfer function (MTF) and radiation damage effect on the pixel, which are especially important for space applications, are studied and analyzed through fabrication of the CIS. The CIS was fabricated using a 0.11 µm 1-poly 4-metal CIS process to demonstrate the proposed techniques and pixel design. A measured FWC of 103,448 electrons and MTF improvement of 300% are achieved with 6.5 µm pixel pitch. Keywords: CMOS image sensors; wide dynamic range; multiple charge transfer; space applications; radiation damage effects 1. Introduction Imaging devices are essential components in the space environment for a range of applications including earth observation, star trackers on satellites, lander and rover cameras [1]. -
Lecture Notes 3 Charge-Coupled Devices (Ccds) – Part II • CCD
Lecture Notes 3 Charge-Coupled Devices (CCDs) { Part II • CCD array architectures and pixel layout ◦ One-dimensional CCD array ◦ Two-dimensional CCD array • Smear • Readout circuits • Anti-blooming, electronic shuttering, charge reset operation • Window of interest, pixel binning • Pinned photodiode EE 392B: CCDs{Part II 3-1 One-Dimensional (Linear) CCD Operation A. Theuwissen, \Solid State Imaging with Charge-Coupled Devices," Kluwer (1995) EE 392B: CCDs{Part II 3-2 • A line of photodiodes or photogates is used for photodetection • After integration, charge from the entire row is transferred in parallel to the horizontal CCD (HCCD) through transfer gates • New integration period begins while charge packets are transferred through the HCCD (serial transfer) to the output readout circuit (to be discussed later) • The scene can be mechanically scanned at a speed commensurate with the pixel size in the vertical direction to obtain 2D imaging • Applications: scanners, scan-and-print photocopiers, fax machines, barcode readers, silver halide film digitization, DNA sequencing • Advantages: low cost (small chip size) EE 392B: CCDs{Part II 3-3 Two-Dimensional (Area) CCD • Frame transfer CCD (FT-CCD) ◦ Full frame CCD • Interline transfer CCD (IL-CCD) • Frame-interline transfer CCD (FIT-CCD) • Time-delay-and-integration CCD (TDI-CCD) EE 392B: CCDs{Part II 3-4 Frame Transfer CCD Light−sensitive CCD array Frame−store CCD array Amplifier Output Horizontal CCD Integration Vertical shift Operation Vertical shift Horizotal shift Time EE 392B: CCDs{Part II 3-5 Pixel Layout { FT-CCD D. N. Nichols, W. Chang, B. C. Burkey, E. G. Stevens, E. A. Trabka, D. -
Advanced MOSFET Structures and Processes for Sub-7 Nm CMOS Technologies
Advanced MOSFET Structures and Processes for Sub-7 nm CMOS Technologies By Peng Zheng A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Engineering - Electrical Engineering and Computer Sciences in the Graduate Division of the University of California, Berkeley Committee in charge: Professor Tsu-Jae King Liu, Chair Professor Laura Waller Professor Costas J. Spanos Professor Junqiao Wu Spring 2016 © Copyright 2016 Peng Zheng All rights reserved Abstract Advanced MOSFET Structures and Processes for Sub-7 nm CMOS Technologies by Peng Zheng Doctor of Philosophy in Engineering - Electrical Engineering and Computer Sciences University of California, Berkeley Professor Tsu-Jae King Liu, Chair The remarkable proliferation of information and communication technology (ICT) – which has had dramatic economic and social impact in our society – has been enabled by the steady advancement of integrated circuit (IC) technology following Moore’s Law, which states that the number of components (transistors) on an IC “chip” doubles every two years. Increasing the number of transistors on a chip provides for lower manufacturing cost per component and improved system performance. The virtuous cycle of IC technology advancement (higher transistor density lower cost / better performance semiconductor market growth technology advancement higher transistor density etc.) has been sustained for 50 years. Semiconductor industry experts predict that the pace of increasing transistor density will slow down dramatically in the sub-20 nm (minimum half-pitch) regime. Innovations in transistor design and fabrication processes are needed to address this issue. The FinFET structure has been widely adopted at the 14/16 nm generation of CMOS technology. -
CMOS Active Pixel Image Sensors for Highly Integrated Imaging Systems
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 2, FEBRUARY 1997 187 CMOS Active Pixel Image Sensors for Highly Integrated Imaging Systems Sunetra K. Mendis, Member, IEEE, Sabrina E. Kemeny, Member, IEEE, Russell C. Gee, Member, IEEE, Bedabrata Pain, Member, IEEE, Craig O. Staller, Quiesup Kim, Member, IEEE, and Eric R. Fossum, Senior Member, IEEE Abstract—A family of CMOS-based active pixel image sensors Charge-coupled devices (CCD’s) are currently the dominant (APS’s) that are inherently compatible with the integration of on- technology for image sensors. CCD arrays with high fill-factor, chip signal processing circuitry is reported. The image sensors small pixel sizes, and large formats have been achieved and were fabricated using commercially available 2-"m CMOS pro- cesses and both p-well and n-well implementations were explored. some signal processing operations have been demonstrated The arrays feature random access, 5-V operation and transistor- with charge-domain circuits [1]–[3]. However, CCD’s cannot transistor logic (TTL) compatible control signals. Methods of be easily integrated with CMOS circuits due to additional on-chip suppression of fixed pattern noise to less than 0.1% fabrication complexity and increased cost. Also, CCD’s are saturation are demonstrated. The baseline design achieved a pixel high capacitance devices so that on-chip CMOS drive electron- size of 40 "m 40 "m with 26% fill-factor. Array sizes of 28 28 elements and 128 128 elements have been fabricated and ics would dissipate prohibitively high power levels for large characterized. Typical output conversion gain is 3.7 "V/e for the area arrays (2–3 W). -
Physical Structure of CMOS Integrated Circuits
Physical Structure of CMOS Integrated Circuits Dae Hyun Kim EECS Washington State University References • John P. Uyemura, “Introduction to VLSI Circuits and Systems,” 2002. – Chapter 3 • Neil H. Weste and David M. Harris, “CMOS VLSI Design: A Circuits and Systems Perspective,” 2011. – Chapter 1 Goal • Understand the physical structure of CMOS integrated circuits (ICs) Logical vs. Physical • Logical structure • Physical structure Source: http://www.vlsi-expert.com/2014/11/cmos-layout-design.html Integrated Circuit Layers • Semiconductor – Transistors (active elements) • Conductor – Metal (interconnect) • Wire • Via • Insulator – Separators Integrated Circuit Layers • Silicon substrate, insulator, and two wires (3D view) Substrate • Side view Metal 1 layer Insulator Substrate • Top view Integrated Circuit Layers • Two metal layers separated by insulator (side view) Metal 2 layer Via 12 (connecting M1 and M2) Insulator Metal 1 layer Insulator Substrate • Top view Connected Not connected Integrated Circuit Layers Integrated Circuit Layers • Signal transfer speed is affected by the interconnect resistance and capacitance. – Resistance ↑ => Signal delay ↑ – Capacitance ↑ => Signal delay ↑ Integrated Circuit Layers • Resistance – = = = Direction of • : sheet resistance (constant) current flows ∙ ∙ • : resistivity (= , : conductivity) 1 – Material property (constant) – Unit: • : thickess (constant) Ω ∙ • : width (variable) • : length (variable) Cross-sectional area = • Example ∙ – : 17. , : 0.13 , : , : 1000 • = 17.1 -
Characterization of the Cmos Finfet Structure On
CHARACTERIZATION OF THE CMOS FINFET STRUCTURE ON SINGLE-EVENT EFFECTS { BASIC CHARGE COLLECTION MECHANISMS AND SOFT ERROR MODES By Patrick Nsengiyumva Dissertation Submitted to the Faculty of the Graduate School of Vanderbilt University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY in Electrical Engineering May 11, 2018 Nashville, Tennessee Approved: Lloyd W. Massengill, Ph.D. Michael L. Alles, Ph.D. Bharat B. Bhuva, Ph.D. W. Timothy Holman, Ph.D. Alexander M. Powell, Ph.D. © Copyright by Patrick Nsengiyumva 2018 All Rights Reserved DEDICATION In loving memory of my parents (Boniface Bimuwiha and Anne-Marie Mwavita), my uncle (Dr. Faustin Nubaha), and my grandmother (Verediana Bikamenshi). iii ACKNOWLEDGEMENTS This dissertation work would not have been possible without the support and help of many people. First of all, I would like to express my deepest appreciation and thanks to my advisor Dr. Lloyd Massengill for his continual support, wisdom, and mentoring throughout my graduate program at Vanderbilt University. He has pushed me to look critically at my work and become a better research scholar. I would also like to thank Dr. Michael Alles and Dr. Bharat Bhuva, who have helped me identify new paths in my research and have been a constant source of ideas. I am also very grateful to Dr. W. T. Holman and Dr. Alexander Powell for serving on my committee and for their constructive comments. Special thanks go to Dr. Jeff Kauppila, Jeff Maharrey, Rachel Harrington, and Tim Haeffner for their support with test IC designs and experiments. I would also like to thank Dennis Ball (Scooter) for his tremendous help with TCAD models.