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Physical Structure of CMOS Integrated Circuits Physical Structure of CMOS Integrated Circuits Dae Hyun Kim EECS Washington State University References • John P. Uyemura, “Introduction to VLSI Circuits and Systems,” 2002. – Chapter 3 • Neil H. Weste and David M. Harris, “CMOS VLSI Design: A Circuits and Systems Perspective,” 2011. – Chapter 1 Goal • Understand the physical structure of CMOS integrated circuits (ICs) Logical vs. Physical • Logical structure • Physical structure Source: http://www.vlsi-expert.com/2014/11/cmos-layout-design.html Integrated Circuit Layers • Semiconductor – Transistors (active elements) • Conductor – Metal (interconnect) • Wire • Via • Insulator – Separators Integrated Circuit Layers • Silicon substrate, insulator, and two wires (3D view) Substrate • Side view Metal 1 layer Insulator Substrate • Top view Integrated Circuit Layers • Two metal layers separated by insulator (side view) Metal 2 layer Via 12 (connecting M1 and M2) Insulator Metal 1 layer Insulator Substrate • Top view Connected Not connected Integrated Circuit Layers Integrated Circuit Layers • Signal transfer speed is affected by the interconnect resistance and capacitance. – Resistance ↑ => Signal delay ↑ – Capacitance ↑ => Signal delay ↑ Integrated Circuit Layers • Resistance – = = = Direction of • : sheet resistance (constant) current flows ∙ ∙ • : resistivity (= , : conductivity) 1 – Material property (constant) – Unit: • : thickess (constant) Ω ∙ • : width (variable) • : length (variable) Cross-sectional area = • Example ∙ – : 17. , : 0.13 , : , : 1000 • = 17.1 10 = 2023 1Ω ∙ . 65 −6 −9 1000∙10 −6 −9 ∙ Ω ∙ ∙ 0 13∙10 ∙ 65∙10 Ω Integrated Circuit Layers • Capacitance Direction of – = current flows ∙ • : permittivity – Material property (constant) – Unit: F/m • : distance between two conductors • Example : 1.8 10 / : 0.13 , : , : 1000 – , −11 . • = 1.8 10 / = 3.6 10 = ∙ −656 −6 −11 0 13∙10 ∙ 1000∙10 −14 −9 ∙ ∙ 65∙10 ∙ 36 MOSFETs – Physical Shape • What a MOSFET looks like at the physical level – : Channel length Gate – : Channel width (G) – : Aspect ratio Current flows Source (S) Drain (D) Silicon dioxide = Substrate (silicon wafer) Gate oxide (insulator) G S D G S D Top view Side view MOSFETs – Physical Shape • Inverter Source: Neil H. Weste and David M. Harris, “CMOS VLSI Design: A Circuits and Systems Perspective,” 2011 MOSFETs – Device Physics • Atomic density of a silicon crystal – 5 × 10 22 ≈ • Intrinsic carrier density – # free electrons (due to thermal excitations) – 1.45 × 10 / (at room temperature) 10 3 ≈ • Mass action law when no current flows in pure silicon – = = – = • : # 2free electrons • : # free holes MOSFETs – Device Physics • Doping – Add impurity atoms (dopants) to enhance # electrons or # holes. – n-type material: if more electrons are added (donors). • : # donors (10 ~10 / ) • # free electrons (majority16 19 carriers):3 / 3 / • # holes (minority carriers): 2 ≈ 3 • ≈ – p-type ≫material: if more holes are added (acceptors). • : # acceptors (10 ~10 / ) • # holes (majority carriers):14 19 3 / 3 / • # free electrons (minority carriers): ≈ 2 3 • ≈ ≫ MOSFETs – Device Physics • Conductivity – = ( + ) • : The charge of an electron ( 1.602 10 ) ∙ ∙ • : Electron mobility (1360 / ) −19 − ∙ • : Hole mobility (480 / 2 ) ∙ 2 • Intrinsic silicon ∙ – 4.27 10 – 2.34 10− 6 ≈ ∙ • Quartz glass (insulator)5 ≈ ∙ – 10 • Mobility 12 ≈ – > • Impurity scattering – Adding a large number of impurity atoms reduces the mobility. PN Junction > 0 = 0 p p p n n n > 0 = 0 pn junction Forward current Reverse blocking MOSFETs Contact Contact (metal) (metal) G G n+ n+ p+ p+ n-well p p nFET pFET n+: heavily doped with donors p+: heavily doped with acceptors * Contacts are used to connect source/drain/gate to metal 1. MOSFETs – Device Physics • : oxide thickness – Typically a few nm • Gate material – Polysilicon (called poly) – Metal • Oxide capacitance (Gate(M) – Insulator(O) – Semiconductor(S)) – = • = : unit gate capacitance ∙ – 3.9 = 3.9 8.854 10 / = −12 • : gate ≈ area 0( ∙ ) ∙ G – Example ∙ • = , = , = – 0. 8 45 70 ≈ 013 MOSFETs – Device Physics (nFET) = 0 > 0 G G electrons n+ n+ n+ n+ p p • Current – Channel charge: = ( ) • No charge forms until reaches . − − | | – Current flowing the channel: = • = : channel transit time (the average time needed for an electron to move from S to D). • = = – ∙ ∙( ) ≈ ∙ ∙ ∙ − ∙ MOSFETs – Device Physics (nFET) • Current through the channel – = ≈• =∙ ∙ ∙ : device− transconductance∙ ∙ − ∙ , , • ∙ : constants∙ • , : variables (designers can decide) • , : variables (but either 0 or ) • Channel resistance > – = = ( ) 1 G Channel resistance ∙ − n+ n+ p MOSFETs – Device Physics (pFET) = < | | − G G holes p+ p+ p+ p+ n n • Current – Channel charge: = ( ) • No charge forms until reaches | |. − | | – Current flowing the channel: = − • = : channel transit time (the average time needed for an electron to move from D to S). • = = – ∙ ∙( ) ≈ ∙ ∙ ∙ − ∙ MOSFETs – Device Physics • Current through the channel – = ≈• =∙ ∙ ∙ : device− transconductance∙ ∙ − ∙ , , • ∙ : constants∙ • , : variables (designers can decide) • , : variables (but either 0 or ) • Channel resistance < | | = = – ( ) − 1 G Channel resistance ∙ − p+ p+ p MOSFETs – Device Physics • Charging the gate requires current flows. – = – The transistor itself has a signal delay. – If is large, the delay goes up. • Energy – = = = = 1 2 – = ∫ ∫ ∙ ∫ ∙ 2 1 2 – Driving2 a transistor consumes energy (power dissipation). .
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