Physical Structure of CMOS Integrated Circuits

Dae Hyun Kim

EECS Washington State University References

• John P. Uyemura, “Introduction to VLSI Circuits and Systems,” 2002. – Chapter 3 • Neil H. Weste and David M. Harris, “CMOS VLSI Design: A Circuits and Systems Perspective,” 2011. – Chapter 1 Goal

• Understand the physical structure of CMOS integrated circuits (ICs) Logical vs. Physical

• Logical structure

𝑏𝑏 𝑐𝑐 𝑓𝑓

• Physical structure 𝑎𝑎

Source: http://www.vlsi-expert.com/2014/11/cmos-layout-design.html Integrated Circuit Layers

• Semiconductor – Transistors (active elements)

• Conductor – Metal (interconnect) • Wire • Via

• Insulator – Separators Integrated Circuit Layers

• Silicon substrate, insulator, and two wires (3D view)

Substrate

• Side view Metal 1 layer Insulator

Substrate

• Top view Integrated Circuit Layers

• Two metal layers separated by insulator (side view) Metal 2 layer Via 12 (connecting M1 and M2) Insulator Metal 1 layer Insulator

Substrate

• Top view

Connected Not connected Integrated Circuit Layers Integrated Circuit Layers

• Signal transfer speed is affected by the interconnect resistance and capacitance. – Resistance ↑ => Signal delay ↑ – Capacitance ↑ => Signal delay ↑ Integrated Circuit Layers

• Resistance

– = = = Direction of 𝑙𝑙 𝜌𝜌 𝑙𝑙 𝑙𝑙 • : sheet resistance (constant) current flows 𝑅𝑅 𝜌𝜌 𝐴𝐴 𝑡𝑡 ∙ 𝑤𝑤 𝑅𝑅𝑠𝑠 ∙ 𝑤𝑤 • 𝑅𝑅:𝑠𝑠 resistivity (= , : conductivity) 1 – Material property (constant) 𝜌𝜌 𝜎𝜎 𝜎𝜎 – Unit: • : thickess (constant) Ω ∙ 𝑚𝑚 𝑙𝑙 • : width (variable) 𝑡𝑡 𝑡𝑡 • : length (variable) 𝑤𝑤 Cross-sectional area 𝑙𝑙 𝑤𝑤 =

• Example 𝐴𝐴 𝑡𝑡 ∙ 𝑤𝑤 – : 17. , : 0.13 , : , : 1000 • = 17.1 10 = 2023 𝜌𝜌 1𝑛𝑛Ω ∙ 𝑚𝑚 𝑡𝑡 𝜇𝜇𝑚𝑚 𝑤𝑤 . 65𝑛𝑛𝑛𝑛 𝑙𝑙 −6 𝜇𝜇𝑚𝑚 −9 1000∙10 𝑚𝑚 −6 −9 𝑅𝑅 ∙ Ω ∙ 𝑚𝑚 ∙ 0 13∙10 𝑚𝑚 ∙ 65∙10 𝑚𝑚 Ω Integrated Circuit Layers

• Capacitance Direction of – = current flows 𝑡𝑡∙𝑙𝑙 • : permittivity 𝐶𝐶 𝜀𝜀 𝑠𝑠 – Material property (constant) 𝜀𝜀 – Unit: F/m • : distance between two conductors

𝑠𝑠 𝑙𝑙 𝑡𝑡 • Example : 1.8 10 / : 0.13 , : , : 1000 – , 𝑠𝑠 −11 . • = 1.8 10 / = 3.6 10 = 𝜀𝜀 ∙ 𝐹𝐹 𝑚𝑚 𝑡𝑡 𝜇𝜇𝑚𝑚 𝑠𝑠 −65𝑛𝑛6 𝑛𝑛 𝑙𝑙 −6 𝜇𝜇𝜇𝜇 −11 0 13∙10 𝑚𝑚 ∙ 1000∙10 𝑚𝑚 −14 −9 𝐶𝐶 ∙ 𝐹𝐹 𝑚𝑚 ∙ 65∙10 𝑚𝑚 ∙ 𝐹𝐹 36𝑓𝑓𝑓𝑓 MOSFETs – Physical Shape

• What a MOSFET looks like at the physical level

– : Channel length Gate – : Channel width (G) 𝐿𝐿 – 𝑊𝑊: Aspect ratio Current flows 𝑊𝑊 𝐿𝐿

𝑾𝑾 Source (S) Drain (D) Silicon dioxide = Substrate (silicon𝑳𝑳 wafer) Gate oxide (insulator) G

S D G S D 𝑾𝑾 𝑳𝑳 Top view Side view MOSFETs – Physical Shape

• Inverter

Source: Neil H. Weste and David M. Harris, “CMOS VLSI Design: A Circuits and Systems Perspective,” 2011 MOSFETs – Device Physics

• Atomic density of a silicon crystal – 5 × 10 22 𝑁𝑁𝑆𝑆𝑆𝑆 ≈ • Intrinsic carrier density – # free electrons (due to thermal excitations) – 1.45 × 10 / (at room temperature) 10 3 𝑛𝑛𝑖𝑖 ≈ 𝑐𝑐𝑐𝑐 • Mass action law when no current flows in pure silicon – = = – = 𝑛𝑛 𝑝𝑝 𝑛𝑛𝑖𝑖 • : # 2free electrons 𝑖𝑖 𝑛𝑛𝑛𝑛• :𝑛𝑛 # free holes 𝑛𝑛 𝑝𝑝 MOSFETs – Device Physics

• Doping – Add impurity atoms (dopants) to enhance # electrons or # holes. – n-type material: if more electrons are added (donors). • : # donors (10 ~10 / ) • # free electrons (majority16 19 carriers):3 / 𝑁𝑁𝑑𝑑 𝑐𝑐𝑐𝑐 3 / 𝑛𝑛 𝑑𝑑 • # holes (minority carriers): 2 𝑛𝑛 ≈ 𝑁𝑁 𝑐𝑐𝑐𝑐 𝑛𝑛𝑖𝑖 3 • 𝑝𝑝𝑛𝑛 ≈ 𝑁𝑁𝑑𝑑 𝑐𝑐𝑐𝑐 – p-type𝑛𝑛𝑛𝑛 ≫material:𝑝𝑝𝑛𝑛 if more holes are added (acceptors). • : # acceptors (10 ~10 / ) • # holes (majority carriers):14 19 3 / 𝑁𝑁𝑎𝑎 𝑐𝑐𝑐𝑐 3 𝑝𝑝 𝑎𝑎 / • # free electrons (minority carriers):𝑝𝑝 ≈ 𝑁𝑁 𝑐𝑐𝑐𝑐 2 𝑛𝑛𝑖𝑖 3 • 𝑛𝑛𝑝𝑝 ≈ 𝑁𝑁𝑎𝑎 𝑐𝑐𝑐𝑐 𝑝𝑝𝑝𝑝 ≫ 𝑛𝑛𝑝𝑝 MOSFETs – Device Physics

• Conductivity – = ( + ) • : The charge of an electron ( 1.602 10 ) 𝜎𝜎 𝑞𝑞 𝜇𝜇𝑛𝑛 ∙ 𝑛𝑛 𝜇𝜇𝑝𝑝 ∙ 𝑝𝑝 • : Electron mobility (1360 / ) −19 𝑞𝑞 − ∙ • : Hole mobility (480 / 2 ) 𝜇𝜇𝑛𝑛 𝑐𝑐𝑐𝑐 𝑉𝑉 ∙ 𝑠𝑠 2 • Intrinsic𝜇𝜇 𝑝𝑝silicon 𝑐𝑐𝑐𝑐 𝑉𝑉 ∙ 𝑠𝑠 – 4.27 10 – 2.34 10− 6 𝜎𝜎 ≈ ∙ • Quartz glass (insulator)5 𝜌𝜌 ≈ ∙ – 10 • Mobility 12 𝜌𝜌 ≈ – >

• Impurity𝝁𝝁𝒏𝒏 𝝁𝝁scattering𝒑𝒑 – Adding a large number of impurity atoms reduces the mobility. PN Junction

> 0 = 0

𝐼𝐼 𝐼𝐼 p p p

n n n

> 0 = 0

𝐼𝐼 𝐼𝐼 pn junction Forward current Reverse blocking MOSFETs

Contact Contact (metal) (metal)

G G

n+ n+ p+ p+ n-well p p

nFET pFET

n+: heavily doped with donors p+: heavily doped with acceptors

* Contacts are used to connect source/drain/gate to metal 1. MOSFETs – Device Physics

• : oxide thickness – Typically a few nm 𝑡𝑡𝑜𝑜𝑜𝑜 • Gate material – Polysilicon (called poly) – Metal • Oxide capacitance (Gate(M) – Insulator(O) – Semiconductor(S)) – =

𝐺𝐺• 𝑜𝑜𝑜𝑜= 𝐺𝐺: unit gate capacitance 𝐶𝐶 𝑐𝑐 ∙𝜀𝜀𝑜𝑜𝑜𝑜𝐴𝐴 𝑜𝑜𝑜𝑜– 3.9 = 3.9 8.854 10 / 𝑐𝑐 𝑡𝑡𝑜𝑜𝑜𝑜 = −12 • : gate𝜀𝜀𝑜𝑜𝑜𝑜 ≈ area𝜀𝜀 0( ∙ ) ∙ 𝐹𝐹 𝑚𝑚 𝑉𝑉𝐺𝐺 G – Example𝐴𝐴𝐺𝐺 𝐿𝐿 ∙ 𝑊𝑊 • = , = , = – 0. 𝑜𝑜𝑜𝑜 𝑡𝑡𝑜𝑜𝑜𝑜 8𝑛𝑛𝑛𝑛 𝐿𝐿 45𝑛𝑛𝑛𝑛 𝑊𝑊 70𝑛𝑛𝑛𝑛 𝑡𝑡 𝐶𝐶𝐺𝐺 ≈ 013𝑓𝑓𝑓𝑓 MOSFETs – Device Physics (nFET)

= 0 > 0 𝑉𝑉𝐺𝐺 𝑉𝑉𝐺𝐺 G G electrons

n+ n+ n+ n+ p p 𝑳𝑳 • Current – Channel charge: = ( ) • No charge forms until reaches . 𝑐𝑐 𝐺𝐺 𝐺𝐺 𝑇𝑇𝑇𝑇 𝑄𝑄 −𝐶𝐶 𝑉𝑉 − |𝑉𝑉 | – Current flowing the channel:𝑉𝑉𝐺𝐺 = 𝑉𝑉𝑇𝑇 𝑇𝑇 𝑄𝑄𝑐𝑐 • = : channel transit time (the𝐼𝐼 average𝜏𝜏𝑡𝑡 time needed for an electron to move𝐿𝐿 from S to D). 𝜏𝜏𝑡𝑡 𝑣𝑣 • = = 𝑉𝑉𝐷𝐷𝐷𝐷 – 𝑣𝑣 𝜇𝜇𝑛𝑛 ∙ 𝐸𝐸 𝜇𝜇𝑛𝑛 ∙( 𝐿𝐿 ) 𝑾𝑾 𝑰𝑰 ≈ 𝝁𝝁𝒏𝒏 ∙ 𝒄𝒄𝒐𝒐𝒐𝒐 ∙ 𝑳𝑳 ∙ 𝑽𝑽𝑮𝑮 − 𝑽𝑽𝑻𝑻𝑻𝑻 ∙ 𝑽𝑽𝑫𝑫𝑫𝑫 MOSFETs – Device Physics (nFET)

• Current through the channel – = 𝑊𝑊 𝐼𝐼 ≈• 𝜇𝜇𝑛𝑛 =∙ 𝑐𝑐𝑜𝑜𝑜𝑜 ∙ 𝐿𝐿 ∙ 𝑉𝑉:𝐺𝐺 device− 𝑉𝑉𝑇𝑇𝑇𝑇 transconductance∙ 𝑉𝑉𝐷𝐷𝐷𝐷 𝛽𝛽𝑛𝑛 ∙ 𝑉𝑉𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 ∙ 𝑉𝑉𝐷𝐷𝐷𝐷 𝑊𝑊 , , • 𝛽𝛽𝑛𝑛 𝜇𝜇𝑛𝑛 ∙ 𝑐𝑐𝑜𝑜𝑜𝑜: constants∙ 𝐿𝐿 • , : variables (designers can decide) 𝜇𝜇𝑛𝑛 𝑐𝑐𝑜𝑜𝑜𝑜 𝑉𝑉𝑇𝑇𝑇𝑇 • , : variables (but either 0 or ) 𝐿𝐿 𝑊𝑊 𝑉𝑉𝐺𝐺 𝑉𝑉𝐷𝐷𝐷𝐷 𝑉𝑉𝐷𝐷𝐷𝐷 • Channel resistance > – = = ( ) 𝑉𝑉𝐺𝐺 𝑉𝑉𝑇𝑇𝑇𝑇 𝑉𝑉𝐷𝐷𝐷𝐷 1 G Channel resistance 𝑅𝑅𝑛𝑛 𝐼𝐼 𝛽𝛽𝑛𝑛∙ 𝑉𝑉𝐺𝐺−𝑉𝑉𝑇𝑇𝑇𝑇 n+ n+ p MOSFETs – Device Physics (pFET)

= < | | 𝑉𝑉𝐺𝐺 𝑉𝑉𝐷𝐷𝐷𝐷 𝑉𝑉𝐺𝐺 𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑉𝑉𝑇𝑇𝑇𝑇 G G holes

p+ p+ p+ p+ n n 𝑳𝑳 • Current – Channel charge: = ( ) • No charge forms until reaches | |. 𝑄𝑄𝑐𝑐 𝐶𝐶𝐺𝐺 𝑉𝑉𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 | | – Current flowing the channel:𝑉𝑉𝐺𝐺 = 𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑉𝑉𝑇𝑇𝑇𝑇 𝑄𝑄𝑐𝑐 • = : channel transit time (the𝐼𝐼 average𝜏𝜏𝑡𝑡 time needed for an electron to move𝐿𝐿 from D to S). 𝜏𝜏𝑡𝑡 𝑣𝑣 • = = 𝑉𝑉𝑆𝑆𝑆𝑆 – 𝑣𝑣 𝜇𝜇𝑝𝑝 ∙ 𝐸𝐸 𝜇𝜇𝑝𝑝 ∙( 𝐿𝐿 ) 𝑾𝑾 𝑰𝑰 ≈ 𝝁𝝁𝒑𝒑 ∙ 𝒄𝒄𝒐𝒐𝒐𝒐 ∙ 𝑳𝑳 ∙ 𝑽𝑽𝑮𝑮 − 𝑽𝑽𝑻𝑻𝑻𝑻 ∙ 𝑽𝑽𝑺𝑺𝑺𝑺 MOSFETs – Device Physics

• Current through the channel – = 𝑊𝑊 𝐼𝐼 ≈• 𝜇𝜇𝑝𝑝 =∙ 𝑐𝑐𝑜𝑜𝑜𝑜 ∙ 𝐿𝐿 ∙ 𝑉𝑉:𝐺𝐺 device− 𝑉𝑉𝑇𝑇 𝑝𝑝transconductance∙ 𝑉𝑉𝑆𝑆𝑆𝑆 𝛽𝛽𝑝𝑝 ∙ 𝑉𝑉 𝐺𝐺 − 𝑉𝑉𝑇𝑇𝑇𝑇 ∙ 𝑉𝑉𝑆𝑆𝑆𝑆 𝑊𝑊 , , • 𝛽𝛽𝑝𝑝 𝜇𝜇𝑝𝑝 ∙ 𝑐𝑐𝑜𝑜𝑜𝑜: constants∙ 𝐿𝐿 • , : variables (designers can decide) 𝜇𝜇𝑝𝑝 𝑐𝑐𝑜𝑜𝑜𝑜 𝑉𝑉𝑇𝑇𝑇𝑇 • , : variables (but either 0 or ) 𝐿𝐿 𝑊𝑊 𝑉𝑉𝐺𝐺 𝑉𝑉𝑆𝑆𝑆𝑆 𝑉𝑉𝐷𝐷𝐷𝐷 • Channel resistance < | | = = – ( ) 𝑉𝑉𝐺𝐺 𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑉𝑉𝑇𝑇𝑇𝑇 𝑉𝑉𝑆𝑆𝑆𝑆 1 G Channel resistance 𝑅𝑅𝑝𝑝 𝐼𝐼 𝛽𝛽𝑝𝑝∙ 𝑉𝑉𝐺𝐺− 𝑉𝑉𝑇𝑇𝑇𝑇 p+ p+ p MOSFETs – Device Physics

• Charging the gate requires current flows. – = 𝑑𝑑𝑉𝑉𝐺𝐺 – 𝑖𝑖The𝐶𝐶 transistor𝐺𝐺 𝑑𝑑𝑑𝑑 itself has a signal delay. – If is large, the delay goes up.

𝐶𝐶𝐺𝐺 • Energy – = = = = 𝑑𝑑𝑑𝑑 1 2 – 𝐸𝐸 = ∫ 𝑃𝑃 𝑑𝑑𝑑𝑑 ∫ 𝑉𝑉 ∙ 𝐼𝐼 𝑑𝑑𝑑𝑑 ∫ 𝑉𝑉 ∙ 𝐶𝐶 𝑑𝑑𝑑𝑑 𝑑𝑑𝑑𝑑 2 𝐶𝐶𝑉𝑉 1 2 – 𝐸𝐸Driving2 𝐶𝐶 𝐺𝐺a𝑉𝑉 𝐷𝐷𝐷𝐷transistor consumes energy (power dissipation).