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CMOS Inverter As Analog Circuit: an Overview

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CMOS Inverter As Analog Circuit: an Overview Journal of Low Power Electronics and Applications Review CMOS Inverter as Analog Circuit: An Overview Woorham Bae 1,2 1 Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720, USA; [email protected] 2 Ayar Labs, Santa Clara, CA 95054, USA Received: 24 June 2019; Accepted: 17 August 2019; Published: 20 August 2019 Abstract: Since the CMOS technology scaling has focused on improving digital circuit, the design of conventional analog circuits has become more and more difficult. To overcome this challenge, there have been a lot of efforts to replace conventional analog circuits with digital implementations. Among those approaches, this paper gives an overview of the latest achievement on utilizing a CMOS inverter as an analog circuit. Analog designers have found that a simple resistive feedback pulls a CMOS inverter into an optimum biasing for analog operation. Recently developed applications of the resistive-feedback inverter, including CMOS inverter as amplifier, high-speed buffer, and output driver for high-speed link, are introduced and discussed in this paper. Keywords: analog; analog and mixed signal; amplifier; CMOS; driver; high-speed buffer; high-speed I/O; Integrated circuit; Inverter 1. Introduction Since the 1960s, scaling of silicon technologies (Moore’s law) has dominantly driven the semiconductor industry, as the scaling is actually the almighty knob for all the challenges we have had; lower power consumption, higher speed, and higher density. However, the main focus of the scaling has been the improvement of digital circuit, for example high Ion/Ioff ratio, as the computing capability has been constrained by the power consumption, instead of the speed of the transistor [1,2]. Such digital-driven scaling leads to several issues in analog circuit design. For instance, the intrinsic gain of transistor has been significantly reduced due to the short-channel effect. Moreover, the threshold voltage of transistor has not been scaled at the same rate of the supply voltage scaling, in order for suppressing the leakage current [3]. That means the “normalized” voltage headroom for analog circuit has been reduced. Therefore, adopting conventional gain-boosting techniques (i.e., cascode) becomes more and more difficult in modern CMOS technology [4]. What makes things worse is that the gate-overdrive voltage of analog circuits should be decreased as the voltage headroom reduces, which increases the sensitivity of analog circuits to the device mismatch [5]. We can observe such trend in Figure1, which compares the stacked common-source (CS) amplifier to the non-stacked CS amplifier [6,7]. Figure1a,b shows the normalized gain of CS amplifiers with respect to V DD/VTH and the normalized large-signal bandwidth with respect to the normalized current dissipation, respectively. The gain of the stacked topology decreases much steeper than that of the non-stacked, which means that the gain enhancement from the cascode topology becomes less attractive in the modern CMOS technology where the voltage headroom is reduced. Moreover, the achievable bandwidth of the stacked amplifier is much less than the non-stacked amplifier even when it dissipates more current, because the increased self-loading from the stacked transistor degrades the rise/fall time. In addition, [6] revealed that the input-referred noise becomes even worse in the stacked topology because the transconductance gm increases due to the reduced gate-overdrive voltage. J. Low Power Electron. Appl. 2019, 9, 26; doi:10.3390/jlpea9030026 www.mdpi.com/journal/jlpea J. Low Power Electron. Appl. 2019, 9, 26 2 of 15 J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 2 of 15 4 1 2 0.8 0 0.6 -2 0.4 -4 -6 0.2 -8 0 22.533.5 0 0.2 0.4 0.6 0.8 1 Figure 1. ComparisonComparison of of stacked over non-stacked st structureructure using common-source (CS) amplifier amplifier topology.topology. ( a) Gain degradationdegradation asas aa functionfunction ofof VVDDDD/V/VTH [6],[6], ( (bb)) large-signal large-signal bandwidth bandwidth degradation degradation as a function of current consumption [[7],7], (c) circuit diagram of a CSCS amplifier.amplifier. In summary,summary, what what we we could could observe observe from from the CMOSthe CMOS scaling scaling trend trend is that is the that scaling the hasscaling focused has focusedon improving on improving the digital the circuits; digital hence, circuits; the performance hence, the ofperformance analog circuits of analog has been circuits degraded has due been to degradedthe short-channel due to etheffect short-channel and the reduced effect voltage and headroom.the reduced The voltage analog headroom. circuit designers The analog have come circuit up designerswith the fact have that come a CMOS up with inverter, the fact which that a is CMOS the representative inverter, which of the is the digital representative circuit family, of the can digital be the circuitmost powerful family, can circuit be the in modern most powerful CMOS technologies,circuit in modern even inCMOS the analog technologies, domain even [8,9]. in First, the thereanalog is domainno stacking; [8,9]. thus, First, it hasthere not is been no astacking;ffected by thus, the reducedit has not voltage been headroom. affected by Second, the reduced CMOS invertervoltage utilizes gm of PMOS as well as that of NMOS at the same time. When we compare the two circuits headroom. Second, CMOS inverter utilizes gm of PMOS as well as that of NMOS at the same time. Whengiven inwe Figure compare2, we the can two find circuits that they given have in theFigure same 2, load we capacitance,can find that including they have the the self-loading. same load However, in case of the CMOS inverter, the overall gm is the sum of g and g ; thus, we can get a capacitance, including the self-loading. However, in case of the CMOSmN inverter,mP the overall gm is the higher bandwidth. This aspect becomes much powerful in recent process technologies, where strained sum of gmN and gmP; thus, we can get a higher bandwidth. This aspect becomes much powerful in recentsilicon process technique technologies, enhances the where PMOS strained current silico densityn technique as much enhances as that of the NMOS PMOS [10 –current12]. In fact,density when as muchwe consider as that theof NMOS sizing, [10–12]. the P/N In ratio fact, of when the inverter we consider for analog the sizing, intent the is di P/Nfferent ratio to of the the digital inverter intent. for analogIn order intent technology is different where to the the strained digital silicon intent technique. In order is technology not adopted, where digital the inverter strained has silicon PMOS techniquewhich is generally is not adopted, twice larger digital than inverter NMOS, has because PMOS wewhich have is togenerally match thetwice strength larger ofthan PMOS NMOS, and becauseNMOS, sincewe have we to assume match that the onlystrength one of of PMOS the PMOS and andNMOS, NMOS since is we turned assume on atthat a time.only one However, of the PMOSin such and analog NMOS inverter, is turned the optimum on at a is time. at around However, P/N ratio in such of unity, analog where inverter, we can the achieve optimum the highest is at g per input capacitance [13]. Note that the PMOS and NMOS continuously run together in analog aroundm P/N ratio of unity, where we can achieve the highest gm per input capacitance [13]. Note that themode. PMOS That and means NMOS we werecontinuously not ableto run fully together utilize in the analog gmP in mode. older technologyThat means nodes. we were In other not able words, to the strained silicon boosts the current density of PMOS to be matched to that of NMOS, and therefore fully utilize the gmP in older technology nodes. In other words, the strained silicon boosts the current densityit makes of the PMOS analog to inverterbe matched become to that more of NMOS, powerful. and therefore it makes the analog inverter become moreSome powerful. readers may wonder how a CMOS inverter acts like an analog circuit, because it is a representative digital circuit. In fact, the boundary of analog and digital is ambiguous, but “biasing” can be used to distinguish them, which is explained in Figure3. The blue line shows the input-output transfer curve of an inverter. Note that the blue lines are the same for both figures. When we see the big picture (large signal), we can find a digital circuit. However, when we focus on a certain operating J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 3 of 15 J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 3 of 15 J. Low Power Electron. Appl. 2019, 9, 26 3 of 15 point (small signal), we can find an analog circuit. We can also find that the maximum gain is achieved at the point where the input and output are the same, that is, at the switching threshold. Analog designers found that such optimum bias point can be achieved with the self-biasing using the resistive feedback,J. Low Power asElectron. shown Appl. in 2019 Figure, 9, x4 FOR. PEER REVIEW 3 of 15 Figure 2. Utilization of gm of PMOS in a CMOS inverter. Figure 2. Utilization of gm of PMOS in a CMOS inverter. Some readers may wonder how a CMOS inverter acts like an analog circuit, because it is a Some readers may wonder how a CMOS inverter acts like an analog circuit, because it is a representative digital circuit. In fact, the boundary of analog and digital is ambiguous, but “biasing” representative digital circuit. In fact, the boundary of analog and digital is ambiguous, but “biasing” can be used to distinguish them, which is explained in Figure 3.
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