CMOS Inverter As Analog Circuit: an Overview

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Journal of Low Power Electronics and Applications

Review CMOS Inverter as Analog Circuit: An Overview

Woorham Bae 1,2

1 Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720, USA; [email protected] 2 Ayar Labs, Santa Clara, CA 95054, USA

Received: 24 June 2019; Accepted: 17 August 2019; Published: 20 August 2019

Abstract: Since the CMOS technology scaling has focused on improving digital circuit, the design of conventional analog circuits has become more and more difficult. To overcome this challenge, there have been a lot of efforts to replace conventional analog circuits with digital implementations. Among those approaches, this paper gives an overview of the latest achievement on utilizing a CMOS inverter as an analog circuit. Analog designers have found that a simple resistive feedback pulls a CMOS inverter into an optimum biasing for analog operation. Recently developed applications of the resistive-feedback inverter, including CMOS inverter as amplifier, high-speed buffer, and output driver for high-speed link, are introduced and discussed in this paper.

Keywords: analog; analog and mixed signal; ampliﬁer; CMOS; driver; high-speed buﬀer; high-speed I/O; Integrated circuit; Inverter

1. Introduction Since the 1960s, scaling of silicon technologies (Moore’s law) has dominantly driven the semiconductor industry, as the scaling is actually the almighty knob for all the challenges we have had; lower power consumption, higher speed, and higher density. However, the main focus of the scaling has been the improvement of digital circuit, for example high Ion/Ioff ratio, as the computing capability has been constrained by the power consumption, instead of the speed of the transistor [1,2]. Such digital-driven scaling leads to several issues in analog circuit design. For instance, the intrinsic gain of transistor has been significantly reduced due to the short-channel effect. Moreover, the threshold voltage of transistor has not been scaled at the same rate of the supply voltage scaling, in order for suppressing the leakage current [3]. That means the “normalized” voltage headroom for analog circuit has been reduced. Therefore, adopting conventional gain-boosting techniques (i.e., cascode) becomes more and more difficult in modern CMOS technology [4]. What makes things worse is that the gate-overdrive voltage of analog circuits should be decreased as the voltage headroom reduces, which increases the sensitivity of analog circuits to the device mismatch [5]. We can observe such trend in Figure1, which compares the stacked common-source (CS) amplifier to the non-stacked CS amplifier [6,7]. Figure1a,b shows the normalized gain of CS amplifiers with respect to V DD/VTH and the normalized large-signal bandwidth with respect to the normalized current dissipation, respectively. The gain of the stacked topology decreases much steeper than that of the non-stacked, which means that the gain enhancement from the cascode topology becomes less attractive in the modern CMOS technology where the voltage headroom is reduced. Moreover, the achievable bandwidth of the stacked amplifier is much less than the non-stacked amplifier even when it dissipates more current, because the increased self-loading from the stacked transistor degrades the rise/fall time. In addition, [6] revealed that the input-referred noise becomes even worse in the stacked topology because the transconductance gm increases due to the reduced gate-overdrive voltage.

J. Low Power Electron. Appl. 2019, 9, 26; doi:10.3390/jlpea9030026 www.mdpi.com/journal/jlpea J. Low Power Electron. Appl. 2019, 9, 26 2 of 15 J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 2 of 15

4 1

2 0.8 0 0.6 -2 0.4 -4 -6 0.2 -8 0 22.533.5 0 0.2 0.4 0.6 0.8 1

Figure 1. ComparisonComparison of of stacked over non-stacked st structureructure using common-source (CS) amplifier ampliﬁer

topology.topology. ( a) Gain degradationdegradation asas aa functionfunction ofof VVDDDD/V/VTH [6],[6], ( (bb)) large-signal large-signal bandwidth bandwidth degradation degradation as a function of current consumption [[7],7], (c) circuit diagram of a CSCS ampliﬁer.amplifier.

In summary,summary, what what we we could could observe observe from from the CMOSthe CMOS scaling scaling trend trend is that is the that scaling the hasscaling focused has focusedon improving on improving the digital the circuits; digital hence, circuits; the performance hence, the ofperformance analog circuits of analog has been circuits degraded has due been to degradedthe short-channel due to etheffect short-channel and the reduced effect voltage and headroom.the reduced The voltage analog headroom. circuit designers The analog have come circuit up designerswith the fact have that come a CMOS up with inverter, the fact which that a is CMOS the representative inverter, which of the is the digital representative circuit family, of the can digital be the circuitmost powerful family, can circuit be the in modern most powerful CMOS technologies,circuit in modern even inCMOS the analog technologies, domain even [8,9]. in First, the thereanalog is domainno stacking; [8,9]. thus, First, it hasthere not is been no astacking;ffected by thus, the reducedit has not voltage been headroom. affected by Second, the reduced CMOS invertervoltage utilizes gm of PMOS as well as that of NMOS at the same time. When we compare the two circuits headroom. Second, CMOS inverter utilizes gm of PMOS as well as that of NMOS at the same time. Whengiven inwe Figure compare2, we the can two find circuits that they given have in theFigure same 2, load we capacitance,can find that including they have the the self-loading. same load However, in case of the CMOS inverter, the overall gm is the sum of g and g ; thus, we can get a capacitance, including the self-loading. However, in case of the CMOSmN inverter,mP the overall gm is the higher bandwidth. This aspect becomes much powerful in recent process technologies, where strained sum of gmN and gmP; thus, we can get a higher bandwidth. This aspect becomes much powerful in recentsilicon process technique technologies, enhances the where PMOS strained current silico densityn technique as much enhances as that of the NMOS PMOS [10 –current12]. In fact,density when as muchwe consider as that theof NMOS sizing, [10–12]. the P/N In ratio fact, of when the inverter we consider for analog the sizing, intent the is di P/Nfferent ratio to of the the digital inverter intent. for analogIn order intent technology is different where to the the strained digital silicon intent technique. In order is technology not adopted, where digital the inverter strained has silicon PMOS techniquewhich is generally is not adopted, twice larger digital than inverter NMOS, has because PMOS wewhich have is togenerally match thetwice strength larger ofthan PMOS NMOS, and becauseNMOS, sincewe have we to assume match that the onlystrength one of of PMOS the PMOS and andNMOS, NMOS since is we turned assume on atthat a time.only one However, of the PMOSin such and analog NMOS inverter, is turned the optimum on at a is time. at around However, P/N ratio in such of unity, analog where inverter, we can the achieve optimum the highest is at g per input capacitance [13]. Note that the PMOS and NMOS continuously run together in analog aroundm P/N ratio of unity, where we can achieve the highest gm per input capacitance [13]. Note that themode. PMOS That and means NMOS we werecontinuously not ableto run fully together utilize in the analog gmP in mode. older technologyThat means nodes. we were In other not able words, to the strained silicon boosts the current density of PMOS to be matched to that of NMOS, and therefore fully utilize the gmP in older technology nodes. In other words, the strained silicon boosts the current densityit makes of the PMOS analog to inverterbe matched become to that more of NMOS, powerful. and therefore it makes the analog inverter become moreSome powerful. readers may wonder how a CMOS inverter acts like an analog circuit, because it is a representative digital circuit. In fact, the boundary of analog and digital is ambiguous, but “biasing” can be used to distinguish them, which is explained in Figure3. The blue line shows the input-output transfer curve of an inverter. Note that the blue lines are the same for both figures. When we see the big picture (large signal), we can find a digital circuit. However, when we focus on a certain operating J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 3 of 15 J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 3 of 15

J. Low Power Electron. Appl. 2019, 9, 26 3 of 15

point (small signal), we can ﬁnd an analog circuit. We can also ﬁnd that the maximum gain is achieved at the point where the input and output are the same, that is, at the switching threshold. Analog designers found that such optimum bias point can be achieved with the self-biasing using the resistive feedback,J. Low Power asElectron. shown Appl. in 2019 Figure, 9, x4 FOR. PEER REVIEW 3 of 15

Figure 2. Utilization of gm of PMOS in a CMOS inverter. Figure 2. Utilization of gm of PMOS in a CMOS inverter. Some readers may wonder how a CMOS inverter acts like an analog circuit, because it is a Some readers may wonder how a CMOS inverter acts like an analog circuit, because it is a representative digital circuit. In fact, the boundary of analog and digital is ambiguous, but “biasing” representative digital circuit. In fact, the boundary of analog and digital is ambiguous, but “biasing” can be used to distinguish them, which is explained in Figure 3. The blue line shows the can be used to distinguish them, which is explained in Figure 3. The blue line shows the input-output transfer curve of an inverter. Note that the blue lines are the same for both figures. input-output transfer curve of an inverter. Note that the blue lines are the same for both figures. When we see the big picture (large signal), we can find a digital circuit. However, when we focus on When we see the big picture (large signal), we can find a digital circuit. However, when we focus on a certain operating point (small signal), we can find an analog circuit. We can also find that the a certain operating point (small signal), we can find an analog circuit. We can also find that the maximum gain is achieved at the point where the input and output are the same, that is, at the maximum gain is achieved at the point where the input and output are the same, that is, at the switching threshold. Analog designers found that such optimum bias point can be achieved with the switching threshold. Analog designers found that such optimum bias point can be achieved with the self-biasing using the resistive feedback, as shown in Figure 4. self-biasing using the resistiveFigure f eedback, 2. Utilization as shown of gm ofof in PMOS PMOS Figure in in a a4. CMOS CMOS inverter. inverter.

Some readers may wonder how a CMOS inverter acts like an analog circuit, because it is a representative digital circuit. In fact, the boundary of analog and digital is ambiguous, but “biasing” can be used to distinguish them, which is explained in Figure 3. The blue line shows the input-output transfer curve of an inverter. Note that the blue lines are the same for both figures. When we see the big picture (large signal), we can find a digital circuit. However, when we focus on a certain operating point (small signal), we can find an analog circuit. We can also find that the maximum gain is achieved at the point where the input and output are the same, that is, at the switching threshold. Analog designers found that such optimum bias point can be achieved with the self-biasing using the resistive feedback, as shown in Figure 4.

Figure 3. Inverter gain curve and distinction between digital and analog. FigureFigure 3. 3. InverterInverter gain gain curve curve and and distinct distinctionion between between digital digital and and analog. analog.

Figure 3. Inverter gain curve and distinction between digital and analog.

Figure 4. CMOS inverter with resistive feedback. Figure 4. CMOS inverter with resistive feedback. Nowadays, in order to take advantage of the CMOS inverter in modern process technology, there has been a lot of approaches to adopt CMOS inverter into analog circuits. This paper focuses on the applications of high-speed analog circuits, and introduces three examples of that, ampliﬁer in optical

Figure 4. CMOS inverter with resistive feedback. J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 4 of 15

J. Low PowerNowadays, Electron. Appl.in order2019, 9to, 26 take advantage of the CMOS inverter in modern process technology,4 of 15 there has been a lot of approaches to adopt CMOS inverter into analog circuits. This paper focuses on the applications of high-speed analog circuits, and introduces three examples of that, amplifier in communicationoptical communication receivers receivers [6,14–30 ],[6 high-speed,14–30], high-speed clock and clock data buandﬀer data [13 ,buffer31–41], [13,31–41], and output and driver output for high-speeddriver for high-speed I/O transmitter I/O transmitter [13,40,42–50 [13,40,42–50].].

2.2. CMOSCMOS InverterInverter asas anan AmplifierAmplifier TheThe firstfirst exampleexample wewe areare goinggoing toto covercover isis thethe useuse ofof aa CMOSCMOS inverterinverter as a high-speed amplifier,amplifier, whichwhich isis mostlymostly adoptedadopted inin optical optical communication communication receiver.receiver. InIn opticaloptical communication,communication, high-speedhigh-speed serialserial datadata is transmittedis transmitted by modulatingby modulating the amplitude the amplitude of light. Atof thelight. receiving At the side, receiving a photodetector side, a (PD)photodetector converts the (PD) received converts light the signal received to the photocurrent.light signal to Due the tophotocurrent. the limited PD Due responsibility to the limited as well PD asresponsibility and the limited as well extinction as and ratio the limited at the transmit extinction side, ratio typically, at the transmit the amplitude side, typically, of photo-current the amplitude signal rangesof photo-current from tens of signal uA to ranges hundreds from of tens uA. Inof orderuA to to hundreds be processed of uA in. a In CMOS order integrated to be processed circuit (IC),in a theCMOS current-mode integrated signalcircuit should (IC), the be current-mode converted to voltage-mode.signal should be Thus, converted a trans-impedance to voltage-mode. amplifier Thus, is a usedtrans-impedance at the very front-end amplifier of is an used optical at the receiver. very front-en As a result,d of an the optical overall receiver. performance As a result, of the the receiver overall is predominantlyperformance of determined the receiver by is the predominantly trans-impedance det amplifierermined by (TIA). the Sincetrans-impedance there is an inherent amplifier trade-o (TIA).ff betweenSince there TIA gainis /annoise inherent and bandwidth, trade-off compound betweensemiconductor TIA gain/noise process and was bandwidth, traditionally compound preferred tosemiconductor build the optical process interface was ICtraditionally due to their preferred high-speed to build characteristic. the optical However, interface since IC due continuous to their advancehigh-speed of CMOScharacteristic. technology However, has reduced since continuo the gap,us nowadays, advance of CMOS CMOS technology technology is has becoming reduced thethe mainstreamgap, nowadays, for optical CMOS interface technology ICs. is becoming the mainstream for optical interface ICs. WeWe can can seesee aa briefbrief historyhistory ofof CMOSCMOS TIATIA forfor opticaloptical receiverreceiver inin FigureFigure5 .5. The The most most primitive primitive TIA TIA isis aa resistor.resistor. ButBut therethere isis aa strictstrict trade-o trade-offff between betweengain gainand andbandwidth, bandwidth, becausebecause thethe gaingain equalsequals thethe resistance R and the bandwidth is 1/2πRC . In addition, the signal-to-noise (SNR) is another main resistance R and the bandwidth is 1/2πRCPDPD. In addition, the signal-to-noise (SNR) is another main issueissue ofof concern.concern. TheThe totaltotal integratedintegrated noisenoise duedue toto thethe thermalthermal noisenoise ofof thethe resistorresistor is is given given as as to: to: kTkT V2 V 2 = = , (1) n,outnout, C , (1) CPDPD wherewherek kis is the the Boltzmann Boltzmann constant constant and andT Tis is the the absolute absolute temperature. temperature. Then, Then, the the input-referred input-referred noise noise is obtainedis obtained by by dividing dividing (1) (1) with with the the trans-impedance trans-impedance gain gain R as: R as: kTkT i2 i2= = , (2) n,innin, 2 2 , (2) RRCCPDPD

FigureFigure 5.5. Trans-impedanceTrans-impedance ampliﬁeramplifier examples.examples. J. Low Power Electron. Appl. 2019, 9, 26 5 of 15

From (2) we can obtain the SNR to:

C SNR = PD I2 R2, (3) kT in where we can observe that higher gain leads to a better SNR, which implies the trade-off of gain/noise over the bandwidth. Many circuit designers have tried to find a way to break the trade-off, and they found that the common-gate (CG) amplifier can break the trade-off. Because the photo-current directly flows to the load resistor, the trans-impedance gain equals to the resistance. On the other hand, the input impedance of the CG amplifier is 1/gm, so the pole at the input of CG amplifier is given as to:

gm1 f 3dB = (4) − 2πCPD

Note that there is no R term in, which implies that the aforementioned trade-off is now broken, since CPD is generally much larger than the load capacitance of the CG amplifier. Since the 1/gm can be reduced by drawing more current by the current source (IB), we can achieve high gain as well as high bandwidth at the cost of power consumption. In addition, [51,52] proposed a regulated-cascode (RGC) TIA, which further improves the gain-bandwidth product of TIA. However, the effectiveness of such stacked configuration has been degraded due to the aforementioned scaling issue, now many researchers have ended up with the resistive feedback inverter TIA. The inverter-TIA still have a similar trade-off as the passive TIA; however, the input resistance of the resistive feedback inverter is R/(1 + A), where A is the gain of the inverter. That means that the trade-off is relaxed by the factor of A. Additionally, note that there is no other path that the photo-current can flow; the gain of this TIA equals R. Readers may consult [28] for a detailed history of TIA evolution. The resistive-feedback inverter TIA is also able to be combined with inductive peaking technique, to extend the bandwidth with less gain/power penalty. References [19,25] present the inverter TIA with series inductive peaking, which is illustrated in Figure6a. Since an inductor blocks an instantaneous current flow, it enables sequential charging (or discharging) of the two adjacent capacitances (for example, PD capacitance and self-load at the input node, or self-load and load capacitances at the output node), which leads to a faster transient response. On the other hand, [6] added an inductor in series with the feedback resistor; that is, the inductive feedback as shown in Figure6b. At a low frequency, the effect of the inductor is negligible; thus, the TIA simply follows the transfer gain of the resistive-feedback inverter. Note that such negative feedback increases the bandwidth at the cost of reduced low-frequency gain. On the other hand, the impedance of the inductor increases as the frequency increases; hence, after zero frequency, it surpasses that of the feedback resistor. That means that the total impedance in the feedback path increases, and thus the gain increases. If the inductive impedance is larger enough than the resistance, the transfer gain of the TIA follows that of the inverter without resistive feedback. At a very high frequency, the second order pole, which is introduced by the inductor and the capacitance as well as the intrinsic pole of the inverter, let the transfer gain decrease rapidly as the frequency increases. As a result, such inductive feedback leads to a high-frequency peaking, which can be used to compensate the dominant pole by the CPD. Recent state-of-the-arts works in [15,24,29] have combined the series peaking and the inductive feedback, and therefore considerable high-bandwidth at a quite impressive energy efficiency is achieved. Moreover, the authors in [29] saved inductor area by incorporating T-coil inductive peaking. J. Low Power Electron. Appl. 2019, 9, 26 6 of 15 J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 6 of 15

Figure 6. (a) Inverter TIA with series peaking,peaking, ((b)) withwith inductiveinductive feedback.feedback.

The applicationapplication of CMOS inverter as an amplifieramplifier is notnot limitedlimited toto thethe TIA.TIA. OpticalOptical receiversreceivers presentedpresented inin [ 18[18,19,21,24–27],19,21,24–27] extend extend the the usage usage of theof the CMOS CMOS inverter inverter to the to post the limitingpost limiting amplifier amplifier which followswhich follows the TIA. the In addition,TIA. In addition, [16,17,30 ][16,17,30] present resistive-feedback-inverter-based present resistive-feedback-inverter-based low-noise low-noise amplifier (LNA)amplifier and (LNA) variable and gain variable amplifier gain (VGA), amplifier respectively. (VGA), respectively. In such applications, In such aapplications, normal inverter a normal stage andinverter a resistive-feedback stage and a resist stageive-feedback are placed stage alternately are placed to retain alternatel the self-biasy to retain (resistive the self-bias feedback) (resistive as well asfeedback) high gain as (inverter),well as high as gain shown (inverter), in Figure as7. shown Recalling in Figure Figure 37., theRecalling small-signal Figure gain 3, the of small-signal inverter is maximizedgain of inverter at the is crossover maximized voltage. at the Therefore,crossover involt orderage. toTherefore, maximize in the order overall to maximize gain of the the amplifier overall chain,gain of the the common-mode amplifier chain, voltage the common-mode should be corrected. voltage Due should to the be considerably corrected. Due large to gainthe considerably of the chain, thelarge resistive gain of feedback the chain, itself the isresistive not enough feedback to retain itself a is correct not enough bias point. to retain Such a common-mode correct bias point. variation Such leadscommon-mode to some large-signal variation leads non-idealities, to some suchlarge-signal as duty-cycle non-idealities, distortion. such Therefore, as duty-cycle a common-mode distortion. feedbackTherefore, is a generally common-mode included feedback as shown is generally in the example included of Figure as shown7. The in DC the componentexample of ofFigure the output 7. The signalDC component is extracted of the through output a low-passsignal is extracted filter (LPF) through and then a low-pass compared filter to the(LPF) reference and then voltage compared (i.e., crossoverto the reference voltage). voltage The feedback(i.e., crossover adjusts voltage). the input The common feedback level adjusts until the common-modeinput common level voltage until at thethe outputcommon-mode becomes voltage the same at asthe the output reference beco voltage.mes the same as the reference voltage.

Figure 7. Inverter-based multi-stage amplifier with common-mode feedback. Figure 7. Inverter-based multi-stage amplifier with common-mode feedback. To sum up, the resistive-feedback inverter has become a mainstream of TIA implementation, To sum up, the resistive-feedback inverter has become a mainstream of TIA implementation, to to fully utilize the CMOS process scaling, against the conventional TIA structures. Moreover, there fully utilize the CMOS process scaling, against the conventional TIA structures. Moreover, there have been many efforts to extend the application to other high-speed amplifiers. For evidence, taking have been many efforts to extend the application to other high-speed amplifiers. For evidence, advantage of the advanced CMOS technology node (14 nm FinFet), [25], where the inverter-based taking advantage of the advanced CMOS technology node (14 nm FinFet), [25], where the TIA and post amplifier are adopted, achieves the highest bandwidth optical receiver, which achieves inverter-based TIA and post amplifier are adopted, achieves the highest bandwidth optical receiver, 64 Gb/s with binary signaling. which achieves 64 Gb/s with binary signaling. J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 7 of 15

J. Low Power Electron. Appl. 2019, 9, 26 7 of 15 3. High Speed Buffer In the previous section, we focused on the small-signal behavior of CMOS inverter (with 3. High Speed Buffer resistive feedback). Here, we will be care of more large-signal-like behavior compared to the amplifierIn the operation. previous section, If the input we focused signal onswing the small-signalis large enough, behavior that ofis, CMOS entering inverter to the (with noise resistive margin feedback).region, the Here, amplitude we will of be carethe signal of more no large-signal-like longer needs behaviorto be considered compared as to long the amplifier as the gain operation. of the If“buffer” the input is signallarger than swing unity. is large However, enough, taking that is, into entering account to the the intrinsic noise margin gain of region, an inverter, the amplitude the 3 dB ofbandwidth the signal is no typically longer needs 5–10× to lower be considered than the asunity-gain long as the bandwidth gain of the (Figure “buffer” 8). is If larger the main than unity.signal However,component taking is at intobetween account the the3 dB intrinsic bandwidth gain and of an th inverter,e unity-gain the 3bandwidth, dB bandwidth the signal is typically experiences 5–10 × lowerdistortion than thewhile unity-gain passing bandwidththrough the (Figure buffer8). even If the though main signal the componentamplitude is atnot between attenuated. the 3 dBFor bandwidthexample, since and the phase unity-gain delay bandwidth, is not a constant the signal over experiences the frequency, distortion a pattern-dependent while passing jitter through will thebe buintroducedffer even to though the non-return-to-zero the amplitude is not (NRZ) attenuated. datastream For example,even if the since Nyquist the phase frequency delay is is below not a constantthe unity-gain over the bandwidth frequency, of a the pattern-dependent buffer [53]. Clock jitter signal will is be another introduced good to and the simpler non-return-to-zero example, as (NRZ)there is datastream only a single even frequency if the Nyquist tone. frequency Let us take is belowinto account the unity-gain additive bandwidth white noise. of The the buamplitudeffer [53]. Clocknoise signalis filtered is another out by good the noise and simpler margin example, of inverter; as there however, is only the a single phase frequency noise propagates tone. Let through us take intothe accountinverter. additive Moreover, white if the noise. clock The frequency amplitude is higher noise is than filtered the out3 dB by bandwidth, the noise margin the low of frequency inverter; however,noise has the a phaselarger noise gain propagates than the throughfundamental the inverter. frequency Moreover, component. if the clockThat frequencyleads to isthe higher jitter thanamplification the 3 dB bandwidth,[54]. Duty-cycle the low distortion frequency is another noise has important a larger gainissue, than since the the fundamental duty-cycle frequencyis actually component.the DC component That leads of to the the jittersignal amplification so the duty-cycle [54]. Duty-cycle error is distortionamplified is after another passing important through issue, a sinceband-limited the duty-cycle buffer is[42]. actually the DC component of the signal so the duty-cycle error is amplified after passing through a band-limited buffer [42].

0 1 10 10 0 10 00 10 000

-20 Figure 8. Magnitude response of CMOS inverter. Figure 8. Magnitude response of CMOS inverter. The above observation implies that the 3 dB bandwidth is more important than the unity-gain bandwidthThe above while observation handling a high-speedimplies that analogthe 3 dB signal, band inwidth contrary is more to the important digital intent. than the The unity-gain resistive feedbackbandwidth is also while very handling useful toa high-speed extend the 3 analog dB bandwidth signal, in of contrary the inverter. to the We digital can obtain intent. a The quantitative resistive analysisfeedback how is thealso resistive very useful feedback to extendsextend the bandwidth3 dB bandwidth of the inverter, of the frominverter. the small We signalcan obtain model a shownquantitative in Figure analysis9. Applying how the KCL resistive to the outputfeedback node, extends we obtain: the bandwidth of the inverter, from the small signal model shown in Figure 9. Applying KCL to the output node, we obtain: vout vx vout gmvx + + jωCLvout = − , (5) rovvvRF− ++outω = x out gvmx j Cv Lout , (5) rR where gm is the sum of gmN and gmP. EquationoF (5) leads to the transfer function as:

where gm is the sum of gmN and gmP. Equationv (5)1 leadsgm RtoF the transfer function as: out = − , (6) vx 1 + RF + jωR C ro F L J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 8 of 15 J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 8 of 15

vgR1− vgRout= 1− m F out= m F , v R , (6) J. Low Power Electron. Appl. 2019 9 x R++F ω , , 26 vx ++1 F ωjRCFL 8 of(6) 15 1 jRCFL ro ro where we can achieve the 3 dB bandwidth to: where we can achieve the 3 dB bandwidthbandwidth to:to: ω =+111111 ωω3dB =3dB=++ .. (7)(7) 3dB . (7) roCLrCoLRFC RL FL C rCoL R FL C

16 16 BW-sim 12 BW-sim RF 12 RF BW-cal vx vout BW-cal vx vout 8 8 r Cin gmvx r o CL 4 Cin gmvx o CL 4

0 0 0510 0510 RF (k ) RF (k ) (a) (b) (a) (b)

FigureFigure 9. (9.a )(a Small) Small signal signal diagram diagram of of resistive resistive feedback feedback inverter, inverter, (b) ( verificationb) verification of (7).of (7). Figure 9. (a) Small signal diagram of resistive feedback inverter, (b) verification of (7). Note that the 3 dB bandwidth of the inverter without feedback is 1/r C . That is, the resistive Note that the 3 dB bandwidth of the inverter without feedback is o1/rLoCL. That is, the resistive feedbackNote increases that the the3 dB 3 dBbandwidth bandwidth of th bye 1inverterR C . Simulatedwithout feedback bandwidth is 1/r shownoCL. That in Figure is, the9b resistive verifies feedback increases the 3 dB bandwidth by/ 1/RF LFCL. Simulated bandwidth shown in Figure 9b verifies feedback increases the 3 dB bandwidth by 1/RFCL. Simulated bandwidth shown in Figure 9b verifies (7).(7). Moreover, Moreover, thanks thanks to to the the negative negative feedback, feedback, this this circuit circuit is is less less sensitive sensitive to to the the PVT PVT variations variations (7). Moreover, thanks to the negative feedback, this circuit is less sensitive to the PVT variations comparedcompared to to the the normal normal CMOS CMOS inverter. inverter. compared to the normal CMOS inverter. OnOn the the other other hand, hand, an AC-coupling an AC-coupling capacitor capacitor is widely is usedwidely at theused input at the of the input resistive of the feedback resistive On the other hand, an AC-coupling capacitor is widely used at the input of the resistive inverter,feedback for inverter, clock buff forer applicationclock buffer [32 application–39] (Figure [32–39] 10). The (Figure primary 10). motivations The primary of themotivations AC coupling of the feedback inverter, for clock buffer application [32–39] (Figure 10). The primary motivations of the forAC the coupling clock bu ffforer the are clock as follows: buffer are as follows: AC coupling for the clock buffer are as follows: 1. 1. SinceSince AC AC coupling coupling completely completely blocks blocks the the DC DC component component of of the the clock clock signal, signal, the the duty-cycle duty-cycle 1. Since AC coupling completely blocks the DC component of the clock signal, the duty-cycle distortiondistortion does does not propagate.not propagate. Thanks Thanks to the self-biasingto the self-biasing to the cross-over to the voltage,cross-over the duty-cyclevoltage, the distortion does not propagate. Thanks to the self-biasing to the cross-over voltage, the isduty-cycle restored to is the restored ideal value to the regardless ideal value of regardless the input duty-cycle of the input (Figure duty-cycle 11). (Figure 11). duty-cycle is restored to the ideal value regardless of the input duty-cycle (Figure 11). 2. 2. CombinedCombined with with the the low-pass low-pass characteristic characteristic of of the th inverter,e inverter, AC AC coupling coupling results results in in a band-passa band-pass 2. Combined with the low-pass characteristic of the inverter, AC coupling results in a band-pass characteristic.characteristic. Because Because a a band-pass band-pass filter filter attenuates attenuates all all out-of-band out-of-band noise, noise, it suppressesit suppresses phase phase characteristic. Because a band-pass filter attenuates all out-of-band noise, it suppresses phase noisenoise and and jitter jitter from from the the input input clock clock [54 [54].]. noise and jitter from the input clock [54]. 3. Because the clock buffer does not have to deal with a wide-band signal, the high-frequency 3. BecauseBecause the clockclock bubufferffer does does not not have have to dealto deal with with a wide-band a wide-band signal, signal, the high-frequency the high-frequency cut-off cut-off frequency can be fairly high (<~1/10 of the clock frequency). Therefore, a small capacitor cut-offfrequency frequency can be fairlycan be high fairly (< high~1/10 (<~1/10 of the clockof the frequency). clock frequency). Therefore, Therefore, a small a capacitor small capacitor can be can be used [39]. canused be [ 39used]. [39].

Figure 10. (a) AC-coupled resistive feedback inverter and (b) Miller approximation to calculate high-pass cut-oﬀ frequency. J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 9 of 15

Figure 10. (a) AC-coupled resistive feedback inverter and (b) Miller approximation to calculate J. Low Power Electron. Appl. 2019, 9, 26 9 of 15 high-pass cut-off frequency.

1 Duty-cycle transfer

0.5

0 0 0.2 0.4 0.6 0.8 1

FigureFigure 11. 11. DutyDuty cycle cycle transfer transfer curve curve of of AC-coupled AC-coupled buffer. buﬀer.

TheThe high-pass high-pass cut-off cut-off frequencyfrequency of of the AC-coupled buffer buffer is calculated as follows. Using Using Miller Miller approximation,approximation, the feedbackfeedback resistanceresistance R RF Fis is translated translated to to the the input input resistance resistance of RofF /R(1F/(1+ A +F ),AF where), where AF AisF theis the DC DC gain gain of theof the inverter. inverter. Then, Then, we we obtain: obtain: RF jωR CC vx ω 1+AFF = jC C, (8) v + RF vxin 1 + jω1 AF CC = 1+AF , (8) v R in 1+ jω F C where we can find that the high-pass cut-off frequency+ is: C 1 AF 1 + AF where we can find that the high-pass cut-offω hpfrequency f = is:, (9) RFCC 1+ A For reference, the overall transfer functionω without= MillerF approximation is given in [39] as: hpf , (9) RFCC v sgmRFCC o , (10) For reference, the overall transfer function without MillerR C approximation is given in [39] as: vin − g + 1 + s(C + C + F C ) + s2R C C m ro L C ro F C L vsgRC omFC≅− where CL is the load capacitance of the buffer. Figure 11 shows an example of the, simulated duty-cycle v 1 RC 2 (10) transfer function of an AC-coupledin gsCCsRCC inverter.++() + +FC + mLCFCLrr On the other hand, the bandwidthoo dependency on the feedback resistance can also be utilized whereto control CL theis the delay load of capacitance a buffer chain. of the Conventionally, buffer. Figure a current-starved11 shows an example inverter of [55 the] or simulated a variable duty-cyclecapacitive-load transfer inverter function [56] of have an AC-coupled been widely usedinverter. to build a variable delay line. However, basically, theirOn mechanism the other ishand, to reduce the bandwidth the bandwidth dependency of CMOS on inverterthe feedback to increase resistance the delay. can also As be a result, utilized such to controldelay cells the havedelay a lowerof a buffer bandwidth chain. than Conventionally an inverter, and, a therefore,current-starved they have inverter usually [55] become or a thevariable main capacitive-loadlimiting factor of inverter the maximum [56] ha speedve been of a chip.widely As used a remedy, to build [13,40 a, 41variable] proposed delay a resistive-feedback line. However, basically,based delay their line mechanism whose delay is to is controlledreduce the by bandwidt adjustingh of the CMOS feedback inverter resistance. to increase As we the observed delay. As in (7)a result,and Figure such9 b,delay the feedback cells have extends a lower the bandwidth bandwidth ofthan an inverter.an inverter, That and means therefore, that the they resistive-feedback have usually becomedelay line the actually main limiting increases factor the of bandwidth the maximum to adjust speed the of a delay, chip. insteadAs a remedy, of reducing [13,40,41] the proposed bandwidth. a resistive-feedbackFrom another qualitative based delay viewpoint line whose of large delay signal, is thecontrolled resistive by feedback adjusting decreases the feedback the voltage resistance. swing; Astherefore, we observed the output in (7) rise and/fall Figure time 9b, is reduced. the feedback References extends [13 the,40 bandwidth] verified the of large-signal an inverter. e Thatffect asmeans well, thatsuch the that resistive-feedback the resistive feedback delay lin reducese actually ISI considerablyincreases the comparedbandwidth to to the adjust conventional the delay, delayinstead line, of reducingat the cost the of bandwidth. increased power From consumption another qualitative due to viewpoint the short-circuit of larg currente signal, induced the resistive by the feedback reduced decreasesvoltage swing. the voltage swing; therefore, the output rise/fall time is reduced. References [13,40] verified the large-signal effect as well, such that the resistive feedback reduces ISI considerably J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 10 of 15 compared to the conventional delay line, at the cost of increased power consumption due to the short-circuit current induced by the reduced voltage swing. J. Low Power Electron. Appl. 2019, 9, 26 10 of 15

4. Output Driver for High-Speed Wireline Communication 4. OutputThe last Driver example for High-Speedis the output Wireline driver for Communication high-speed I/O link. On the right side of Figure 12, we can findThe a last conceptual example diagram is the output of a source-series driver for high-speed terminated I/ O(SST) link. driver, On the which right is side also of known Figure as 12 a, wevoltage-mode can find a conceptualdriver [35–50]. diagram Instead of of a source-seriesrelying on a parallel terminated resistance (SST) driver,to match which the driver’s is also knownoutput impedanceas a voltage-mode with the driver characteristic [35–50]. Insteadimpedance of relying of the ontransmission a parallel resistancechannel, the to matchSST driver the driver’s adopts seriesoutput termination. impedance with Such the series-terminated characteristic impedance data transmission of the transmission is conceptually channel, enabled the SST driverwith a adoptsseries combinationseries termination. of a 50- SuchΩ resistance series-terminated and an ideal data switch transmission driven by is conceptuallyNRZ data. The enabled main advantage with a series of SSTcombination driver over of a the 50-Ω parallel-terminationresistance and an ideal counterp switchart, driven which by is NRZ represented data. The by main current-mode advantage of logic SST (CML)driver overdriver, the is parallel-termination its low-power consumption. counterpart, Assumi whichng is terminations represented byat both current-mode transmit logicand receive (CML) sidesdriver, (double is its low-power termination), consumption. the series termination Assuming flows terminations the signal at bothcurrent transmit to 100- andΩ resistance receive sides (I = (doubleVswing/100), termination), whereas the the seriesparallel termination termination flows flows the signalto 25 Ω current (I = V toswing 100-/25).Ω resistance As a result,(I = theVswing parallel/100), whereastermination the dissipates parallel termination 4× higher current flows to to 25 achieveΩ (I = Vaswing same/25). voltage As a swing. result, theOn parallelthe other termination hand, the maindissipates downside 4 higher of SST current driver to originates achieve a sameto the voltagefact that swing. there Onis no the ideal other switch hand, in the IC. main There downside are two × typesof SST of driver practical originates SST implementation, to the fact that thereN-over-N is no idealand P-over-N switch in configurations IC. There are two, as typesshown of in practical Figure 12.SST It implementation, is well known N-over-Nthat the N-over-N and P-over-N works configurations, well only for as low shown swing in Figureapplications, 12. It is whereas well known the P-over-Nthat the N-over-N is appropriate works for well higher only swing for low applications. swing applications, Note that whereas the P-over-N the P-over-N structure is appropriate is a CMOS inverter.for higher Basically, swing applications. their approach Note is thatthe same. the P-over-N Instead structureof using an is aideal CMOS 0-Ω inverter. switch, they Basically, utilize their the finiteapproach resistance is the same.of switch Instead transistor; of using if anthe ideal turn-on 0-Ω resistanceswitch, they equals utilize to the50-Ω finite, a single resistance transistor of switch can worktransistor; as the if the combination turn-on resistance of the equalsideal switch to 50-Ω and, a single the resistor. transistor The can work50-Ω asimpedance the combination is generally of the calibratedideal switch by and adjusting the resistor. the number The 50- Ωofimpedance activated dr isiver generally slices calibratedand the gate-overdrive by adjusting the voltage. number The of mainactivated challenge driver here slices is and the the non-linear gate-overdrive nature voltage. of CMOS The transistor main challenge does not here let is the the transistors non-linear have nature a constantof CMOS resistance transistor over does the not swin let theg range transistors [42]. For have example, a constant when resistance the output over voltage the swing increases, range [42the]. VForDS example,of the pull-down when the NMOS output voltage(MN1, M increases,N3) increases the VandDS ofcauses the pull-down the NMOS NMOS to fall (M intoN1,M theN3 saturation) increases region,and causes where the the NMOS output to fallimpedance into the becomes saturation very region, high. where Note that the outputthe linearity impedance is a function becomes of veryVDS, andhigh. the Note VDS thatrange the equals linearity the isoutput a function swing. of VDS, and the VDS range equals the output swing.

Figure 12.12.Conceptual Conceptual diagram diagram of source-series of source-series terminated terminated (SST) driver (SST) and practicaldriver implementationand practical implementationof N-over-N and of P-over-N N-over-N SST an conﬁgurations.d P-over-N SST configurations.

To resolve this issue, a series resistance is placedplaced at the output of the SST driver, as shown in Figure 1313[ [37,46–48].37,46–48]. The turn-on resistance of the transistor is reduced here (i.e., 25 ΩΩ) to make the sum with the series resistance be 50 Ω. The series resistor takes charge of a portion of the output swing, hence, the VDS of the transistors is reduced. The downside of this approach is the increased transistor J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 11 of 15 J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 11 of 15 sum with the series resistance be 50 Ω. The series resistor takes charge of a portion of the output sumJ. Low Powerwith Electron.the series Appl. resistance2019, 9, 26 be 50 Ω. The series resistor takes charge of a portion of the output11 of 15 swing, hence, the VDS of the transistors is reduced. The downside of this approach is the increased swing, hence, the VDS of the transistors is reduced. The downside of this approach is the increased transistor size. If 25-Ω resistance is used, the size of transistor is doubled so that both the input transistor size. If 25-Ω resistance is used, the size of transistor is doubled so that both the input size.capacitance If 25-Ω andresistance the output is used, self-capacitance the size of transistor are doubled, is doubled each so of that which both theincreases input capacitanceburdens of andthe capacitance and the output self-capacitance are doubled, each of which increases burdens of the thepre-driver output self-capacitancestage and degrades are doubled, the bandwidth each of which of the increases driver burdensitself, respectively. of the pre-driver Note stagethat andthe pre-driver stage and degrades the bandwidth of the driver itself, respectively. Note that the degradestransistors the should bandwidth operate of in the the driver linear itself, region respectively. for better linearity, Note that where the transistors the current should density operate is much in transistors should operate in the linear region for better linearity, where the current density is much thelower linear than region that in for the better saturation linearity, region. where Therefor the currente, the density device is size much is lowergenerally than enormously that in the saturation large. lowerregion. than Therefore, that in the saturation device size region. is generally Therefor enormouslye, the device large. size is generally enormously large.

VDD VDD

50=>25 25 in out

50=>25

Figure 13. SST driver with series resistance. Figure 13. SST driver with series resistance. Rather than putting a series resistor, it has been proposed that using a feedback resistor can Rather thanthan puttingputting a a series series resistor, resistor, it has it has been been proposed proposed that usingthat using a feedback a feedback resistor resistor can change can change the game [13,40,44,50], which is shown in Figure 14. As we studied, the feedback resistor sets changethe game the [ 13game,40,44 [13,40,44,50],,50], which which is shown is shown in Figure in Figure 14. As 14. we As studied, we studied, the feedbackthe feedback resistor resistor sets sets the the biasing point that the CMOS operates in the saturation region. In addition, the DC output thebiasing biasing point point that thethat CMOS the CMOS operates operates in the saturationin the saturation region. Inregion. addition, In theaddition, DC output the DC impedance output impedance becomes 1/gm, instead of 1/gds. That means we can achieve a high current density of the impedancebecomes 1/ gbecomesm, instead 1/g ofm, 1instead/gds. That of 1/g meansds. That we means can achieve we can a high achieve current a high density current of thedensity saturation of the saturation region and a low output impedance from 1/gm as well. In addition, the gm is easy to be saturationregion and region a low outputand a low impedance output fromimpedance 1/gm as from well. 1/g Inm addition, as well. In the addition, gm is easy the to g bem is regulated easy to bybe regulated by using a well-known constant-gm bias circuit [13,57]. regulatedusing a well-known by using a constant-gwell-knownm bias constant-g circuitm [13 bias,57 ].circuit [13,57].

Figure 14. Output driver based on re resistive-feedbacksistive-feedback inverter. Figure 14. Output driver based on resistive-feedback inverter. Although the feedback resistance does not affect affect the DC output impedance, the high-frequency Although the feedback resistance does not affect the DC output impedance, the high-frequency output impedance, which affects affects the return loss of the transmitter, is a function of the feedback output impedance, which affects the return loss of the transmitter, is a function of the feedback resistance. The output impedance is calculated as: resistance. The output impedance is calculated as: 11 1 1++sRsRFCin C Zout ≅⋅1 1+ sRFin C , (11) Zout ≅⋅1 Fin1 , Z gm + 11· 1 + sRFCin( ) , out gsRC++r11o 1()gmro+1 (11) gsRCmFin++1()+ (11) mFinrgromo+1 where Cin is the input capacitance of the driverrgromo [50]. We can find that the1 feedback introduces both zero 1 gmro+1 (at ) and pole (at ). As a result, the output impedance becomes ro at a very high frequency. RFCin RFCin J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 12 of 15 where Cin is the input capacitance of the driver [50]. We can find that the feedback introduces both J. Low Power Electron. Appl. 2019, 9, 26 + 12 of 15 1 grmo 1 zero (at ) and pole (at ). As a result, the output impedance becomes ro at a very RFinC RFinC Therefore,high frequency. a designer Therefore, should a carefullydesigner chooseshould acarefully proper RchooseF such a that proper guarantees RF such the that zero guarantees frequency the is zerohigher frequency than the is Nyquist higher frequencythan the Nyquist of the transmit frequency data. of the transmit data. On thethe otherother hand, hand, there there are are two two downsides downsides of the of resistive-feedbackthe resistive-feedback SST driver;SST driver; low output low output swing swingand power and power consumption. consumption. Since theSince transistor the transistor should sh operateould operate in the in deep the saturationdeep saturation region region to have to havehigh rhigho, the r outputo, the output impedance impedance deviates deviates from 1 /fromgm, which 1/gm, iswhich maintained is maintained by the constant-g by the constant-gm biasing,m whenbiasing, the when output the swing output increases. swing Itincreases. also dissipates It also a higherdissipates current a higher than that current of the conventionalthan that of SSTthe conventionaldriver due to theSST short-circuitdriver due to current. the short-circuit However, ascu therrent. data However, rate increases, as the the data pre-driver’s rate increases, dynamic the pre-driver’sswitching power, dynamic which switching is consumed power, for drivingwhich highis consumed input capacitance, for driving dramatically high input increases. capacitance, Note dramaticallythat the dynamic increases. power Note is proportional that the dynamic to the switchingpower is proportional frequency and to the switching capacitance, frequency whereas and the thedriver’s capacitance, current whereas consumption the driver’s is fixed current regardless consum of theption data is ratefixed (I regardless= Vswing/100 ofΩ the). Asdata a result,rate (I it= Vsurpassesswing/100Ω the). As static a result, power it consumptionsurpasses the of static the outputpower driverconsumption [42]. As of a result,the output the pre-driverdriver [42]. power As a result,reduction, the thanks pre-driver to the smallpower input reduction, capacitance than ofks the to resistive-feedback the small input SST driver,capacitance is able toof fullythe resistive-feedbackcompensate the increased SST driver, static is power.able to fully compensate the increased static power. Another advantage of this driver is a simple slicing implementation because of its inherent current-driven nature.nature. InIn the the conventional conventional drivers drivers (including (including CML CM andL SST),and SST), the output the output driver shoulddriver shouldbe sliced be to controlsliced to the control swing andthethe swing equalization and the coe eqffiualizationcient; thus, coefficient; it increases thethus, complexity it increases and the parasitic.complexity On and the the other parasitic. hand, On in the theresistive-feedback other hand, in the SSTresistive-feedback driver, the slicing SST candriver, be included the slicing in can the becurrent-mode included in pre-driver the current-mode as shown inpre-driver Figure 15 .as That shown is, a simplein Figure current 15. digital-to-analogThat is, a simple convertor current (DAC)digital-to-analog in the pre-driver convertor can (DAC) replace in the the slicing pre-driver at the can output replace stage; the thus,slicing it at significantly the output reducesstage; thus, the itdesign significantly complexity reduces and parasiticthe design eff ects.complexity It has also and been parasitic proven effects. that the It has current alsoDAC-based been proven pre-driver that the currentis beneficial DAC-based for pulse-amplitude pre-driver is be modulationneficial for signalingpulse-amplitude in [40], modulation where a fabricated signaling 28-Gb in [40],/s PAM-4where atransmitter fabricated chip28-Gb/s is presented. PAM-4 transmitter chip is presented.

Figure 15. Current-mode pre-driver for resistive-feedback SST driver. Figure 15. Current-mode pre-driver for resistive-feedback SST driver. 5. Conclusions 5. Conclusions This paper introduces three state-of-the-art applications of CMOS inverter with resistor feedback, by providingThis paper the basicintroduces theories three of those state-of-the-art applications a andpplications the state-of-the-arts of CMOS implementationinverter with resistor results. Thefeedback, focus ofby this providing paper is not the just basic enumerating theories the of prior those arts, applications but emphasizing and thethe potential state-of-the-arts of CMOS implementationinverter as an analog results. circuit. The As focus discussed of this in the pape introduction,r is not just CMOS enumerating inverter becomes the prior more arts, powerful but whereasemphasizing the conventional the potential analog of CMOS circuits inverter become as lessan analog eﬀective circuit. as technology As discussed scales in down. the introduction, As a result, I J. Low Power Electron. Appl. 2019, 9, 26 13 of 15 believe that there are a lot of undiscovered usages of the CMOS inverter, which will need thorough examination in future research.

Funding: This research received no external funding. Conﬂicts of Interest: The authors declare no conﬂict of interest.

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