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Programmable CMOS/Memristor Threshold Logic

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Programmable CMOS/Memristor Threshold Logic This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1 Programmable CMOS/Memristor Threshold Logic Ligang Gao, Fabien Alibart, and Dmitri B. Strukov (k) (k) (k) used in the paper) is given by w1 = w2 = … = wN = 1/k (k) Abstract—This paper proposes a hybrid CMOS/memristor and T = 1. implementation of a programmable threshold logic gate. In this LTG is a universal gate and much more powerful than gate, memristive devices implement ratioed diode-resistor logic, similar fan-in single NAND or NOR gates. A recent study while CMOS circuitry is used for signal amplification and indicates up to 2× reduction on average (and even up to 5× for inversion. Due to the excellent scaling prospects and nonvolatile some) in the gate count for representative benchmark circuits analog memory of memristive devices, the proposed threshold implemented with LTGs, as compared to traditional logic logic is in-field configurable and potentially very compact. The concept is experimentally verified by implementing a 4-input synthesis [4]. This is an example of why LTGs have been a symmetric linear threshold gate with an integrated circuit CMOS popular choice for the implementation of computer arithmetic flip-flop, silicon diodes, and Ag/a-Si/Pt memristive devices. circuits [5, 6]. However, these gates have been historically more commonly applied in artificial neural networks, due to Index Terms—Memristor, programmable circuits, solid-state their similarity in functionality with that of biological neurons electrolyte memory, threshold logic, neural networks. [1], and also conventional signal and image processing due to efficient implementation of weighted filters [7]. For instance, one of the earliest concepts in artificial neural networks – the I. INTRODUCTION McCullough-Pitts perceptron [8] -- can be implemented with a HE development of high-performance threshold logic single LTG. T would benefit a number of important applications in Various implementations of LTGs have been investigated, computing, from microprocessors to bio-inspired information and some are even used today in commercial products [1]. processing [1]. To be specific, let us focus on a particular type Most common implementations are based on pseudo-nMOS, of threshold logic – a linear threshold gate (LTG), whose output-wired inverters, and floating-gate and switch capacitor transfer function for N-input gate is defined as logic styles, whereas less conventional ones utilize non- traditional device technologies such as single electron transistors and negative differential resistance devices. In ∑ { , (1) most cases the weights are fixed and cannot be changed in- field, but some LTG implementations are employing digitally stored weights (which incurs a rather large penalty), and where xi is a Boolean input variable, wi is an integer weight of the corresponding input i, and the threshold T is an integer perhaps only a hybrid technology approach based on CMOS and floating gate transistors relies on programming analog number [2]. A special case of LTG is symmetric LTG with 1 identical weights for different inputs [1, 3]. N-input symmetric weights directly into the gate [9]. The in-field reconfiguration LTG can implement a maximum of N nontrivial Boolean of the LTG’s weights is a very desirable feature for most of (k) (k) (k) the applications, and in this paper we present an alternative functions f (x1, x2, …, xN) defined by w1 = w2 = … = (k) (k) solution for programmable LTGs based on hybrid-circuit wN = 1 and T = k, i.e. technology. The potential advantages over the floating-gate ∑ approach and a comparison to another memristor-based { , (2) threshold gate concept [10-13] are discussed in Section IV. The key element of the proposed hybrid CMOS/memristor 2 where k = 1, 2, …, N. By dividing the inequality in Eq. 2 by k, circuits is a resistance-switching “memristive” [14-16] device the alternative definition for the symmetric LTG (which is also – see, e.g., reviews of such devices and their applications in [17-21]. In the simplest case, a memristive device consists of 1The technique of achieving LTG by replicating normal/complimentary Manuscript received March 19, 2012. This work is supported via NSF inputs of a fixed majority gate, which is a symmetric LTG with fixed weights, grant CCF-1017579 and AFOSR under MURI grant FA9550-12-1-0038. is also not attractive due to its large area overhead. L. Gao, F. Alibart, and D. B. Strukov are with the Department of Electrical 2According to the original definition [14, 15], the more appropriate name and Computer Engineering, University of California at Santa Barbara, Santa would be “CMOS/memristive-device circuit” because the resistance switching Barbara, CA 93106, USA (e-mail: [email protected]; devices considered in this work are not pure memristors because of nonlinear [email protected]; [email protected]) I-V characteristics and hence they belong to a more general class of Copyright (c) 2012 IEEE. Personal use of this material is permitted. memristive devices. However, such a name is in line with the recent However, permission to use this material for any other purposes must be suggestion from the same authors [16], which is to use the term “memristor” obtained from the IEEE by sending a request to [email protected]. in a much broader sense. U.S. Government work not protected by U.S. copyright. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 2 an active thin film layer of some material sandwiched between to the integer numbers required by the original definition of two metal electrodes. The device’s footprint is determined by LTG by multiplying both sides of the inequality in Eq. 1 by the overlap area of two electrodes and, therefore, limited only the appropriate constants. by the electrode’s dimensions. Application of a relatively B. Symmetric LTG large electrical stress (voltage or current) across electrodes changes the resistivity (“memory state”) of the thin film The effect of the dynamic range of memristive devices (i.e. H L material. The memory state of properly engineered devices is the ratio RON /RON ) on the number of different Boolean nonvolatile and could be read without disturbing it with a functions which the N-input LTG can implement, the choice smaller (as compared to a write) electrical stress. For many of optimal RL , and the weights of the memristive devices for devices, the resistance can be changed continuously so that the a particular Boolean function are best investigated using a memory state is essentially analog, which enables many symmetric LTG. For symmetric LTG weights, w(k) = 1/R(k) prospective applications [20-24]. and RL must satisfy the following pair of conditions: (k) II. CMOS/MEMRISTOR THRESHOLD GATE (k-1)RL < R < k RL. (5) A. General Case The inset of Fig. 1(b) shows the possible spectrum of R(k) with Memristive devices are well suited for implementing respect to RL given by (5). In order to implement all N weights in the proposed threshold logic circuits (Fig. 1(a)). In Boolean functions with a symmetric LTG, the [RL, NRL] range particular, let us consider diode-like memristive devices with a L H should fit within a physically permitted range [RON , RON ]; strongly suppressed current below the effective threshold VTH therefore 4 (e.g. due to an additional layer added in the device stack) and linear conductance above such a threshold with a configurable H L RON /RON ≥ N. (6) slope (differential conductance) 1/R (Fig. 1(b)). Here we assume that the slope can be configured to any value between L H 1/RON and 1/RON , so that (a) VINPUT H L 1/RON ≤ 1/R ≤ 1/RON . (3) x1 x2 x3 x4 Such particular I-V of the memristive device simplifies the CMOS D flip-flop x1 implementation of the configurable ratioed diode-resistor logic RON x w1 (DRL) (Fig. 1(a)), which is comprised of several (N) 2 w 2 T w3 memristive devices connected in parallel to a single pull-down x3 3 VOUTPUT w4 resistor RL. To suppress leakage currents between inputs of N x4 the gate, operating voltage is chosen from the condition RL I R L VTH < VDD < 2VTH . (4) (b) ON Neglecting leakage currents below VTH, i.e. currents via ROFF H resistance (Fig. 1(b)), the output voltage of ratioed DRL RON always ranges from 0 to V -V and is equal half of that DD TH R value when VRESET -VTH OFF V 0 +VTH VSET ∑ . (5) L H RON RON Generally, the DRL is connected to a CMOS gate so that the RL 2RL 3RL 4RL NRL voltage swing is restored (and possibly inverted) and the (1) (2) (3) (4) (N) output of the CMOS gate is used to drive the inputs of other R R R R R logic gates. In principle, a simple CMOS inverter would be Fig. 1. (a) The main idea of a LTG implemented with memristors and sufficient for that purpose, although we chose D-flip-flop CMOS D flip-flop; (b) I-V characteristics of memristive devices (schematically represented). The shaded area on panel b shows the range of because of its effectiveness for high-throughput pipelined possible intermediate states utilized for the implementation of the threshold circuits [3, 25]. Assuming that the CMOS gate is designed to gate. restore a signal to VDD (logical “1”), if the input voltage is larger than (V -V )/2 and otherwise to 0 (logical “0”), the DD TH 4 combined circuit (Fig.
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