FinFET History, Fundamentals and Future

Tsu‐Jae King Liu Department of Electrical Engineering and Computer Sciences University of California, Berkeley, CA 94720‐1770 USA

June 11, 2012

2012 Symposium on VLSI Technology Short Course Impact of Moore’s Law

Transistor Scaling Higher Performance, Investment Lower Cost Market Growth

# DEVICES (MM) # DEVICES CMOS generation: 1 um • • 180 nm •• 32 nm

YEAR Source: ITU, Mark Lipacis, Morgan Stanley Research http://www.morganstanley.com/institutional/techresearch/pdfs/2SETUP_12142009_RI.pdf 2 1996: The Call from DARPA • 0.25 m CMOS technology was state‐of‐the‐art • DARPA Advanced Microelectronics (AME) Program Broad Agency Announcement for 25 nm CMOS technology 1998 International Technology Roadmap for Semiconductors (ITRS) 1999 2002 2005 2008 2011 2014 2017 2020 Technology Node 180 130 100 70 50 35 25 18 nm nm nm nm nm nm nm nm Gate Oxide 1.9‐2.5 1.5‐1.9 1.0‐1.5 0.8‐1.2 0.6‐0.8 0.5‐0.6 Thickness, TOX (nm) Solutions No known

Drive Current, IDSAT being pursued solutions

End of Roadmap  UC‐Berkeley project “Novel Fabrication, Device Structures, and Physics of 25 nm FETs for Terabit‐Scale Electronics” • June 1997 through July 2001

3 MOSFET Fundamentals

Metal Oxide Semiconductor 0.25 micron MOSFET XTEM Field‐Effect Transistor:

GATE LENGTH, Lg

Gate

Source Drain Si substrate http://www.eetimes.com/design/automotive‐design/4003940/LCD‐driver‐highly‐integrated

GATE OXIDE THICKNESS, Tox

4 MOSFET Operation: Gate Control

Desired N‐channel MOSFET • Current between Source and Drain characteristics: cross‐section is controlled by the Gate voltage. • High ON current Gate • Low OFF current • “N‐channel” & “P‐channel” MOSFETs gate oxide Leff operate in a complementary manner N+ P N+ “CMOS” = Complementary MOS Source Body Drain

log ID Electron Energy Band Profile ION n(E)  exp (‐E/kT) E

CURRENT

Inverse slope is subthreshold swing, S Sourceincreasing IOFF DRAIN [mV/dec] GATE VOLTAGE

increasing 0 V Drain VTH GS V distance DD 5 CMOS Devices and Circuits

CIRCUIT SYMBOLS CMOS INVERTER CIRCUIT V INVERTER N‐channel P‐channel VDD OUT LOGIC SYMBOL MOSFET MOSFET S G G VDD D VIN VOUT S D S D D S GND VIN 0 V CMOS NAND GATE DD STATIC MEMORY (SRAM) CELL NOT AND (NAND) WORD LINE TRUTH TABLE

0 1 or or BIT LINE 1 0 BIT LINE

6 Improving the ON/OFF Current Ratio

Gate log I D ION C ox Ctotal C S  dep Cox Source Body Drain VDD VGS • The greater the capacitive coupling between Gate and channel, the better control the Gate has over the channel potential.

higher ION/IOFF for fixed VDD, or lower VDD to achieve target ION/IOFF reduced drain‐induced barrier lowering (DIBL):

log ID increasing VDS increasing Drain Source IOFF VDS VGS 7 MOSFET in ON State (VGS > VTH) width velocity inversion‐layer charge density I D  W vQinv gate‐oxide capacitance  v  eff Qinv  Cox (VGS VTH ) mobility gate overdrive D I

Gate CURRENT,

Source Drain

DRAIN Substrate

DRAIN VOLTAGE, VDS 8 Effective Drive Current (IEFF) CMOS inverter chain: V V V V DD 1 2 3 V2 tpLH IH + IL V /2 V3 DD IEFF = V tpHL 2 1 TIME I IH (DIBL = 0) DSAT VDD VIN = VDD S

D IH VIN = 0.83VDD

V VOUT CURRENT IN D V = 0.75V S IN DD GND DRAIN IL VIN = 0.5VDD NMOS

0.5VDD VDD NMOS DRAIN VOLTAGE = VOUT M. H. Na et al. (IBM), IEDM Technical Digest, pp. 121‐124, 2002 9 CMOS Technology Scaling

XTEM images with the same scale courtesy V. Moroz (Synopsys, Inc.) 90 nm node 65 nm node 45 nm node 32 nm node

T. Ghani et al., (after S. Tyagi et al., IEDM 2005) K. Mistry et al., P. Packan et al., IEDM 2003 IEDM 2007 IEDM 2009

• Gate length has not scaled proportionately with device pitch (0.7x per generation) in recent generations. – Transistor performance has been boosted by other means.

10 MOSFET Performance Boosters

• Strained channel regions  eff

• High‐k gate dielectric and metal gate electrodes  Cox Cross‐sectional TEM views of Intel’s 32 nm CMOS devices

P. Packan et al. (Intel), IEDM Technical Digest, pp. 659‐662, 2009 11 Process‐Induced Variations

• Sub‐wavelength lithography: – Resolution enhancement techniques are costly and increase process sensitivity

• Gate line‐edge roughness: courtesy Mike Rieger (Synopsys, Inc.)

photoresist

• Random dopant fluctuations (RDF): – Atomistic effects become significant in nanoscale FETs A. Brown et al., SiO2 Gate IEEE Trans. Nanotechnology, p. 195, 2002 Source Drain A. Asenov, Symp. VLSI Tech. Dig., p. 86, 2007

12 A Journey Back through Time… Why New Transistor Structures?

• Off‐state leakage (IOFF) must be suppressed as Lg is scaled down

– allows for reductions in VTH and hence VDD • Leakage occurs in the region away from the channel surface  Let’s get rid of it! Lg Ultra‐Thin‐Body MOSFET: Gate

SourceSource DrainDrain “Silicon‐on‐ Buried Oxide Insulator” (SOI) Substrate Wafer

14 Thin‐Body MOSFETs

• IOFF is suppressed by using an adequately thin body region. – Body doping can be eliminated  higher drive current due to higher carrier mobility  Reduced impact of random dopant fluctuations (RDF)

Ultra‐Thin Body (UTB) Double‐Gate (DG)

Lg

Gate Gate Source Drain Source Drain TSi TSi Buried Oxide Gate Substrate

TSi < (1/4)  Lg TSi < (2/3)  Lg

B. Yu et al., ISDRS 1997 R.‐H. Yan et al., IEEE TED 1992 15 Effect of TSi on Leakage

Lg = 25 nm; Tox,eq = 12Å

TSi = 10 nm TSi = 20 nm

6 10 G Si Thickness [nm] G 0.0 SD4.0 3x102 8.0 12.0 SD G 16.0 10‐1 20.0 Leakage Current G 2 Density [A/cm ]    @ VDS = 0.7 V Ioff = 2.1 nA/ m Ioff = 19 A/ m

16 Double‐Gate MOSFET Structures

PLANAR:

VERTICAL FIN:

L. Geppert, IEEE Spectrum, October 2002 17 DELTA MOSFET D. Hisamoto, T. Kaga, Y. Kawamoto, and E. Takeda (Hitachi Central Research Laboratory), “A fully depleted lean‐channel transistor (DELTA) –a novel vertical ultrathin SOI MOSFET,” IEEE Electron Device Letters Vol. 11, pp. 36‐39, 1990

• Improved gate control Wl = 0.4 m observed for Wg < 0.3 m

– Leff= 0.57 m

18 Double‐Gate FinFET

• Self‐aligned gates straddle narrow silicon fin • Current flows parallel to wafer surface

Gate Length, Lg S G G Gate 2 D Source Gate 1 Current Flow Fin Height, H

Drain fin

Fin Width, Wfin

19 1998: First N‐channel FinFETs D. Hisamoto, W.‐C. Lee, J. Kedzierski, E. Anderson, H. Takeuchi, K. Asano, T.‐J. King, J. Bokor, and C. Hu, “A folded‐channel MOSFET for deep‐sub‐tenth micron era,” IEEE International Electron Devices Meeting Technical Digest, pp. 1032‐1034, 1998 Plan View

Lg = 30 nm Wfin = 20 nm Hfin = 50 nm

Lg = 30 nm Wfin = 20 nm Hfin = 50 nm

• Devices with Lg down to 17 nm were successfully fabricated

20 1999: First P‐channel FinFETs X. Huang, W.‐C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.‐K. Choi, K. Asano, V. Subramanian, T.‐J. King, J. Bokor, and C. Hu, “Sub 50‐nm FinFET: PMOS,” IEEE International Electron Devices Meeting Technical Digest, pp. 67‐70, 1999

Lg = 18 nm Wfin = 15 nm Hfin = 50 nm

Transmission Electron Micrograph

21 2000: Vested Interest from Industry

• Semiconductor Research Corporation (SRC) &AMD fund project: – Development of a FinFET process flow compatible with a conventional planar CMOS process – Demonstration of the compatibility of the FinFET structure with a production environment (October 2000 through September 2003)

• DARPA/SRC Focus Center Research Program funds projects: – Approaches for enhancing FinFET performance (MSD Center, April 2001 through August 2003) – FinFET‐based circuit design (C2S2 Center, August 2003 through July 2006)

22 FinFET Structures

Original: Gate‐last Gate process flow

Source Si FinDrain

Gate Improved: Gate‐first process flow Source Drain

23 Fin Width Requirement

Measured FinFET DIBL

• To adequately suppress DIBL,

Lg/Wfin > 1.5  Challenge for lithography!

N. Lindert et al. (UC‐Berkeley), IEEE Electron Device Letters, Vol. 22, pp. 487‐489, 2001 24 Sub‐Lithographic Fin Patterning Spacer Lithography a.k.a. Sidewall Image Transfer (SIT) and Self‐Aligned Double Patterning (SADP) 1. Deposit & pattern sacrificial layer 3. Etch back mask layer to form “spacers”

SOI SOI

BOX BOX

4. Remove sacrificial layer; 2. Deposit mask layer (SiO or Si N ) 2 3 4 etch SOI layer to form fins

SOI fins

BOX BOX

Note that fin pitch is 1/2 that of patterned layer

25 Benefits of Spacer Lithography

• Spacer litho. provides for better CD control and uniform fin width

SEM image of FinFET with spacer‐defined fins:

Y.‐K. Choi et al. (UC‐Berkeley), IEEE Trans. Electron Devices, Vol. 49, pp. 436‐441, 2002 26 Spacer‐Defined FinFETs

Y.‐K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.‐J. King, J. Bokor, and C. Hu, "Sub‐20nm CMOS FinFET technologies,” IEEE International Electron Devices Meeting Technical Digest, pp. 421‐424, 2001

Lg = 60 nm, Wfin = 40 nm Transfer Characteristics Output Characteristics

27 2001: 15 nm FinFETs

Y.‐K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.‐J. King, J. Bokor, C. Hu, "Sub‐20nm CMOS FinFET technologies,” IEEE International Electron Devices Meeting Technical Digest, pp. 421‐424, 2001

Transfer Characteristics Output Characteristics 10-2 10-2 600 600 V =1.0 V V =-1.0 V P+Si Ge d d 0.4 0.6 |V -V|=1.2V NMOS -4 Gate -4 500 PMOS g t 500 10 10 [A/um] [uA/um] d V =0.05 V d 400 400 -6 V =-0.05 V d -6 Voltage step 10 d 10 300 : 0.2V 300

-8 N-body= -8 10 10 2x1018cm-3 200 200 -10 -10 10 10 100 100 PMOS NMOS 10-12 10-12 0 0 DrainCurrent, I

-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 Drain Current, I -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 Gate Voltage, V [V] Drain Voltage, V [V] g d

Wfin = 10 nm; Tox = 2.1 nm

28 2002: 10 nm FinFETs

B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.‐Y. Yang, C. Tabery, SEM C. Hu, T.‐J. King, J. Bokor, M.‐R. Lin, and D. Kyser, image: "FinFET scaling to 10nm gate length," International Electron Devices Meeting Technical Digest, pp. 251‐254, 2002

Output Characteristics TEM images

• These devices were fabricated at AMD, using optical lithography.

29 Hole Mobility Comparison

Measured Field‐Effect Hole Mobility 160 • DG FET has higher hole 140 Vg-Vth=.8V mobility due to lower 120 <100> channel transverse electric field

/V-sec) 100 2 80 FinFET 60 • For the same gate 40 Bulk FET overdrive, hole mobility

Mobility(cm in DG‐FinFET is 2× that in 20 a control bulk FET 0 00.51 Effective Field (MV/cm)

30 FinFET Process Refinements

Y.‐K. Choi, L. Chang, P. Ranade, J. Lee, D. Ha, S. Balasubramanian, A. Agarwal, T.‐J. King, and J. Bokor, "FinFET process refinements for improved mobility and gate work function engineering," IEEE International Electron Devices Meeting Technical Digest, pp. 259‐262, 2002

Fin‐sidewall smoothening for Gate work function tuning

improved carrier mobilities for VTH adjustment

31 FinFET Reliability

Y.‐K. Choi, D. Ha, J. Bokor, and T.‐J. King, “Reliability study of CMOS FinFETs,” IEEE International Electron Devices Meeting Technical Digest, pp. 177‐180, 2003

Stress Bias Condition: Vg=Vd=2.0V 30 • Narrower fin  improved

[%] L =80nm g d 20 hot‐carrier (HC) immunity / I d I

 10

• HC lifetime and oxide QBD

0 are also improved by

[%] -10 T smoothening the Si fin / V T -20 W =18nm W =26nm sidewall surfaces (by H2 fin fin V

 W =34nm W =42nm fin fin annealing) -30 100 101 102 103 Stress Time [sec]

32 Tri‐Gate FET

Lg = 60 nm Wfin = 55 nm Hfin = 36 nm

B. Doyle et al. (Intel), IEEE Electron Device Letters, Vol. 24, pp. 263‐265, 2003 33 SOI Multi‐Gate MOSFET Designs

Tri‐Gate FET Relaxed fin dimensions

WSi > Lg/2; HSi > Lg/5

FinFET Narrow fin

WSi ~ Lg/2

body dimensions required for DIBL=100 mV/V eff L

/ Tox = 1.1nm Si H

UTB FET Ultra‐thin SOI WSi / Leff HSi ~ Lg/5 after Yang and Fossum, IEEE Trans. Electron Devices, Vol. 52, pp. 1159‐1164, 2005 34 Double‐Gate vs. Tri‐Gate FET

• The Double‐Gate FET does not require a highly selective gate etch, due to the protective dielectric hard mask. • Additional gate fringing capacitance is less of an issue for the Tri‐Gate FET, since the top fin surface contributes to current conduction in the ON state. Double‐Gate FET Tri‐Gate FET

channel

after M. Khare, 2010 IEDM Short Course 35 Independent Gate Operation • The gate electrodes of a double‐gate FET can be isolated by a masked etch, to allow for separate biasing. Drain – One gate is used for switching. Back‐ Gate1 Gated – The other gate is used for VTH control. Gate2 FET Source

D. M. Fried et al. (Cornell U.), IEEE Electron Device Letters, L. Mathew et al. (Freescale Semiconductor), Vol. 25, pp. 199‐201, 2004 2004 IEEE International SOI Conference 36 Bulk FinFET

• FinFETs can be made on bulk‐Si wafers lower cost improved thermal conduction with super‐steep retrograde well (SSRW) or “punch‐ through stopper” at the base of the fins

• 90 nm Lg FinFETs demonstrated

 Wfin = 80 nm  Hfin = 100 nm DIBL = 25 mV

C.‐H. Lee et al. (Samsung), Symposium on VLSI Technology Digest, pp. 130‐131, 2004 37 Bulk vs. SOI FinFET

(compared to SOI FinFET)

H. Bu (IBM), 2011 IEEE International SOI Conference 38 2004: High‐k/Metal Gate FinFET

D. Ha, H. Takeuchi, Y.‐K. Choi, T.‐J. King, W. Bai, D.‐L. Kwong, A. Agarwal, and M. Ameen,

“Molybdenum‐gate HfO2 CMOS FinFET technology,” IEEE International Electron Devices Meeting Technical Digest, pp. 643‐646, 2004

39 IDSAT Boost with Embedded‐SiGe S/D

Process flow:

IOFF vs. ION

• 25% improvement in IDSAT is achieved with silicon‐ Lg = 50 nm germanium source/drain, Wfin = 35 nm H = 65 nm due in part to reduced fin parasitic resistance

P. Verheyen et al. (IMEC), Symposium on VLSI Technology Digest, pp. 194‐195, 2005 40 Fin Design Considerations

• Fin Width Gate Length – Determines DIBL • Fin Height

– Limited by etch technology Source – Tradeoff: layout efficiency vs. design flexibility Drain • Fin Pitch – Determines layout area Fin Height Pfin – Limits S/D implant tilt angle Fin Width – Tradeoff: performance vs. layout efficiency

41 FinFET Layout

• Layout is similar to that of conventional MOSFET, except

that the channel width is quantized: Pfin

Source Source Gate Gate Drain Drain

Source Source Bulk‐Si MOSFET FinFET The S/D fins can be merged by selective epitaxy:

Intel M. Guillorn et al. (IBM), Symp. VLSI Technology 2008 Corp. 42 Impact of Fin Layout Orientation

• If the fin is oriented || or  to the wafer flat, the channel surfaces lie along (110) planes. – lower electron mobility – higher hole mobility • If the fin is oriented 45° to the (Series resistance is more wafer flat, the channel surfaces significant at shorter Lg.) lie along (100) planes.

L. Chang et al. (IBM), SISPAD 2004 43 FinFET‐Based SRAM Design Best Paper Award: Z. Guo, S. Balasubramanian, R. Zlatanovici, T.‐J. King, and B. Nikolic, “FinFET‐based SRAM design,” Int’l Symposium on Low Power Electronics and Design, pp. 2‐7, 2005 6‐T SRAM Cell Designs Cell Layouts Butterfly Curves

Reduced cell area with independently gated PGs

44 State‐of‐the‐Art FinFETs

22nm/20nm high‐performance CMOS technology

• Lg = 25 nm

XTEM Images of Fin

C.C. Wu et al. (TSMC), IEDM 2010 45 Looking to the Future…

2010 International Technology Roadmap for Semiconductors (ITRS) 2012 2014 2016 2018 2020 2022 2024 Gate Length 24 nm 18 nm 15 nm 13 nm 11 nm 10 nm 7 nm Gate Oxide

Thickness, TOX (nm)

Drive Current, IDSAT

End of Roadmap (always ~15 yrs away!)

46 FinFET vs. UTBB SOI MOSFET

Cross‐sectional TEM views of 25 nm UTB SOI devices

NFET TSi = 5 nm

PFET TSi = 5 nm

K. Cheng et al. (IBM), Symposium on VLSI B. Doris (IBM), 2011 *C.C. Wu et al. Technology Digest, pp. 128‐129, 2011 IEEE International (TSMC), IEDM SOI Conference 2010

47 Projections for FinFET vs. UTBB SOI MOSFETs

300 FDSOI Open: FinFET 250 Closed: FDSOI Open: FinFET

/V.s) Unstrained 2 Closed: FDSOI Longi. NMOS: 200 Trans. Vertical

Electron 150

Mobility Unstrained Unstrained Longi. FinFET Longi. Electron Mobility (cm Electron Trans. Trans. 100 Vertical Vertical

2x1012 4x1012 6x10128x10121013 2x1012 4x1012 6x10128x10121013 2x1012 4x1012 6x10128x10121013 -2 -2 -2 Inversion Charge Concentration (cm ) Inversion Charge Concentration (cm ) Inversion Charge Concentration (cm ) Technology Node: 20nm 14/16nm 10/12nm tSOI=7nm; tFIN=10nm tSOI=5nm; tFIN=7.5nm tSOI=3.5nm; tFIN=5nm 300 0 270 Unstrained FinFET Unstrained FinFET 0 Unstrained 240 Longi. Longi. 0 Longi. 210 Trans. Trans. 0 Trans. /V.s) 2 180 Vertical Vertical 0 Vertical PMOS: 150 0 FinFET Hole 120 0

FDSOI Mobility 90 0

Hole Mobility (cm Hole Mobility FDSOI 60 FDSOI 0

2x1012 4x1012 6x10128x10121013 2x1012 4x1012 6x10128x10121013 2x1012 4x1012 6x10128x10121013 -2 -2 -2 Inversion Charge Concentration (cm ) Inversion Charge Concentration (cm ) Inversion Charge Concentration (cm )

N. Xu et al. (UC‐Berkeley), IEEE Electron Device Letters, Vol. 33, pp. 318‐320, 2012 48 Remaining FinFET Challenges

• VTH adjustment

– Requires gate work‐function (WF) or Leff tuning

– Dynamic VTH control is not possible for high‐aspect‐ratio multi‐fin devices • Fringing capacitance between gate and top/bottom of S/D – Mitigated by minimizing fin pitch and using via‐contacted, merged S/D M. Guillorn, Symp. VLSI Technology 2008

• Parasitic resistance  Conformal doping is needed – Uniform S/D doping is e.g. Y. Sasaki, IEDM 2008 difficult to achieve with conventional implantation H. Kawasaki, IEDM 2008 • Variability – Performance is very sensitive to fin width – WF variation dominant for undoped channel T. Matsukawa, Symp. VLSI Technology 2008 49 Random Dopant Fluctuation Effects

• Channel/body doping can be eliminated to mitigate RDF effects. • However, due to source/drain doping, a trade‐off exists between

performance & RDF tolerance for Lg < 10nm:

SOI FinFET w/ atomistic IOFF and VT vs. TSi ION vs. TSi S/D gradient regions: 1E-4  = 3nm 100  = 3nm SD SD

m) 0.8 1E-6 75  m) 

50 (mV) (mA / VT ON (A /  1E-8 I 0.4

OFF 25 I

1E-10 0 4.5 5.5 6.5 4.5 5.5 6.5 T (nm) T (nm) Lg = 9nm, EOT = 0.7nm Si Si

V. Varadarajan et al. (UC-Berkeley), IEEE Silicon Nanoelectronics Workshop, 2006 50 Bulk vs. SOI Multi‐Gate FET Design

• To ease the fin width requirement, the fin height should be reduced. eff

L tri‐gate SOI (thick BOX)

/ [J.G. Fossum et al., IEDM 2004]

Si • The bulk tri‐gate design

H has the most relaxed body dimension requirements.  SSRW (at the base of the fin) improves electrostatic integrity WSi / Leff

X. Sun et al. (UC‐Berkeley), IEEE Electron Device Letters,Vol. 29, pp. 491‐493, 2008 51 SOI MOSFET Evolution

• The Gate‐All‐Around (GAA) structure provides for the greatest capacitive coupling between the gate and the channel.

http://www.electroiq.com/content/eiq-2/en/articles/sst/print/volume-51/issue-5/features/nanotechnology/fully-gate-all-around-silicon-nanowire-cmos-devices.html 52 Scaling to the End of the Roadmap

32 nm 22 nm beyond 10 nm planar multi‐gate stacked nanowires segmented channel 3‐D:

Intel Corp. quasi‐planar: C. Dupré et al. (CEA‐LETI) IEDM 2008 Stacked gate‐all‐around (GAA) FETs achieve the P. Packan et al. (Intel), IEDM 2009 highest layout efficiency. B. Ho (UCB), ISDRS 2011 53 Summary

• The FinFET was originally developed for manufacture of self‐aligned double‐gate MOSFETs, to address the need

for improved gate control to suppress IOFF, DIBL and process‐induced variability for Lg < 25nm. • Tri‐Gate and Bulk variations of the FinFET have been developed to improve manufacturability and cost. • It has taken ~10 years to bring “3‐D” transistors into volume production.

• Multi‐gate MOSFETs provide a pathway to achieving lower power and/or improved performance. • Further evolution of the MOSFET to a stacked‐channel structure may occur by the end of the roadmap.

54 Acknowledgments

• Collaborators at UC‐Berkeley

Profs. Hu, King, Bokor

Prof. Subramanian Digh Hisamoto Hideki Takeuchi Xuejue Huang Wen-Chin Lee Jakub Kedzierski

Yang‐Kyu Choi

Stephen Tang Leland Chang Nick Lindert

Sriram Kyoungsub Radu Balasubramanian Pushkar Ranade, Charles Kuo, Daewon Ha Peiqi Xuan Shin Zheng Guo Zlatanovici Prof. Nikolic • Early research funding: DARPA, SRC, AMD • UC Berkeley Microfabrication Laboratory (birthplace of the FinFET)

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