FinFET History, Fundamentals and Future Tsu‐Jae King Liu Department of Electrical Engineering and Computer Sciences University of California, Berkeley, CA 94720‐1770 USA June 11, 2012 2012 Symposium on VLSI Technology Short Course Impact of Moore’s Law Transistor Scaling Higher Performance, Investment Lower Cost Market Growth # DEVICES (MM) CMOS generation: 1 um • • 180 nm •• 32 nm YEAR Source: ITU, Mark Lipacis, Morgan Stanley Research http://www.morganstanley.com/institutional/techresearch/pdfs/2SETUP_12142009_RI.pdf 2 1996: The Call from DARPA • 0.25 m CMOS technology was state‐of‐the‐art • DARPA Advanced Microelectronics (AME) Program Broad Agency Announcement for 25 nm CMOS technology 1998 International Technology Roadmap for Semiconductors (ITRS) 1999 2002 2005 2008 2011 2014 2017 2020 Technology Node 180 130 100 70 50 35 25 18 nm nm nm nm nm nm nm nm Gate Oxide 1.9‐2.5 1.5‐1.9 1.0‐1.5 0.8‐1.2 0.6‐0.8 0.5‐0.6 Thickness, TOX (nm) Solutions No known Drive Current, IDSAT being pursued solutions End of Roadmap UC‐Berkeley project “Novel Fabrication, Device Structures, and Physics of 25 nm FETs for Terabit‐Scale Electronics” • June 1997 through July 2001 3 MOSFET Fundamentals Metal Oxide Semiconductor 0.25 micron MOSFET XTEM Field‐Effect Transistor: GATE LENGTH, Lg Gate Source Drain Si substrate http://www.eetimes.com/design/automotive‐design/4003940/LCD‐driver‐highly‐integrated GATE OXIDE THICKNESS, Tox 4 MOSFET Operation: Gate Control Desired N‐channel MOSFET • Current between Source and Drain characteristics: cross‐section is controlled by the Gate voltage. • High ON current Gate • Low OFF current • “N‐channel” & “P‐channel” MOSFETs gate oxide Leff operate in a complementary manner N+ P N+ “CMOS” = Complementary MOS Source Body Drain log ID Electron Energy Band Profile ION n(E) exp (‐E/kT) E CURRENT Inverse slope is subthreshold swing, S Sourceincreasing IOFF DRAIN [mV/dec] GATE VOLTAGE increasing 0 V Drain VTH GS V distance DD 5 CMOS Devices and Circuits CIRCUIT SYMBOLS CMOS INVERTER CIRCUIT V INVERTER N‐channel P‐channel VDD OUT LOGIC SYMBOL MOSFET MOSFET S G G VDD D VIN VOUT S D S D D S GND VIN 0 V CMOS NAND GATE DD STATIC MEMORY (SRAM) CELL NOT AND (NAND) WORD LINE TRUTH TABLE 0 1 or or BIT LINE 1 0 BIT LINE 6 Improving the ON/OFF Current Ratio Gate log I D ION C ox Ctotal C S dep Cox Source Body Drain VDD VGS • The greater the capacitive coupling between Gate and channel, the better control the Gate has over the channel potential. higher ION/IOFF for fixed VDD, or lower VDD to achieve target ION/IOFF reduced drain‐induced barrier lowering (DIBL): log ID increasing VDS increasing Drain Source IOFF VDS VGS 7 MOSFET in ON State (VGS > VTH) width velocity inversion‐layer charge density I D W vQinv gate‐oxide capacitance v eff Qinv Cox (VGS VTH ) mobility gate overdrive D I Gate CURRENT, Source Drain DRAIN Substrate DRAIN VOLTAGE, VDS 8 Effective Drive Current (IEFF) CMOS inverter chain: V V V V DD 1 2 3 V2 tpLH IH + IL V /2 V3 DD IEFF = V tpHL 2 1 TIME I IH (DIBL = 0) DSAT VDD VIN = VDD S D IH VIN = 0.83VDD V VOUT CURRENT IN D V = 0.75V S IN DD GND DRAIN IL VIN = 0.5VDD NMOS 0.5VDD VDD NMOS DRAIN VOLTAGE = VOUT M. H. Na et al. (IBM), IEDM Technical Digest, pp. 121‐124, 2002 9 CMOS Technology Scaling XTEM images with the same scale courtesy V. Moroz (Synopsys, Inc.) 90 nm node 65 nm node 45 nm node 32 nm node T. Ghani et al., (after S. Tyagi et al., IEDM 2005) K. Mistry et al., P. Packan et al., IEDM 2003 IEDM 2007 IEDM 2009 • Gate length has not scaled proportionately with device pitch (0.7x per generation) in recent generations. – Transistor performance has been boosted by other means. 10 MOSFET Performance Boosters • Strained channel regions eff • High‐k gate dielectric and metal gate electrodes Cox Cross‐sectional TEM views of Intel’s 32 nm CMOS devices P. Packan et al. (Intel), IEDM Technical Digest, pp. 659‐662, 2009 11 Process‐Induced Variations • Sub‐wavelength lithography: – Resolution enhancement techniques are costly and increase process sensitivity • Gate line‐edge roughness: courtesy Mike Rieger (Synopsys, Inc.) photoresist • Random dopant fluctuations (RDF): – Atomistic effects become significant in nanoscale FETs A. Brown et al., SiO2 Gate IEEE Trans. Nanotechnology, p. 195, 2002 Source Drain A. Asenov, Symp. VLSI Tech. Dig., p. 86, 2007 12 A Journey Back through Time… Why New Transistor Structures? • Off‐state leakage (IOFF) must be suppressed as Lg is scaled down – allows for reductions in VTH and hence VDD • Leakage occurs in the region away from the channel surface Let’s get rid of it! Lg Ultra‐Thin‐Body MOSFET: Gate SourceSource DrainDrain “Silicon‐on‐ Buried Oxide Insulator” (SOI) Substrate Wafer 14 Thin‐Body MOSFETs • IOFF is suppressed by using an adequately thin body region. – Body doping can be eliminated higher drive current due to higher carrier mobility Reduced impact of random dopant fluctuations (RDF) Ultra‐Thin Body (UTB) Double‐Gate (DG) Lg Gate Gate Source Drain Source Drain TSi TSi Buried Oxide Gate Substrate TSi < (1/4) Lg TSi < (2/3) Lg B. Yu et al., ISDRS 1997 R.‐H. Yan et al., IEEE TED 1992 15 Effect of TSi on Leakage Lg = 25 nm; Tox,eq = 12Å TSi = 10 nm TSi = 20 nm 6 10 G Si Thickness [nm] G 0.0 SD4.0 3x102 8.0 12.0 SD G 16.0 10‐1 20.0 Leakage Current G 2 Density [A/cm ] @ VDS = 0.7 V Ioff = 2.1 nA/ m Ioff = 19 A/ m 16 Double‐Gate MOSFET Structures PLANAR: VERTICAL FIN: L. Geppert, IEEE Spectrum, October 2002 17 DELTA MOSFET D. Hisamoto, T. Kaga, Y. Kawamoto, and E. Takeda (Hitachi Central Research Laboratory), “A fully depleted lean‐channel transistor (DELTA) –a novel vertical ultrathin SOI MOSFET,” IEEE Electron Device Letters Vol. 11, pp. 36‐39, 1990 • Improved gate control Wl = 0.4 m observed for Wg < 0.3 m – Leff= 0.57 m 18 Double‐Gate FinFET • Self‐aligned gates straddle narrow silicon fin • Current flows parallel to wafer surface Gate Length, Lg S G G Gate 2 D Source Gate 1 Current Flow Fin Height, H Drain fin Fin Width, Wfin 19 1998: First N‐channel FinFETs D. Hisamoto, W.‐C. Lee, J. Kedzierski, E. Anderson, H. Takeuchi, K. Asano, T.‐J. King, J. Bokor, and C. Hu, “A folded‐channel MOSFET for deep‐sub‐tenth micron era,” IEEE International Electron Devices Meeting Technical Digest, pp. 1032‐1034, 1998 Plan View Lg = 30 nm Wfin = 20 nm Hfin = 50 nm Lg = 30 nm Wfin = 20 nm Hfin = 50 nm • Devices with Lg down to 17 nm were successfully fabricated 20 1999: First P‐channel FinFETs X. Huang, W.‐C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.‐K. Choi, K. Asano, V. Subramanian, T.‐J. King, J. Bokor, and C. Hu, “Sub 50‐nm FinFET: PMOS,” IEEE International Electron Devices Meeting Technical Digest, pp. 67‐70, 1999 Lg = 18 nm Wfin = 15 nm Hfin = 50 nm Transmission Electron Micrograph 21 2000: Vested Interest from Industry • Semiconductor Research Corporation (SRC) &AMD fund project: – Development of a FinFET process flow compatible with a conventional planar CMOS process – Demonstration of the compatibility of the FinFET structure with a production environment (October 2000 through September 2003) • DARPA/SRC Focus Center Research Program funds projects: – Approaches for enhancing FinFET performance (MSD Center, April 2001 through August 2003) – FinFET‐based circuit design (C2S2 Center, August 2003 through July 2006) 22 FinFET Structures Original: Gate‐last Gate process flow Source Si FinDrain Gate Improved: Gate‐first process flow Source Drain 23 Fin Width Requirement Measured FinFET DIBL • To adequately suppress DIBL, Lg/Wfin > 1.5 Challenge for lithography! N. Lindert et al. (UC‐Berkeley), IEEE Electron Device Letters, Vol. 22, pp. 487‐489, 2001 24 Sub‐Lithographic Fin Patterning Spacer Lithography a.k.a. Sidewall Image Transfer (SIT) and Self‐Aligned Double Patterning (SADP) 1. Deposit & pattern sacrificial layer 3. Etch back mask layer to form “spacers” SOI SOI BOX BOX 4. Remove sacrificial layer; 2. Deposit mask layer (SiO or Si N ) 2 3 4 etch SOI layer to form fins SOI fins BOX BOX Note that fin pitch is 1/2 that of patterned layer 25 Benefits of Spacer Lithography • Spacer litho. provides for better CD control and uniform fin width SEM image of FinFET with spacer‐defined fins: Y.‐K. Choi et al. (UC‐Berkeley), IEEE Trans. Electron Devices, Vol. 49, pp. 436‐441, 2002 26 Spacer‐Defined FinFETs Y.‐K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.‐J. King, J. Bokor, and C. Hu, "Sub‐20nm CMOS FinFET technologies,” IEEE International Electron Devices Meeting Technical Digest, pp. 421‐424, 2001 Lg = 60 nm, Wfin = 40 nm Transfer Characteristics Output Characteristics 27 2001: 15 nm FinFETs Y.‐K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.‐J. King, J. Bokor, C. Hu, "Sub‐20nm CMOS FinFET technologies,” IEEE International Electron Devices Meeting Technical Digest, pp. 421‐424, 2001 Transfer Characteristics Output Characteristics 10-2 10-2 600 600 V =1.0 V V =-1.0 V P+Si Ge d d 0.4 0.6 |V -V|=1.2V NMOS -4 Gate -4 500 PMOS g t 500 10 10 [A/um] [uA/um] d V =0.05 V d 400 400 -6 V =-0.05 V d -6 Voltage step 10 d 10 300 : 0.2V 300 -8 N-body= -8 10 10 2x1018cm-3 200 200 -10 -10 10 10 100 100 PMOS NMOS 10-12 10-12 0 0 Drain Current, I -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 Drain Current, I -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 Gate Voltage, V [V] Drain Voltage, V [V] g d Wfin = 10 nm; Tox = 2.1 nm 28 2002: 10 nm FinFETs B.