Logic Design with Mosfets

Logic Design with MOSFETs

Dae Hyun Kim

EECS Washington State University References

• John P. Uyemura, “Introduction to VLSI Circuits and Systems,” 2002. – Chapter 2 • Neil H. Weste and David M. Harris, “CMOS VLSI Design: A Circuits and Systems Perspective,” 2011. – Chapter 1 Goal

• Design logic gates using MOSFETs (NMOS and PMOS) Signals and Wires

• Signals – 0 = = Ground = GND = Low = 0V – 1 = = Power = PWR = High = 5V, 3.3V, 1.5V, 1.2V, 1.0V, etc. 𝑉𝑉𝑆𝑆𝑆𝑆

𝑉𝑉𝐷𝐷𝐷𝐷

• Wires

Wire 1 a

b Wire 2 a a

a a

No connection Connection Ideal Switches

• Switch Control Control

𝑥𝑥Electrically open𝑦𝑦 𝑥𝑥Electrically short𝑦𝑦 • Assert-high switch = =

𝑨𝑨 𝟎𝟎 𝑨𝑨 𝟏𝟏 = Open ( is undefined) Closed ( = ) 𝑥𝑥 𝑦𝑦 𝑥𝑥 𝑦𝑦 𝑥𝑥 • Assert-low switch𝑦𝑦 𝒚𝒚 𝒙𝒙 = =

𝑨𝑨 𝟎𝟎 = 𝑨𝑨 𝟏𝟏 Closed ( = ) Open ( is undefined) 𝑥𝑥 𝑦𝑦 𝑥𝑥 𝑥𝑥 𝑦𝑦 𝒚𝒚 𝒙𝒙 𝑦𝑦 Series/Parallel Connections of Switches

• Series a b y

0 0 𝑎𝑎 𝑏𝑏 = = ( ) 0 1 undefined

𝑥𝑥 AND operation𝑦𝑦 𝑥𝑥 ∙ 𝑎𝑎 ∙ 𝑏𝑏 𝑥𝑥 ∙ 𝑎𝑎 ∙ 𝑏𝑏 1 0 𝑥𝑥 ∙ 𝑎𝑎 ( is defined only when = 1 and = 1) 1 1 ( is undefined if = 0 or = 0) 𝑦𝑦 𝑎𝑎 𝑏𝑏 • Parallel 𝑥𝑥 𝑦𝑦 𝑎𝑎 𝑏𝑏

a b y 𝑎𝑎 0 0 undefined + = ( + ) 0 1 𝑏𝑏 𝑥𝑥 𝑥𝑥 ∙ 𝑎𝑎 𝑥𝑥 ∙ 𝑏𝑏 𝑥𝑥 ∙ 𝑎𝑎 𝑏𝑏 1 0 OR operation 1 1 ( is defined only when = 1 or = 1) 𝑥𝑥 ( is undefined if = 0 and = 0) 𝑦𝑦 𝑎𝑎 𝑏𝑏 𝑦𝑦 𝑎𝑎 𝑏𝑏 Inverter Design with Switches

• Inverter – The output is defined both when = 0 and when = 1.

𝑎𝑎 𝑎𝑎

1 1 a y 𝑎𝑎 ∙ 𝑎𝑎� 0 1 = 1 + 0 = 1 0 0 𝑎𝑎 𝑦𝑦 ∙ 𝑎𝑎� ∙ 𝑎𝑎 𝑎𝑎� 0

∙ 𝑎𝑎 Inverter Design with Switches

• Two inverter designs

1 𝑎𝑎

0 𝑎𝑎 𝑦𝑦

0 𝑎𝑎�

Why?

1 𝑎𝑎� 𝑦𝑦 MOSFETs as Switches

• MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor – n-channel MOSFET = nFET = NMOS – p-channel MOSFET = pFET = PMOS – Complementary MOS: CMOS

• Symbols

Gate Gate 𝑉𝑉𝐺𝐺 𝑉𝑉𝐺𝐺

Source Drain Drain Source 𝑉𝑉𝑆𝑆 𝑉𝑉𝐷𝐷 𝑉𝑉𝐷𝐷 𝑉𝑉𝑆𝑆 nFET pFET = =

( ) ( )

𝑉𝑉𝐷𝐷 ≥ 𝑉𝑉𝑆𝑆 𝑉𝑉𝑆𝑆 ≥ 𝑉𝑉𝐷𝐷 MOSFETs as Switches

• Threshold voltage – nFET: > 0

– pFET: 𝑛𝑛 < 0 𝑉𝑉𝑇𝑇 𝑉𝑉𝑇𝑇𝑝𝑝

Drain • nFET 𝑉𝑉𝐴𝐴 – OFF: = 1: Mn ON Gate Mn 𝑉𝑉𝐷𝐷𝐷𝐷

– ON: 𝑛𝑛> 𝑛𝑛 𝐴𝐴 𝐺𝐺𝐺𝐺 𝑇𝑇 Source = 0: Mn OFF 𝑉𝑉 ≤ 𝑉𝑉 𝑇𝑇0𝑛𝑛 𝑉𝑉𝐴𝐴 𝑉𝑉 𝑉𝑉𝐺𝐺𝐺𝐺𝑛𝑛 𝑉𝑉𝑇𝑇𝑛𝑛 Logic translation𝐴𝐴

• Example (PTM High-Performance 45nm High-K Metal Gate) – : 1.0V – : 0.46893V 𝑉𝑉𝐷𝐷𝐷𝐷 – : -0.49158V 𝑉𝑉𝑇𝑇𝑛𝑛 𝑉𝑉𝑇𝑇𝑝𝑝 • Example (PTM High-Performance 32nm High-K Metal Gate) – : 0.9V – : 0.49396V 𝑉𝑉𝐷𝐷𝐷𝐷 – : -0.49155V 𝑉𝑉𝑇𝑇𝑛𝑛 𝑉𝑉𝑇𝑇𝑝𝑝 • Example (PTM High-Performance 22nm High-K Metal Gate) – : 0.8V – : 0.50308V 𝑉𝑉𝐷𝐷𝐷𝐷 – : -0.4606V 𝑉𝑉𝑇𝑇𝑛𝑛 𝑉𝑉𝑇𝑇𝑝𝑝 Pass Characteristics

• nFET ↑ ↓ ↑ = 𝑽𝑽𝒊𝒊𝒊𝒊0 𝑽𝑽𝑮𝑮𝑮𝑮 𝑽𝑽𝒐𝒐𝒐𝒐𝒐𝒐0 Logic 0 transfer: strong logic 0 𝑉𝑉𝐷𝐷 𝑉𝑉𝑖𝑖𝑖𝑖 = 0.1 𝑉𝑉𝐷𝐷𝐷𝐷 - 0.1 0.1 ... 𝐷𝐷𝐷𝐷...... 𝑉𝑉𝐺𝐺 𝑉𝑉𝐷𝐷𝐷𝐷 𝑉𝑉 =

𝑆𝑆 𝑜𝑜𝑜𝑜𝑜𝑜 𝑉𝑉 𝑉𝑉 𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑉𝑉 𝑇𝑇𝑛𝑛 𝑉𝑉𝑇𝑇𝑛𝑛 𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑉𝑉𝑇𝑇𝑛𝑛 Logic 1 transfer: weak logic 1 • pFET 𝑉𝑉𝐷𝐷𝐷𝐷 𝑉𝑉𝑇𝑇𝑛𝑛 𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑉𝑉𝑇𝑇𝑛𝑛

= ↓ ↓ ↓ 𝑆𝑆 𝑖𝑖𝑖𝑖 = 0 𝑉𝑉 𝑉𝑉 𝑽𝑽𝒊𝒊𝒊𝒊 𝑽𝑽𝑺𝑺𝑺𝑺 𝑽𝑽𝒐𝒐𝒐𝒐𝒐𝒐 Logic 1 transfer: strong logic 1 𝐺𝐺 𝑉𝑉 𝑉𝑉𝐷𝐷𝐷𝐷 𝑉𝑉𝐷𝐷𝐷𝐷 𝑉𝑉𝐷𝐷𝐷𝐷 = 𝑉𝑉𝐷𝐷𝐷𝐷...− 𝜀𝜀 𝑉𝑉𝐷𝐷𝐷𝐷...− 𝜀𝜀 𝑉𝑉𝐷𝐷𝐷𝐷...− 𝜀𝜀 𝐷𝐷 𝑜𝑜𝑜𝑜𝑜𝑜 𝑉𝑉 𝑉𝑉 | | | | 𝑇𝑇𝑝𝑝 𝑇𝑇𝑝𝑝 𝑉𝑉0 𝑉𝑉𝑇𝑇0𝑝𝑝 |𝑉𝑉 | Logic 0 transfer: weak logic 0

𝑉𝑉𝑇𝑇𝑝𝑝 Pass Characteristics

• SPICE simulation (45nm technology) – nFET

𝑉𝑉𝑖𝑖𝑖𝑖

𝑉𝑉𝐷𝐷𝐷𝐷

𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 Pass Characteristics

• SPICE simulation (45nm technology) – pFET

𝑉𝑉𝑖𝑖𝑖𝑖 0

𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 Pass Characteristics

• nFET – Strong logic 0 transfer – Weak logic 1 transfer

• pFET – Strong logic 1 transfer – Weak logic 0 transfer

• CMOS – Use pFETs to pass logic 1. – Use nFETs to pass logic 0. Basic Logic Gates in CMOS

• Principles – Construct the nFET network using only nFETs and the pFET network using only pFETs. – If the output is 1, the pFET network connects to the output and the nFET network disconnects and the output. 𝑉𝑉𝐷𝐷𝐷𝐷 – If the output is 0, the nFET network connects to the output and the 𝑉𝑉𝑆𝑆𝑆𝑆 pFET network disconnects and the output. 𝑉𝑉𝑆𝑆𝑆𝑆 𝑉𝑉𝐷𝐷𝐷𝐷 𝑉𝑉𝐷𝐷𝐷𝐷 pFET network

, , , … (inputs) (output)

𝑎𝑎 𝑏𝑏 𝑐𝑐 𝑓𝑓 nFET network Basic Logic Gates in CMOS

• Inverter

# TRs: 2 = nFET: 1 pFET: 1 𝑥𝑥 𝑓𝑓 𝑥𝑥̅

off 0 = 1 1 = 0

off 𝑓𝑓 𝑓𝑓

= 1 + 0 =

𝑓𝑓 𝑥𝑥̅ ∙ 𝑥𝑥 ∙ 𝑥𝑥̅ Basic Logic Gates in CMOS

• SPICE simulation Basic Logic Gates in CMOS

• Two-input NAND (NAND2)

= # TRs: 4 nFETs: 2 𝑎𝑎 𝑓𝑓 𝑎𝑎 ∙ 𝑏𝑏 pFETs: 2

𝑏𝑏 off off off 0 = 1 0 = 1 1 = 0 off off 𝑓𝑓 𝑓𝑓 𝑓𝑓

0 off 1 1

= 1 + 1 + 1 + 0 = + =

𝑓𝑓 𝑎𝑎� ∙ 𝑏𝑏� ∙ 𝑎𝑎� ∙ 𝑏𝑏 ∙ 𝑎𝑎 ∙ 𝑏𝑏� ∙ 𝑎𝑎 ∙ 𝑏𝑏 ∙ 𝑎𝑎� 𝑏𝑏� 𝑎𝑎 ∙ 𝑏𝑏 Basic Logic Gates in CMOS

• SPICE simulation Basic Logic Gates in CMOS

• Two-input NOR (NOR2)

# TRs: 4 𝑏𝑏 nFETs: 2 = + pFETs: 2 𝑎𝑎

𝑓𝑓 𝑎𝑎 𝑏𝑏 𝑎𝑎 𝑏𝑏 0 1 1 off

0 0 off 1 off = 1 = 0 = 0 0 off 0 off 0 off 1 1 1 𝑓𝑓 𝑓𝑓 𝑓𝑓

= 1 + 0 + 0 + 0 = = +

𝑓𝑓 𝑎𝑎� ∙ 𝑏𝑏� ∙ 𝑎𝑎� ∙ 𝑏𝑏 ∙ 𝑎𝑎 ∙ 𝑏𝑏� ∙ 𝑎𝑎 ∙ 𝑏𝑏 ∙ 𝑎𝑎� ∙ 𝑏𝑏� 𝑎𝑎 𝑏𝑏 Basic Logic Gates in CMOS

• SPICE simulation Complex Logic Gates in CMOS

• Example = ( + )

• Using logic gates 𝑓𝑓 𝑎𝑎 ∙ 𝑏𝑏 𝑐𝑐

# TRs: 14 nFETs: 7 pFETs: 7 𝑏𝑏 𝑐𝑐 𝑓𝑓 • Using logic gates 𝑎𝑎 # TRs: 10

nFETs: 5 𝑏𝑏 pFETs: 5 𝑐𝑐 𝑓𝑓 • Using TRs 𝑎𝑎 # TRs: 6 nFETs: 3 pFETs: 3 Complex Logic Gates in CMOS

• How to design – Inverter = = 1 + 0 = pFET network nFET network (connects 1 and𝑓𝑓 the𝑥𝑥 output)̅ 𝑥𝑥̅ ∙ (connects𝑥𝑥 ∙ 0 and the output) 𝑥𝑥 𝑓𝑓 𝑥𝑥̅ – NAND2 = = 1 + 0 = ( + ) 1 + 0 pFET network nFET network 𝑓𝑓 𝑎𝑎 ∙ 𝑏𝑏 𝑎𝑎 ∙ 𝑏𝑏(expressed∙ 𝑎𝑎 by∙ 𝑏𝑏 ∙and ) 𝑎𝑎� 𝑏𝑏� ∙ 𝑎𝑎 ∙ 𝑏𝑏(expressed∙ by and ) ( + ) 𝑎𝑎� 𝑏𝑏� 𝑎𝑎 𝑏𝑏 � 𝑎𝑎� 𝑏𝑏 =

𝑎𝑎 𝑓𝑓 𝑎𝑎 ∙ 𝑏𝑏 ( )

𝑎𝑎 ∙ 𝑏𝑏 𝑏𝑏 Complex Logic Gates in CMOS

• How to design – Express = 1 + 0 = ( , … , ) 1 + ( , … , ) 0 𝑓𝑓 – Design a pFET network using A = ( , … , ). 𝑓𝑓 𝐴𝐴 ∙ 𝐵𝐵 ∙ 𝐹𝐹 𝑥𝑥1 𝑥𝑥𝑛𝑛 ∙ 𝐹𝐹 𝑥𝑥1 𝑥𝑥𝑛𝑛 ∙ • pFETs are ON when the inputs are 0. 𝐹𝐹 𝑥𝑥1 𝑥𝑥𝑛𝑛 – Design an nFET network using B = ( , … , ). • nFETs are ON when the inputs are 1. 𝐹𝐹 𝑥𝑥1 𝑥𝑥𝑛𝑛 • Example = ( + ) = ( + ) 1 + + 0 = ( + ) 1 + + 0 – 𝑓𝑓 𝑎𝑎 ∙ 𝑏𝑏 𝑐𝑐 pFET network nFET network 𝑓𝑓 𝑎𝑎 ∙ 𝑏𝑏 𝑐𝑐 ∙ 𝑎𝑎 ∙ 𝑏𝑏 𝑐𝑐 ∙ 𝑎𝑎� 𝑏𝑏� ∙ 𝑐𝑐̅ ∙ 𝑎𝑎 ∙ 𝑏𝑏 𝑐𝑐 ∙

𝑏𝑏 𝑎𝑎

𝑎𝑎 𝑐𝑐 𝑏𝑏 𝑐𝑐 Complex Logic Gates in CMOS

• Example = ( + )

𝑓𝑓 𝑎𝑎 ∙ 𝑏𝑏 𝑐𝑐

𝑏𝑏

𝑎𝑎 # TRs: 6

𝑐𝑐 nFETs: 3 pFETs: 3 𝑓𝑓

𝑎𝑎

𝑏𝑏 𝑐𝑐 Complex Logic Gates in CMOS

• Structured logic design – Design a given Boolean equation using nFETs and pFETs.

• Assume that only non-inverted input signals are given. – , , , … are given. – , , , … are not given. If you need them, you should generate them. 𝑎𝑎 𝑏𝑏 𝑐𝑐 𝑎𝑎� 𝑏𝑏� 𝑐𝑐̅ Complex Logic Gates in CMOS

• Design methodology 1 – When = ( , … , ) ( is a function of non-inverted variables) • = = 1 + 0 1 𝑛𝑛 • Design𝑓𝑓 an𝑆𝑆 𝑥𝑥 nFET 𝑥𝑥network𝑆𝑆 for using , … , . 𝑓𝑓 𝑆𝑆̅ 𝑆𝑆̅ ∙ 𝑆𝑆 ∙ • Design a pFET network for using , … , . 𝑆𝑆 𝑥𝑥1 𝑥𝑥𝑛𝑛 • Connect them to , , . 𝑆𝑆̅ 𝑥𝑥1 𝑥𝑥𝑛𝑛 𝑎𝑎 = ( + ) – Example: 𝑉𝑉𝐷𝐷𝐷𝐷 𝑉𝑉𝑆𝑆𝑆𝑆 𝑓𝑓 • = ( + ) 1 + a ( + ) 0 𝑓𝑓 𝑎𝑎 ∙ 𝑏𝑏 𝑐𝑐 𝑏𝑏 𝑐𝑐 • Design an nFET network for a ( + ). 𝑓𝑓 𝑎𝑎 ∙ 𝑏𝑏 𝑐𝑐 ∙ ∙ 𝑏𝑏 𝑐𝑐 ∙ • Design a pFET network for ( + ) = + . ∙ 𝑏𝑏 𝑐𝑐 • Connect them. 𝑎𝑎 ∙ 𝑏𝑏 𝑐𝑐 𝑎𝑎� 𝑏𝑏� ∙ 𝑐𝑐̅ 𝑏𝑏

𝑎𝑎 𝑐𝑐 Complex Logic Gates in CMOS

• Design methodology 2 – When = ( , … , ) • = = 1 + 0 1 𝑛𝑛 • Design𝑓𝑓 an𝑆𝑆 𝑥𝑥 nFET 𝑥𝑥network for . 𝑓𝑓 𝑆𝑆̅ 𝑆𝑆̅ ∙ 𝑆𝑆 ∙ • Design a pFET network with a dual logic of the nFET network. 𝑆𝑆 – Dual of , … , , 0,1, , = ( , … , , 1,0, , )

• Connect them.𝑓𝑓 𝑥𝑥 1 𝑥𝑥𝑛𝑛 𝐴𝐴𝐴𝐴𝐴𝐴 𝑂𝑂𝑂𝑂 𝑓𝑓 𝑥𝑥1 𝑥𝑥𝑛𝑛 𝑂𝑂𝑂𝑂 𝐴𝐴𝐴𝐴𝐴𝐴 – Example: = ( + ) 𝑎𝑎

• = ( + ) 1 + a ( + ) 0 𝑓𝑓 𝑎𝑎 ∙ 𝑏𝑏 𝑐𝑐 • Design an nFET network for a ( + ). 𝑓𝑓 𝑎𝑎 ∙ 𝑏𝑏 𝑐𝑐 ∙ ∙ 𝑏𝑏 𝑐𝑐 ∙ 𝑏𝑏 𝑐𝑐 • Dual of + = + = + . ∙ 𝑏𝑏 𝑐𝑐 • Connect them. 𝑎𝑎 ∙ 𝑏𝑏 𝑐𝑐 𝑎𝑎 𝑏𝑏 ∙ 𝑐𝑐 𝑎𝑎 𝑏𝑏 ∙ 𝑐𝑐

𝑏𝑏

𝑎𝑎 𝑐𝑐 Complex Logic Gates in CMOS

• Dual logic – , … , , 0,1, , = ( , … , , 1,0, , ) – Example 𝐷𝐷 𝑓𝑓 𝑥𝑥1 𝑥𝑥𝑛𝑛 𝐴𝐴𝐴𝐴𝐴𝐴 𝑂𝑂𝑂𝑂 𝑓𝑓 𝑥𝑥1 𝑥𝑥𝑛𝑛 𝑂𝑂𝑂𝑂 𝐴𝐴𝐴𝐴𝐴𝐴 • ( ) = + • ( + 𝐷𝐷) = 𝐴𝐴 ∙ 𝐵𝐵 𝐴𝐴 𝐵𝐵 • (1 ) =𝐷𝐷 0 + = 𝐴𝐴 𝐵𝐵 𝐴𝐴 ∙ 𝐵𝐵 • (1 + 𝐷𝐷) = 0 = 0 ∙ 𝐴𝐴 𝐴𝐴 𝐴𝐴 • (0 ) 𝐷𝐷= 1 + =1 𝐴𝐴 ∙ 𝐴𝐴 • (0 + 𝐷𝐷) = 1 = ∙ 𝐴𝐴 𝐴𝐴 𝐷𝐷 • Principles of𝐴𝐴 the dual∙ 𝐴𝐴 logic𝐴𝐴 – The nFET and the pFET networks work complementarily. – If the nFET network is ON (i.e., connects to the output), the pFET network is OFF (i.e., disconnect the output from ) and vice versa. 𝑉𝑉𝑆𝑆𝑆𝑆 – If two networks are dual, they work complementarily. 𝑉𝑉𝐷𝐷𝐷𝐷 • Prove! Complex Logic Gates in CMOS

• Principles of the dual logic – = ( , … , ) = = ( , … , ) 1 + ( , … , ) 0 – ( , … , ) = ( , … , , 0,1, , ) = , … , , 1,0, , = 𝑓𝑓 𝑆𝑆 𝑥𝑥1 𝑥𝑥𝑛𝑛 𝑓𝑓 𝑆𝑆 𝑥𝑥1 𝑥𝑥𝑛𝑛 ∙ 𝑆𝑆 𝑥𝑥1 𝑥𝑥𝑛𝑛 ∙ ( , … , ) (De Morgan’s law) 1 𝑛𝑛 1 𝑛𝑛 1 𝑛𝑛 – A𝑆𝑆 pFET𝑥𝑥 is𝑥𝑥 ON𝐷𝐷 𝑆𝑆when𝑥𝑥 its𝑥𝑥 control𝐴𝐴𝐴𝐴𝐴𝐴 variable𝑂𝑂𝑂𝑂 ( )𝑆𝑆 is𝑥𝑥 0. 𝑥𝑥 𝑂𝑂𝑂𝑂 𝐴𝐴𝐴𝐴𝐴𝐴 𝑆𝑆 𝑥𝑥1 𝑥𝑥𝑛𝑛 – Thus, the pFET network is the dual of the nFET network. 𝑥𝑥𝑖𝑖 Complex Logic Gates in CMOS

• Design methodology 3 – When = ( , … , ) ( is a function of non-inverted variables) • = = 𝑓𝑓 𝑆𝑆 𝑥𝑥1 𝑥𝑥𝑛𝑛 𝑆𝑆 • Design and add an inverter at the output. 𝑓𝑓 𝑆𝑆 𝑆𝑆̅ – Example: = ( + ) 𝑆𝑆̅ • = + = ( + ) 𝑓𝑓 𝑎𝑎 ∙ 𝑏𝑏 𝑐𝑐 • Design ( + ). 𝑓𝑓 𝑎𝑎 ∙ 𝑏𝑏 𝑐𝑐 𝑎𝑎 ∙ 𝑏𝑏 𝑐𝑐 𝑏𝑏 • Add an inverter at the output. 𝑎𝑎 ∙ 𝑏𝑏 𝑐𝑐 𝑎𝑎

𝑐𝑐 𝑓𝑓

𝑎𝑎

𝑏𝑏 𝑐𝑐 Complex Logic Gates in CMOS

• Design methodology 4 – When = ( , … , ) ( is a function of inverted variables) • Generate inverted inputs ( , … , ) from the given inputs ( , … , ). 1 𝑛𝑛 • Design𝑓𝑓 𝑆𝑆 using𝑥𝑥 the𝑥𝑥 inverted𝑆𝑆 inputs. 𝑥𝑥1 𝑥𝑥𝑛𝑛 𝑥𝑥1 𝑥𝑥𝑛𝑛 – Example: 𝑆𝑆= ( + ) • Inverters are not shown for brevity. 𝑓𝑓 𝑎𝑎� ∙ 𝑏𝑏� 𝑐𝑐̅

𝑏𝑏�

𝑎𝑎�

𝑐𝑐̅ 𝑓𝑓

𝑎𝑎�

𝑏𝑏� 𝑐𝑐̅ Complex Logic Gates in CMOS

• Design methodology 5 – When = ( , … , ) • = ( , … , ) = ( , … , ) = ( , … , ) 𝑓𝑓 𝑆𝑆 𝑥𝑥1 𝑥𝑥𝑛𝑛 • Design ( , … , ) using the𝐷𝐷 given inputs. 𝐷𝐷 𝑓𝑓 𝑆𝑆 𝑥𝑥1 𝑥𝑥𝑛𝑛 𝑆𝑆 𝑥𝑥1 𝑥𝑥𝑛𝑛 𝑆𝑆 𝑥𝑥1 𝑥𝑥𝑛𝑛 • Add an inverter at the𝐷𝐷 output. 𝑆𝑆 𝑥𝑥1 𝑥𝑥𝑛𝑛 – Example: = + ( )

• = ( + ) = � ( + ) 𝑏𝑏 𝑓𝑓 𝑎𝑎� 𝑏𝑏 ∙ 𝑐𝑐̅ 𝑓𝑓 𝑎𝑎 ∙ 𝑏𝑏 𝑐𝑐 𝑎𝑎 ∙ 𝑏𝑏 𝑐𝑐 𝑎𝑎

𝑐𝑐 𝑓𝑓

𝑎𝑎

𝑏𝑏 𝑐𝑐 Complex Logic Gates in CMOS

• Design methodology 6 – When = ( , … , ) • = = 𝑓𝑓 𝑆𝑆 𝑥𝑥1 𝑥𝑥𝑛𝑛 • Generate inverted inputs ( , … , ) from the given inputs ( , … , ). 𝑓𝑓 𝑆𝑆 𝑆𝑆̅ • Design using the inverted inputs and add an inverter at the output. 𝑥𝑥1 𝑥𝑥𝑛𝑛 𝑥𝑥1 𝑥𝑥𝑛𝑛 𝑆𝑆̅ • Design methodology 7 – When = ( , … , ) • = ( , … , ) = ( , … , ) 𝑓𝑓 𝑆𝑆 𝑥𝑥1 𝑥𝑥𝑛𝑛 • Design using the given non𝐷𝐷-inverted inputs ( , … , ). 𝑓𝑓 𝑆𝑆 𝑥𝑥1 𝑥𝑥𝑛𝑛 𝑆𝑆 𝑥𝑥1 𝑥𝑥𝑛𝑛 𝐷𝐷 𝑆𝑆 𝑥𝑥1 𝑥𝑥𝑛𝑛 • Design methodology 8 – When = ( , , … , ) or ( , , … , ) • Convert the given function into an appropriate form to simplify the logic. 1 1 𝑛𝑛 1 1 𝑛𝑛 • Design𝑓𝑓 it𝑆𝑆. 𝑥𝑥 𝑥𝑥 𝑥𝑥 𝑆𝑆 𝑥𝑥 𝑥𝑥 𝑥𝑥 Complex Logic Gates in CMOS

• Examples (assuming only non-inverted inputs are available) – = (AND2) • Design = and add an inverter at the output. (# TRs: 6) 𝑓𝑓 𝑎𝑎 ∙ 𝑏𝑏 = = + • Design 𝑓𝑓 𝑎𝑎 ∙ 𝑏𝑏 with two inverters to generate and . (# TRs: 8)

𝑓𝑓 𝑎𝑎 ∙ 𝑏𝑏 𝑎𝑎� 𝑏𝑏� 𝑎𝑎� 𝑏𝑏� – = + • Add two inverters to generate and , then design . (# TRs: 12) 𝑓𝑓 𝑎𝑎� ∙ 𝑏𝑏 𝑐𝑐̅ ∙ 𝑑𝑑 𝑎𝑎� 𝑐𝑐̅ 𝑓𝑓 – = + (2:1 MUX)

𝑓𝑓 𝑠𝑠̅ ∙ 𝑎𝑎 𝑠𝑠 ∙ 𝑏𝑏 Complex Logic Gates in CMOS

• Bubble pushing (how to construct a pFET network) – = 1 + 0 = ( , … , ) 1 + ( , … , ) 0 𝐷𝐷 𝑓𝑓 𝐴𝐴 ∙ 𝐵𝐵 ∙ 𝐹𝐹 𝑥𝑥1 𝑥𝑥𝑛𝑛 ∙ 𝐹𝐹 𝑥𝑥1 𝑥𝑥𝑛𝑛 ∙ = 0 = ( + ) 0

𝑓𝑓 𝑎𝑎 ∙ 𝑏𝑏 ∙ 𝑓𝑓 𝑎𝑎 𝑏𝑏 ∙

𝑎𝑎 𝑎𝑎 𝑎𝑎 𝑏𝑏 𝑎𝑎 𝑏𝑏 𝑏𝑏 𝑏𝑏 = 1 = ( + ) 1 � 𝑓𝑓 𝑎𝑎� 𝑏𝑏� ∙ 𝑓𝑓 𝑎𝑎� ∙ 𝑏𝑏 ∙ 𝑎𝑎 𝑎𝑎 𝑎𝑎 𝑎𝑎 𝑏𝑏 𝑏𝑏 𝑏𝑏 𝑏𝑏 Complex Logic Gates in CMOS

• Bubble pushing (how to construct a pFET network) – Example

𝑎𝑎 = 𝑎𝑎 𝑏𝑏 𝑏𝑏

𝑐𝑐 𝑐𝑐 𝑑𝑑 𝑓𝑓 𝑑𝑑 𝑓𝑓 𝑒𝑒 𝑒𝑒

= 𝑎𝑎 𝑎𝑎 𝑏𝑏 𝑏𝑏

𝑐𝑐 𝑐𝑐 𝑑𝑑

𝑑𝑑 𝑓𝑓 𝑒𝑒 𝑒𝑒

𝑓𝑓 Complex Logic Gates in CMOS

• XOR – = + = + (#TRs: 8+4(for the two inverters)) • XNOR 𝑎𝑎 ⊕ 𝑏𝑏 𝑎𝑎 ∙ 𝑏𝑏� 𝑎𝑎� ∙ 𝑏𝑏 𝑎𝑎 ∙ 𝑏𝑏 𝑎𝑎� ∙ 𝑏𝑏� – = + = + (#TRs: 8+4(for the two inverters))

𝑎𝑎 ⊕ 𝑏𝑏 𝑎𝑎 ∙ 𝑏𝑏 𝑎𝑎� ∙ 𝑏𝑏� 𝑎𝑎 ∙ 𝑏𝑏� 𝑎𝑎� ∙ 𝑏𝑏

𝑏𝑏� 𝑎𝑎 𝑏𝑏 𝑎𝑎

� 𝑎𝑎� 𝑏𝑏 𝑎𝑎� 𝑏𝑏 𝑎𝑎 ⊕ 𝑏𝑏 𝑎𝑎 ⊕ 𝑏𝑏 𝑎𝑎� 𝑎𝑎� 𝑎𝑎 𝑎𝑎

𝑏𝑏 𝑏𝑏� 𝑏𝑏� 𝑏𝑏 Complex Logic Gates in CMOS

• Structured logic analysis – Derive a Boolean equation for a given transistor-level schematic.

• Analysis methodology 1 – Convert the nFET network into a Boolean equation (only when the pFET network is the dual of the nFET network.) – Notice that the nFET network passes logic 0. • Example – = + = + + = + 𝑎𝑎 𝑏𝑏 𝑓𝑓 𝑎𝑎 ∙ 𝑏𝑏 𝑎𝑎� ∙ 𝑏𝑏� 𝑎𝑎� 𝑏𝑏� ∙ 𝑎𝑎 𝑏𝑏 𝑎𝑎 ∙ 𝑏𝑏� 𝑎𝑎� ∙ 𝑏𝑏 � 𝑎𝑎� 𝑏𝑏 𝑎𝑎 ⊕ 𝑏𝑏 𝑎𝑎� 𝑎𝑎

𝑏𝑏 𝑏𝑏� Complex Logic Gates in CMOS

• Analysis methodology 2 – Identify all the paths from to the output (only when the pFET network is the dual of the nFET network.) 𝑉𝑉𝑆𝑆𝑆𝑆 – Merge them into a single Boolean equation. – Negate the output. • Example

– Path 1: – Path 2: c 𝑏𝑏 𝑏𝑏 ∙ 𝑎𝑎 – Merge: + = ( + ) 𝑎𝑎 ∙ 𝑎𝑎 – Negate: ( + ) 𝑐𝑐 𝑏𝑏 ∙ 𝑎𝑎 𝑐𝑐 ∙ 𝑎𝑎 𝑎𝑎 ∙ 𝑏𝑏 𝑐𝑐 – = ( + ) 𝑓𝑓 𝑎𝑎 ∙ 𝑏𝑏 𝑐𝑐 path 2 path 1 𝑓𝑓 𝑎𝑎 ∙ 𝑏𝑏 𝑐𝑐 𝑎𝑎

𝑏𝑏 𝑐𝑐 Pass Transistors

• nFET – = 0: OFF – = 1: ON 𝑔𝑔 • = 0: = strong 0 𝑔𝑔 • = 1: = weak 1 𝑔𝑔 𝑎𝑎 𝑏𝑏

𝑎𝑎 𝑏𝑏 𝑎𝑎 𝑏𝑏

• pFET – = 1: OFF – = 0: ON 𝑔𝑔 • = 0: = weak 0 𝑔𝑔 • = 1: = strong 1 𝑔𝑔 𝑎𝑎 𝑏𝑏 𝑎𝑎 𝑏𝑏 𝑎𝑎 𝑏𝑏 Transmission Gate Circuits

• Transistor circuit

𝑠𝑠̅ 𝑠𝑠̅ 𝑥𝑥 𝑦𝑦 𝑥𝑥 𝑦𝑦 𝑠𝑠 • Behaviors 𝑠𝑠 – When = 0: Both nFET and pFET are OFF. – When = 1: Both nFET and pFET are ON. 𝑠𝑠 • If = 0, the nFET perfectly transmits it to (nFET is good at transferring 0.) • If 𝑠𝑠= 1, the pFET perfectly transmits it to (pFET is good at transferring 1.) 𝑥𝑥 𝑦𝑦 𝑥𝑥 𝑦𝑦 • Disadvantage – Needs . – Does not restore the input signals. 𝑠𝑠̅ Transmission Gate Circuits

• Logic design using transmission gates – MUX: = +

𝑓𝑓 𝑠𝑠̅ ∙ 𝑥𝑥0 𝑠𝑠 ∙ 𝑥𝑥1

𝑠𝑠

𝑥𝑥0

𝑠𝑠̅ 𝑓𝑓 1 𝑥𝑥 – XNOR 𝑏𝑏�

𝑎𝑎 𝑓𝑓 𝑎𝑎⨁𝑏𝑏

𝑏𝑏 Pass Transistors vs. Transmission Gates

Pass TR. Transmission Gates

Symbols

Strong 0 Weak 0 Strong 0 Signal strength Weak 1 Strong 1 Strong 1 Area ( > 1) 1 + Control signal , 𝐴𝐴 𝑟𝑟𝑟𝑟 𝑟𝑟 𝑟𝑟 𝐴𝐴 𝑔𝑔 𝑔𝑔 𝑔𝑔 𝑔𝑔̅ Buffer

• =

𝑌𝑌 𝐴𝐴

𝐴𝐴 𝐴𝐴 𝑌𝑌 𝑌𝑌

• Buffers are used for – Signal restoration – Interconnect optimization Tristate Inverter

• Truth table

EN Y

1 𝑍𝑍 • Symbol & Schematic 𝐴𝐴̅

𝐸𝐸𝐸𝐸 𝐴𝐴 𝐴𝐴 𝑌𝑌 𝐸𝐸𝐸𝐸 𝑌𝑌 𝐸𝐸𝐸𝐸 𝐸𝐸𝐸𝐸 𝐴𝐴 𝑌𝑌 𝐴𝐴 𝐸𝐸𝐸𝐸 Tristate Buffer

• Symbol

𝐸𝐸𝐸𝐸 𝐸𝐸𝐸𝐸

𝐴𝐴 𝑌𝑌 𝐴𝐴 𝑌𝑌

𝐸𝐸𝐸𝐸 • Gate-level schematic

𝐸𝐸𝐸𝐸 𝐴𝐴 𝑌𝑌 Sequential Circuit – D Latch

• Positive-level-sensitive D latch CLK Q 0 hold 1 𝑪𝑪𝑪𝑪𝑪𝑪 𝐷𝐷 𝐷𝐷𝐷𝐷 𝑉𝑉 Transparent Hold

Capture 𝑡𝑡

𝑫𝑫 𝑉𝑉𝐷𝐷𝐷𝐷

𝑡𝑡

𝑸𝑸 𝑉𝑉𝐷𝐷𝐷𝐷

0 𝑡𝑡 Sequential Circuit – D Latch

• Schematic

𝐶𝐶𝐶𝐶𝐶𝐶

𝐷𝐷 𝑄𝑄� 𝐶𝐶𝐶𝐶𝐶𝐶

𝐶𝐶𝐶𝐶𝐶𝐶

𝑄𝑄 𝐶𝐶𝐶𝐶𝐶𝐶 Sequential Circuit – D Flip-Flop

• Positive-edge-triggered D flip-flop CLK Q 0, 1 hold ↑ catch 𝑪𝑪𝑪𝑪𝑪𝑪 𝐷𝐷𝐷𝐷 𝐷𝐷 𝑉𝑉 Hold

Capture 𝑡𝑡

𝑫𝑫 𝑉𝑉𝐷𝐷𝐷𝐷

𝑡𝑡

𝑸𝑸 𝑉𝑉𝐷𝐷𝐷𝐷

0 𝑡𝑡 Sequential Circuit – D Flip-Flop

• Schematic

𝐶𝐶𝐶𝐶𝐶𝐶 𝐶𝐶𝐶𝐶𝐶𝐶

𝐷𝐷 𝑄𝑄 𝐶𝐶𝐶𝐶𝐶𝐶 𝐶𝐶𝐶𝐶𝐶𝐶

𝐶𝐶𝐶𝐶𝐶𝐶 𝐶𝐶𝐶𝐶𝐶𝐶

𝑄𝑄� 𝐶𝐶𝐶𝐶𝐶𝐶 𝐶𝐶𝐶𝐶𝐶𝐶 Sequential Circuit

• Example – Inputs: , , , – Outputs: , 𝐷𝐷 𝐴𝐴𝐴𝐴𝐴𝐴 𝐶𝐶𝐶𝐶𝐶𝐶 𝐶𝐶𝐶𝐶𝐶𝐶 𝑄𝑄 𝑄𝑄�

𝐶𝐶𝐶𝐶𝐶𝐶 𝐶𝐶𝐶𝐶𝐶𝐶

𝐶𝐶𝐶𝐶𝐶𝐶 𝐶𝐶𝐶𝐶𝐶𝐶 𝐷𝐷 𝑄𝑄

𝐴𝐴𝐴𝐴𝐴𝐴 𝑄𝑄�