Logic Design with Mosfets

Logic Design with Mosfets

Logic Design with MOSFETs Dae Hyun Kim EECS Washington State University References • John P. Uyemura, “Introduction to VLSI Circuits and Systems,” 2002. – Chapter 2 • Neil H. Weste and David M. Harris, “CMOS VLSI Design: A Circuits and Systems Perspective,” 2011. – Chapter 1 Goal • Design logic gates using MOSFETs (NMOS and PMOS) Signals and Wires • Signals – 0 = = Ground = GND = Low = 0V – 1 = = Power = PWR = High = 5V, 3.3V, 1.5V, 1.2V, 1.0V, etc. • Wires Wire 1 a b Wire 2 a a a a No connection Connection Ideal Switches • Switch Control Control Electrically open Electrically short • Assert-high switch = = = Open ( is undefined) Closed ( = ) • Assert-low switch = = = Closed ( = ) Open ( is undefined) Series/Parallel Connections of Switches • Series a b y 0 0 = = ( ) 0 1 undefined AND operation ∙ ∙ ∙ ∙ 1 0 ∙ ( is defined only when = 1 and = 1) 1 1 ( is undefined if = 0 or = 0) • Parallel a b y 0 0 undefined + = ( + ) 0 1 ∙ ∙ ∙ 1 0 OR operation 1 1 ( is defined only when = 1 or = 1) ( is undefined if = 0 and = 0) Inverter Design with Switches • Inverter – The output is defined both when = 0 and when = 1. 1 1 a y ∙ � 0 1 = 1 + 0 = 1 0 0 ∙ � ∙ � 0 ∙ Inverter Design with Switches • Two inverter designs 1 0 0 � Why? 1 � MOSFETs as Switches • MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor – n-channel MOSFET = nFET = NMOS – p-channel MOSFET = pFET = PMOS – Complementary MOS: CMOS • Symbols Gate Gate Source Drain Drain Source nFET pFET = = ( ) ( ) ≥ ≥ MOSFETs as Switches • Threshold voltage – nFET: > 0 – pFET: < 0 Drain • nFET – OFF: = 1: Mn ON Gate Mn – ON: > Source = 0: Mn OFF ≤ 0 Logic translation • pFET | | Source – OFF: = 1: Mp OFF | | Gate Mp – ON: > | | ≤ − = 0: Mp ON Drain 0 Logic translation MOSFETs as Switches • Example (PTM High-Performance 45nm High-K Metal Gate) – : 1.0V – : 0.46893V – : -0.49158V • Example (PTM High-Performance 32nm High-K Metal Gate) – : 0.9V – : 0.49396V – : -0.49155V • Example (PTM High-Performance 22nm High-K Metal Gate) – : 0.8V – : 0.50308V – : -0.4606V Pass Characteristics • nFET ↑ ↓ ↑ = 0 0 Logic 0 transfer: strong logic 0 = 0.1 - 0.1 0.1 ... ... ... = − − Logic 1 transfer: weak logic 1 • pFET − = ↓ ↓ ↓ = 0 Logic 1 transfer: strong logic 1 = ...− ...− ...− | | | | 0 0 | | Logic 0 transfer: weak logic 0 Pass Characteristics • SPICE simulation (45nm technology) – nFET Pass Characteristics • SPICE simulation (45nm technology) – pFET 0 Pass Characteristics • nFET – Strong logic 0 transfer – Weak logic 1 transfer • pFET – Strong logic 1 transfer – Weak logic 0 transfer • CMOS – Use pFETs to pass logic 1. – Use nFETs to pass logic 0. Basic Logic Gates in CMOS • Principles – Construct the nFET network using only nFETs and the pFET network using only pFETs. – If the output is 1, the pFET network connects to the output and the nFET network disconnects and the output. – If the output is 0, the nFET network connects to the output and the pFET network disconnects and the output. pFET network , , , … (inputs) (output) nFET network Basic Logic Gates in CMOS • Inverter # TRs: 2 = nFET: 1 pFET: 1 ̅ off 0 = 1 1 = 0 off = 1 + 0 = ̅ ∙ ∙ ̅ Basic Logic Gates in CMOS • SPICE simulation Basic Logic Gates in CMOS • Two-input NAND (NAND2) = # TRs: 4 nFETs: 2 ∙ pFETs: 2 off off off 0 = 1 0 = 1 1 = 0 off off 0 off 1 1 = 1 + 1 + 1 + 0 = + = � ∙ � ∙ � ∙ ∙ ∙ � ∙ ∙ ∙ � � ∙ Basic Logic Gates in CMOS • SPICE simulation Basic Logic Gates in CMOS • Two-input NOR (NOR2) # TRs: 4 nFETs: 2 = + pFETs: 2 0 1 1 off 0 0 off 1 off = 1 = 0 = 0 0 off 0 off 0 off 1 1 1 = 1 + 0 + 0 + 0 = = + � ∙ � ∙ � ∙ ∙ ∙ � ∙ ∙ ∙ � ∙ � Basic Logic Gates in CMOS • SPICE simulation Complex Logic Gates in CMOS • Example = ( + ) • Using logic gates ∙ # TRs: 14 nFETs: 7 pFETs: 7 • Using logic gates # TRs: 10 nFETs: 5 pFETs: 5 • Using TRs # TRs: 6 nFETs: 3 pFETs: 3 Complex Logic Gates in CMOS • How to design – Inverter = = 1 + 0 = pFET network nFET network (connects 1 and the output)̅ ̅ ∙ (connects ∙ 0 and the output) ̅ – NAND2 = = 1 + 0 = ( + ) 1 + 0 pFET network nFET network ∙ ∙ (expressed∙ by∙ ∙and ) � � ∙ ∙ (expressed∙ by and ) ( + ) � � � � = ∙ ( ) ∙ Complex Logic Gates in CMOS • How to design – Express = 1 + 0 = ( , … , ) 1 + ( , … , ) 0 – Design a pFET network using A = ( , … , ). ∙ ∙ 1 ∙ 1 ∙ • pFETs are ON when the inputs are 0. 1 – Design an nFET network using B = ( , … , ). • nFETs are ON when the inputs are 1. 1 • Example = ( + ) = ( + ) 1 + + 0 = ( + ) 1 + + 0 – ∙ pFET network nFET network ∙ ∙ ∙ ∙ � � ∙ ̅ ∙ ∙ ∙ Complex Logic Gates in CMOS • Example = ( + ) ∙ # TRs: 6 nFETs: 3 pFETs: 3 Complex Logic Gates in CMOS • Structured logic design – Design a given Boolean equation using nFETs and pFETs. • Assume that only non-inverted input signals are given. – , , , … are given. – , , , … are not given. If you need them, you should generate them. � � ̅ Complex Logic Gates in CMOS • Design methodology 1 – When = ( , … , ) ( is a function of non-inverted variables) • = = 1 + 0 1 • Design an nFET network for using , … , . ̅ ̅ ∙ ∙ • Design a pFET network for using , … , . 1 • Connect them to , , . ̅ 1 = ( + ) – Example: • = ( + ) 1 + a ( + ) 0 ∙ • Design an nFET network for a ( + ). ∙ ∙ ∙ ∙ • Design a pFET network for ( + ) = + . ∙ • Connect them. ∙ � � ∙ ̅ Complex Logic Gates in CMOS • Design methodology 2 – When = ( , … , ) • = = 1 + 0 1 • Design an nFET network for . ̅ ̅ ∙ ∙ • Design a pFET network with a dual logic of the nFET network. – Dual of , … , , 0,1, , = ( , … , , 1,0, , ) • Connect them. 1 1 – Example: = ( + ) • = ( + ) 1 + a ( + ) 0 ∙ • Design an nFET network for a ( + ). ∙ ∙ ∙ ∙ • Dual of + = + = + . ∙ • Connect them. ∙ ∙ ∙ Complex Logic Gates in CMOS • Dual logic – , … , , 0,1, , = ( , … , , 1,0, , ) – Example 1 1 • ( ) = + • ( + ) = ∙ • (1 ) = 0 + = ∙ • (1 + ) = 0 = 0 ∙ • (0 ) = 1 + =1 ∙ • (0 + ) = 1 = ∙ • Principles of the dual∙ logic – The nFET and the pFET networks work complementarily. – If the nFET network is ON (i.e., connects to the output), the pFET network is OFF (i.e., disconnect the output from ) and vice versa. – If two networks are dual, they work complementarily. • Prove! Complex Logic Gates in CMOS • Principles of the dual logic – = ( , … , ) = = ( , … , ) 1 + ( , … , ) 0 – ( , … , ) = ( , … , , 0,1, , ) = , … , , 1,0, , = 1 1 ∙ 1 ∙ ( , … , ) (De Morgan’s law) 1 1 1 – A pFET is ON when its control variable ( ) is 0. 1 – Thus, the pFET network is the dual of the nFET network. Complex Logic Gates in CMOS • Design methodology 3 – When = ( , … , ) ( is a function of non-inverted variables) • = = 1 • Design and add an inverter at the output. ̅ – Example: = ( + ) ̅ • = + = ( + ) ∙ • Design ( + ). ∙ ∙ • Add an inverter at the output. ∙ Complex Logic Gates in CMOS • Design methodology 4 – When = ( , … , ) ( is a function of inverted variables) • Generate inverted inputs ( , … , ) from the given inputs ( , … , ). 1 • Design using the inverted inputs. 1 1 – Example: = ( + ) • Inverters are not shown for brevity. � ∙ � ̅ � � ̅ � � ̅ Complex Logic Gates in CMOS • Design methodology 5 – When = ( , … , ) • = ( , … , ) = ( , … , ) = ( , … , ) 1 • Design ( , … , ) using the given inputs. 1 1 1 • Add an inverter at the output. 1 – Example: = + ( ) • = ( + ) = � ( + ) � ∙ ̅ ∙ ∙ Complex Logic Gates in CMOS • Design methodology 6 – When = ( , … , ) • = = 1 • Generate inverted inputs ( , … , ) from the given inputs ( , … , ). ̅ • Design using the inverted inputs and add an inverter at the output. 1 1 ̅ • Design methodology 7 – When = ( , … , ) • = ( , … , ) = ( , … , ) 1 • Design using the given non-inverted inputs ( , … , ). 1 1 1 • Design methodology 8 – When = ( , , … , ) or ( , , … , ) • Convert the given function into an appropriate form to simplify the logic. 1 1 1 1 • Design it. Complex Logic Gates in CMOS • Examples (assuming only non-inverted inputs are available) – = (AND2) • Design = and add an inverter at the output. (# TRs: 6) ∙ = = + • Design ∙ with two inverters to generate and . (# TRs: 8) ∙ � � � � – = + • Add two inverters to generate and , then design . (# TRs: 12) � ∙ ̅ ∙ � ̅ – = + (2:1 MUX) ̅ ∙ ∙ Complex Logic Gates in CMOS • Bubble pushing (how to construct a pFET network) – = 1 + 0 = ( , … , ) 1 + ( , … , ) 0 ∙ ∙ 1 ∙ 1 ∙ = 0 = ( + ) 0 ∙ ∙ ∙ = 1 = ( + ) 1 � � � ∙ � ∙ ∙ Complex Logic Gates in CMOS • Bubble pushing (how to construct a pFET network) – Example = = Complex Logic Gates in CMOS • XOR – = + = + (#TRs: 8+4(for the two inverters)) • XNOR ⊕ ∙ � � ∙ ∙ � ∙ � – = + = + (#TRs: 8+4(for the two inverters)) ⊕ ∙ � ∙ � ∙ � � ∙ � � � � ⊕ ⊕ � � � � Complex Logic Gates in CMOS • Structured logic analysis – Derive a Boolean equation for a given transistor-level schematic. • Analysis methodology 1 – Convert the nFET network into a Boolean equation (only when the pFET network is the dual of the nFET network.) – Notice that the nFET network passes logic 0. • Example – = + = + + = + ∙ � ∙ � � � ∙ ∙ � � ∙ � � ⊕ � � Complex Logic Gates in CMOS • Analysis methodology 2 – Identify all the paths from to the output (only when the

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