Introduction to CMOS VLSI Design

Lecture 4: CMOS Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh

Outline q Introduction q MOS q nMOS I-V Characteristics q pMOS I-V Characteristics q Gate and Diffusion q Pass q RC Delay Models

3: CMOS Transistor Theory CMOS VLSI Design Slide 2 Introduction q So far, we have treated transistors as ideal q An ON transistor passes a finite amount of current – Depends on terminal – Derive current- (I-V) relationships q Transistor gate, source, drain all have capacitance – I = C (ΔV/Δt) -> Δt = (C/I) ΔV – Capacitance and current determine speed q Also explore what a “degraded level” really means

3: CMOS Transistor Theory CMOS VLSI Design Slide 3 MOS Transistors - Types and Symbols

D D

G G

S S NMOS Enhancement NMOS Depletion D D

G G B

S S PMOS Enhancement NMOS with Bulk Contact

© Digital Integrated Circuits2nd Devices The MOS Transistor

Polysilicon Aluminum

© Digital Integrated Circuits2nd Devices Controlling current flow in an nFET.

© Digital Integrated Circuits2nd Introduction to Circuits, Fourth Edition by PeterDevices Uyemura, Copyright © 2004 John Wiley & Sons. All rights reserved. Controlling current flow in a pFET.

© Digital Integrated Circuits2nd Introduction to Circuits, Fourth Edition by PeterDevices Uyemura, Copyright © 2004 John Wiley & Sons. All rights reserved. What is a Transistor?

A ! A MOS Transistor

VGS ≥ VT |V GS |

R on S D

© Digital Integrated Circuits2nd Devices I-V Curves Current (I) vs. Voltage (V) I = f(V) -4 6x 10

5

4

(A)

3D I

2

1

0 0 0.5 1 1.5 2 2.5 VDS MOS I = V/R I = Is*exp(k*V-Vt) I = f(Vgs, Vds) Terminal Voltages

V q Mode of operation depends on Vg, Vd, Vs g + + – Vgs = Vg – Vs Vgs Vgd – Vgd = Vg – Vd - - V V – Vds = Vd – Vs = Vgs - Vgd s - + d Vds q Source and drain are symmetric diffusion terminals – By convention, source is terminal at lower voltage

– Hence Vds ≥ 0 q nMOS body is grounded. First assume source is 0 too. q Three regions of operation – Cutoff – Linear – Saturation

3: CMOS Transistor Theory CMOS VLSI Design Slide 10 MOS Capacitor q Gate and body form MOS capacitor

polysilicon gate q Operating modes V < 0 g silicon dioxide insulator + – Accumulation - p-type body

– Depletion (a) – Inversion 0 < Vg < Vt depletion region + In general, MOS -

gate capacitance (b) is not constant

Vg > Vt inversion region + -

(c)

3: CMOS Transistor Theory CMOS VLSI Design Slide 11 MOS Transistors – Operating regions

2nd Copyright© Digital Integrated © 2005 CircuitsPearson Addison-Wesley. All rights reserved. Devices nMOS Cutoff q No channel q Ids = 0

V = 0 V d gs + g + gd - - s d g n+ n+ s p-type body b

3: CMOS Transistor Theory CMOS VLSI Design Slide 13 nMOS Linear q Channel forms q Current flows from d to s V > V gs t V = V – e- from s to d + g + gd gs - - q I increases with V s d ds ds V = 0 n+ n+ ds q Similar to linear resistor p-type body b d V > V gs t V > V > V + g + gs gd t g - - I s d ds n+ n+ 0 < V < V -V s ds gs t p-type body b

3: CMOS Transistor Theory CMOS VLSI Design Slide 14 Linear Region Vgs>Vt & Vgd>Vt

V GS VDS S G ID D Ids + + n – V(x) + n Vgd L x R V p-substrate gs

B I=V/R PositiveMOS transistorCharge and on its Gate: bias conditions Ids Channel exists, Current Flows

since Vds > 0 R= 1/(k’(W/L)(Vgs-Vt)) 2 Ids = k’(W/L)((Vgs-Vt)Vds-Vds /2)

Vds © Digital Integrated Circuits2nd Devices nMOS Saturation q Channel pinches off q Ids independent of Vds q We say current saturates q Similar to

d V > V gs t V < V + g + gd t - - I g s d ds

n+ n+ Vds > Vgs-Vt s p-type body b

3: CMOS Transistor Theory CMOS VLSI Design Slide 16 Saturation: Vgs>Vt & Vgd

VGS Ids V > V - V G DS GS T Vgd D S Ids

+ n+ - V - V n+ Vgs GS T

Positive Charge on Gate: Channel exists, Current Flows

since Vds > 0 But: channel is “pinched off” 2 Ids = (k’/2)(W/L)(Vgs-Vt) © Digital Integrated Circuits2nd Devices I-V Characteristics q In Linear region, Ids depends on – How much charge is in the channel? – How fast is the charge moving?

3: CMOS Transistor Theory CMOS VLSI Design Slide 18 MOS Transistors – Regions Transitions

2nd Copyright© Digital Integrated © 2005 CircuitsPearson Addison-Wesley. All rights reserved. Devices Channel Charge q MOS structure looks like plate capacitor while operating in inversion – Gate – oxide – channel q Qchannel =

gate

Vg polysilicon + + V C V gate source gs g gd drain W - - Vs channel Vd t ox n+ - + n+ Vds L SiO2 gate oxide n+ n+ (good , = 3.9) εox p-type body p-type body

3: CMOS Transistor Theory CMOS VLSI Design Slide 20 Channel Charge q MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel q Qchannel = CV q C =

gate

Vg polysilicon + + V C V gate source gs g gd drain W - - Vs channel Vd t ox n+ - + n+ Vds L SiO2 gate oxide n+ n+ (good insulator, = 3.9) εox p-type body p-type body

3: CMOS Transistor Theory CMOS VLSI Design Slide 21 Channel Charge q MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel q Qchannel = CV q C = Cg = εoxWL/tox = CoxWL Cox = εox / tox C = 8.6*fF/um2 q V = ox gate

Vg polysilicon + + V C V gate source gs g gd drain W - - Vs channel Vd t ox n+ - + n+ Vds L SiO2 gate oxide n+ n+ (good insulator, = 3.9) εox p-type body p-type body

3: CMOS Transistor Theory CMOS VLSI Design Slide 22 Channel Charge q MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel q Qchannel = CV q C = Cg = εoxWL/tox = CoxWL Cox = εox / tox q V = Vgc – Vt = (Vgs – Vds/2) – Vt gate

Vg polysilicon + + V C V gate source gs g gd drain W - - Vs channel Vd t ox n+ - + n+ Vds L SiO2 gate oxide n+ n+ (good insulator, = 3.9) εox p-type body p-type body

3: CMOS Transistor Theory CMOS VLSI Design Slide 23 Carrier velocity q Charge is carried by e- q Carrier velocity v proportional to lateral E-field between source and drain q v =

3: CMOS Transistor Theory CMOS VLSI Design Slide 24 Carrier velocity q Charge is carried by e- q Carrier velocity v proportional to lateral E-field between source and drain q v = µE µ called mobility q E =

3: CMOS Transistor Theory CMOS VLSI Design Slide 25 Carrier velocity q Charge is carried by e- q Carrier velocity v proportional to lateral E-field between source and drain q v = µE µ called mobility q E = Vds/L q Time for carrier to cross channel: – t =

3: CMOS Transistor Theory CMOS VLSI Design Slide 26 Carrier velocity q Charge is carried by e- q Carrier velocity v proportional to lateral E-field between source and drain q v = µE µ called mobility q E = Vds/L q Time for carrier to cross channel: – t = L / v

3: CMOS Transistor Theory CMOS VLSI Design Slide 27 nMOS Linear I-V q Now we know

– How much charge Qchannel is in the channel – How much time t each carrier takes to cross

Ids =

3: CMOS Transistor Theory CMOS VLSI Design Slide 28 nMOS Linear I-V q Now we know

– How much charge Qchannel is in the channel – How much time t each carrier takes to cross Q I = channel ds t =

3: CMOS Transistor Theory CMOS VLSI Design Slide 29 nMOS Linear I-V q Now we know

– How much charge Qchannel is in the channel – How much time t each carrier takes to cross Q I = channel ds t

W ⎛⎞Vds =µCVVox ⎜⎟gs−− t V ds L ⎝⎠2 W ⎛⎞Vds = C =β ⎜⎟VVgs−− t V ds βµox ⎝⎠2 L

3: CMOS Transistor Theory CMOS VLSI Design Slide 30 Computed Curves

Linear Resistor Vgs = 5v

Vgs = 4.5v

Vgs = 4.0v

© Digital Integrated Circuits2nd Devices nMOS Saturation I-V q If Vgd < Vt, channel pinches off near drain

– When Vds > Vdsat = Vgs – Vt q Now drain voltage no longer increases current

Ids =

3: CMOS Transistor Theory CMOS VLSI Design Slide 32 nMOS Saturation I-V q If Vgd < Vt, channel pinches off near drain

– When Vds > Vdsat = Vgs – Vt q Now drain voltage no longer increases current

⎛⎞Vdsat IVVVds=β ⎜⎟ gs−− t dsat ⎝⎠2

3: CMOS Transistor Theory CMOS VLSI Design Slide 33 nMOS Saturation I-V q If Vgd < Vt, channel pinches off near drain

– When Vds > Vdsat = Vgs – Vt q Now drain voltage no longer increases current

⎛⎞Vdsat IVVVds=β ⎜⎟ gs−− t dsat ⎝⎠2 β 2 =VV− 2 ( gs t )

3: CMOS Transistor Theory CMOS VLSI Design Slide 34 Computed Curves

Linear Resistor Vgs = 5v

Vgs = 4.5v

Vgs = 4.0v

3: CMOS Transistor Theory CMOS VLSI Design Slide 35 nMOS I-V Summary q Shockley 1st order transistor models

⎧

⎪ 0 VVgs< t cutoff ⎪ ⎪ V IVVVVV⎛⎞ds linear ds=⎨β ⎜⎟ gs−− t2 ds ds < dsat ⎪ ⎝⎠ ⎪ β 2 VV− VV>saturation ⎩⎪ 2 ( gs t) ds dsat

3: CMOS Transistor Theory CMOS VLSI Design Slide 36 Example q We will be using a 0.180 µm process for your project – From TSMC

– tox = 40 Å – µ = 180 cm2/V*s

– Vt = 0.4 V q Plot Ids vs. Vds

– Vgs = 0, 0.3,…, 1.8 – Use W/L = 4/2 λ

WWW⎛⎞3.9• 8.85⋅ 10−14 CAV350⎛⎞155 120 / 2 β==µox (180) ⎜⎟−8 ⎜⎟ = µ LLL⎝⎠10040 ⋅ 10 ⎝⎠

3: CMOS Transistor Theory CMOS VLSI Design Slide 37 pMOS I-V q All dopings and voltages are inverted for pMOS q Mobility µp is determined by holes – Typically 2-3x lower than

that of µn q Thus pMOS must be wider to provide same current

– Often, assume µn / µp = 2

3: CMOS Transistor Theory CMOS VLSI Design Slide 38 Current-Voltage Relations Long-Channel Device

Cut-off (VGS – VT < 0) “no current” (not really)

© Digital Integrated Circuits2nd Devices ID versus VDS short channel device

-4 -4 x 10 x 10 6 2.5 VGS= 2.5 V VGS= 2.5 V 5 2 Resistive Saturation 4 VGS= 2.0 V

VGS= 2.0 V 1.5

(A) (A)

D

3 D

I I VDS = VGS - VT 1 VGS= 1.5 V 2 VGS= 1.5 V 0.5 1 VGS= 1.0 V VGS= 1.0 V

0 0 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 V (V) VDS (V) DS Long Channel Short Channel

© Digital Integrated Circuits2nd Devices Rabaey’s unified model for manual analysis

G

S D

B

© Digital Integrated Circuits2nd Devices for Manual Analysis

© Digital Integrated Circuits2nd Devices Simple Model versus SPICE

-4 x 10 2.5

VDS=VDSAT 2 Velocity 1.5 Saturated

(A) Linear D

I 1

VDSAT=VGT 0.5 V =V DS GT Saturated 0 0 0.5 1 1.5 2 2.5 V (V) DS © Digital Integrated Circuits2nd Devices Even Simpler: The Transistor as a Switch

VGS ≥ VT R ID on VGS = VDD S D Rmid

R0

VDS VDD/2 VDD

© Digital Integrated Circuits2nd Devices The Transistor as a Switch

This week’s Lab – find Req for our TSMC 180nm process

© Digital Integrated Circuits2nd Devices Saturation Effects

Discharge of 1pf capacitor, with Vgs of 3,4,5 . Also, 12k resistor.

d g Which is the resistor? s

© Digital Integrated Circuits2nd Devices More on Capacitance q Any two conductors separated by an insulator have capacitance q Gate to channel capacitor is very important – Creates channel charge necessary for operation q Source and drain have capacitance to body – Across reverse-biased – Called diffusion capacitance because it is associated with source/drain diffusion

3: CMOS Transistor Theory CMOS VLSI Design Slide 47 Gate Capacitance q Approximate channel as connected to source q Cgs = εoxWL/tox = CoxWL = CpermicronW q Cpermicron is typically about 2 fF/µm

polysilicon gate W

tox L SiO gate oxide n+ n+ 2 (good insulator, εox = 3.9ε0) p-type body

3: CMOS Transistor Theory CMOS VLSI Design Slide 48 The Gate Capacitance

Polysilicon gate

Source Drain W n+ xd xd n+

Gate-bulk L d overlap Top view Gate oxide tox n+ L n+

Cross section

© Digital Integrated Circuits2nd Devices Dynamic Behavior of MOS Transistor

G

CGS CGD

S D

CSB CGB CDB

B

© Digital Integrated Circuits2nd Devices Physical visualization of FET

© Digital Integrated Circuits2nd Introduction to Circuits, Fourth Edition by PeterDevices Uyemura, Copyright © 2004 John Wiley & Sons. All rights reserved. MOS Capacitances Behavior !

2nd Copyright© Digital Integrated © 2005 CircuitsPearson Addison-Wesley. All rights reserved. Devices Gate Capacitance – Behavior

G G G

CGC CGC CGC S D S D S D

Cut-off Resistive Saturation

Most important regions in digital design: saturation and cut-off

© Digital Integrated Circuits2nd Devices Measuring the Gate Cap

3 102 16 10 9 V GS 8 I 7 6 5 4 Gate Capacitance (F) 3 2 2 2 2 1.5 2 1 2 0.5 0 0.5 1 1.5 2

V GS (V)

© Digital Integrated Circuits2nd Devices Diffusion Capacitance q Csb, Cdb q Undesirable, called q Capacitance depends on area and perimeter – Use small diffusion nodes

– Comparable to Cg for contacted diff

– ½ Cg for uncontacted – Varies with process

3: CMOS Transistor Theory CMOS VLSI Design Slide 55 Diffusion Capacitance

Channel-stop implant NA 1

Side wall Source W N D Bottom

xj Side wall Channel L S Substrate N A

© Digital Integrated Circuits2nd Devices Calculation of the FET junction capacitance

© Digital Integrated Circuits2nd Introduction to Circuits, Fourth Edition by PeterDevices Uyemura, Copyright © 2004 John Wiley & Sons. All rights reserved. Capacitances in 0.25 µm CMOS process

Values for a Typical Device:

© Digital Integrated Circuits2nd Devices Parasitic Resistances

Polysilicon gate Drain contact G LD

VGS,eff

S D W

RS RD

Drain

© Digital Integrated Circuits2nd Devices Final construction of the nFET RC model

CG

© Digital Integrated Circuits2nd Introduction to Circuits, Fourth Edition by PeterDevices Uyemura, Copyright © 2004 John Wiley & Sons. All rights reserved. Latchup

VDD VDD R nwell p-source p+ n+ n+ p+ p+ n+

n-well Rnwell

R psubs n-source R p-substrate psubs

(a) Origin of latchup (b) Equivalent circuit

© Digital Integrated Circuits2nd Devices Summary of MOSFET Operating Regions

q Strong Inversion VGS > VT

§ Linear (Resistive) VDS < VDSAT

§ Saturated (Constant Current) VDS ≥ VDSAT

q Weak Inversion (Sub-Threshold) VGS ≤ VT

§ Exponential in VGS with linear VDS dependence

© Digital Integrated Circuits2nd Devices SPICE MODELS

Level 1: Long Channel Equations - Very Simple

Level 2: Physical Model - Includes Velocity Saturation and Threshold Variations

Level 3: Semi-Emperical - Based on curve fitting to measured devices

Level 4 (BSIM): Emperical - Simple and Popular

© Digital Integrated Circuits2nd Devices Main MOS SPICE Parameters

© Digital Integrated Circuits2nd Devices SPICE Parameters for Parasitics

© Digital Integrated Circuits2nd Devices SPICE Transistors Parameters

© Digital Integrated Circuits2nd Devices Circuit Simulation Model of CMOS

© Digital Integrated Circuits2nd Devices Pass Transistors

q We have assumed source is grounded VDD q What if source > 0? VDD § e.g. pass transistor passing VDD

© Digital3: Integrated CMOS Circuits Transistor2nd Theory Slide 68 Devices Pass Transistors

q We have assumed source is grounded q What if source > 0? VDD V § e.g. pass transistor passing VDD DD

q Vg = VDD

§ If Vs > VDD-Vt, Vgs < Vt § Hence transistor would turn itself off

q nMOS pass transistors pull no higher than VDD-Vtn § Called a degraded “1”

§ Approach degraded value slowly (low Ids)

q pMOS pass transistors pull no lower than Vtp

© Digital3: Integrated CMOS Circuits Transistor2nd Theory Slide 69 Devices Pass Transistor Ckts

VDD VDD VDD VDD VDD VDD

VDD

VDD

VSS

© Digital3: Integrated CMOS Circuits Transistor2nd Theory Slide 70 Devices Pass Transistor Ckts

V V V V DD DD DD DD V V DD DD V = V -V V -V s DD tn V -V DD tn DD tn VDD-Vtn

V DD V -V Vs = |Vtp| DD tn V DD VDD-2Vtn VSS

© Digital3: Integrated CMOS Circuits Transistor2nd Theory Slide 71 Devices Effective Resistance

q Shockley models have limited value § Not accurate enough for modern transistors § Too complicated for much hand analysis q Simplification: treat transistor as resistor

§ Replace Ids(Vds, Vgs) with effective resistance R

– Ids = Vds/R § R averaged across switching of digital gate q Too inaccurate to predict current at any given time § But good enough to predict RC delay

© Digital3: Integrated CMOS Circuits Transistor2nd Theory Slide 72 Devices RC Delay Model

q Use equivalent circuits for MOS transistors § Ideal switch + capacitance and ON resistance § Unit nMOS has resistance R, capacitance C § Unit pMOS has resistance 2R, capacitance C q Capacitance proportional to width q Resistance inversely proportional to width d s kC kC R/k d 2R/k d g k g kC g k g s kC kC kC s s d

© Digital3: Integrated CMOS Circuits Transistor2nd Theory Slide 73 Devices RC Values

q Capacitance

§ C = Cg = Cs = Cd = 2 fF/µm of gate width § Values similar across many processes q Resistance § R ≈ 6 KΩ*µm in 0.6um process § Improves with shorter channel lengths q Unit transistors § May refer to minimum contacted device (4/2 λ) § Or maybe 1 µm wide device § Doesn’t matter as long as you are consistent

© Digital3: Integrated CMOS Circuits Transistor2nd Theory Slide 74 Devices Inverter Delay Estimate

q Estimate the delay of a fanout-of-1 inverter

2 Y 2 A 1 1

© Digital3: Integrated CMOS Circuits Transistor2nd Theory Slide 75 Devices Inverter Delay Estimate

q Estimate the delay of a fanout-of-1 2C

inverter R

2C 2C 2 Y 2 A Y 1 1 C R C

C

© Digital3: Integrated CMOS Circuits Transistor2nd Theory Slide 76 Devices Inverter Delay Estimate

q Estimate the delay of a fanout-of-1 2C

inverter R

2C 2C 2C 2C 2 Y 2 A Y 1 1 R C C R C C

C

© Digital3: Integrated CMOS Circuits Transistor2nd Theory Slide 77 Devices Inverter Delay Estimate

q Estimate the delay of a fanout-of-1 2C

inverter R

2C 2C 2C 2C 2 Y 2 A Y 1 1 R C C R C C

C

d = 6RC

© Digital3: Integrated CMOS Circuits Transistor2nd Theory Slide 78 Devices