Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q nMOS I-V Characteristics q pMOS I-V Characteristics q Gate and Diffusion Capacitance q Pass Transistors q RC Delay Models 3: CMOS Transistor Theory CMOS VLSI Design Slide 2 Introduction q So far, we have treated transistors as ideal switches q An ON transistor passes a finite amount of current – Depends on terminal voltages – Derive current-voltage (I-V) relationships q Transistor gate, source, drain all have capacitance – I = C (ΔV/Δt) -> Δt = (C/I) ΔV – Capacitance and current determine speed q Also explore what a “degraded level” really means 3: CMOS Transistor Theory CMOS VLSI Design Slide 3 MOS Transistors - Types and Symbols D D G G S S NMOS Enhancement NMOS Depletion D D G G B S S NMOS with PMOS Enhancement Bulk Contact © Digital Integrated Circuits2nd Devices The MOS Transistor Polysilicon Aluminum © Digital Integrated Circuits2nd Devices Controlling current flow in an nFET. © Digital Integrated Circuits2nd Introduction to Circuits, Fourth Edition by PeterDevices Uyemura, Copyright © 2004 John Wiley & Sons. All rights reserved. Controlling current flow in a pFET. © Digital Integrated Circuits2nd Introduction to Circuits, Fourth Edition by PeterDevices Uyemura, Copyright © 2004 John Wiley & Sons. All rights reserved. What is a Transistor? A Switch! A MOS Transistor VGS ≥ VT |V GS | R on S D © Digital Integrated Circuits2nd Devices I-V Curves Current (I) vs. Voltage (V) I = f(V) x 10-4 6 5 4 (A) 3D I 2 1 0 0 0.5 1 1.5 2 2.5 VDS Resistor Diode MOS I = V/R I = Is*exp(k*V-Vt) I = f(Vgs, Vds) Terminal Voltages V q Mode of operation depends on Vg, Vd, Vs g + + – Vgs = Vg – Vs Vgs Vgd – Vgd = Vg – Vd - - V V – Vds = Vd – Vs = Vgs - Vgd s - + d Vds q Source and drain are symmetric diffusion terminals – By convention, source is terminal at lower voltage – Hence Vds ≥ 0 q nMOS body is grounded. First assume source is 0 too. q Three regions of operation – Cutoff – Linear – Saturation 3: CMOS Transistor Theory CMOS VLSI Design Slide 10 MOS Capacitor q Gate and body form MOS capacitor polysilicon gate q Operating modes V < 0 g silicon dioxide insulator + – Accumulation - p-type body – Depletion (a) – Inversion 0 < Vg < Vt depletion region + In general, MOS - gate capacitance (b) is not constant Vg > Vt inversion region + - depletion region (c) 3: CMOS Transistor Theory CMOS VLSI Design Slide 11 MOS Transistors – Operating regions 2nd Copyright© Digital Integrated © 2005 CircuitsPearson Addison-Wesley. All rights reserved. Devices nMOS Cutoff q No channel q Ids = 0 V = 0 V d gs + g + gd - - s d g n+ n+ s p-type body b 3: CMOS Transistor Theory CMOS VLSI Design Slide 13 nMOS Linear q Channel forms q Current flows from d to s V > V gs t V = V – e- from s to d + g + gd gs - - q I increases with V s d ds ds V = 0 n+ n+ ds q Similar to linear resistor p-type body b d V > V gs t V > V > V + g + gs gd t g - - I s d ds n+ n+ 0 < V < V -V s ds gs t p-type body b 3: CMOS Transistor Theory CMOS VLSI Design Slide 14 Linear Region Vgs>Vt & Vgd>Vt V GS VDS S G ID D Ids + + n – V(x) + n Vgd L x R V p-substrate gs B I=V/R PositiveMOS transistorCharge and on its Gate: bias conditions Ids Channel exists, Current Flows since Vds > 0 R= 1/(k’(W/L)(Vgs-Vt)) 2 Ids = k’(W/L)((Vgs-Vt)Vds-Vds /2) Vds © Digital Integrated Circuits2nd Devices nMOS Saturation q Channel pinches off q Ids independent of Vds q We say current saturates q Similar to current source d V > V gs t V < V + g + gd t - - I g s d ds n+ n+ Vds > Vgs-Vt s p-type body b 3: CMOS Transistor Theory CMOS VLSI Design Slide 16 Saturation: Vgs>Vt & Vgd<Vt VGS Ids V > V - V G DS GS T Vgd D S Ids - + V n+ VGS - VT n+ gs Positive Charge on Gate: Channel exists, Current Flows since Vds > 0 But: channel is “pinched off” 2 Ids = (k’/2)(W/L)(Vgs-Vt) © Digital Integrated Circuits2nd Devices I-V Characteristics q In Linear region, Ids depends on – How much charge is in the channel? – How fast is the charge moving? 3: CMOS Transistor Theory CMOS VLSI Design Slide 18 MOS Transistors – Regions Transitions 2nd Copyright© Digital Integrated © 2005 CircuitsPearson Addison-Wesley. All rights reserved. Devices Channel Charge q MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel q Qchannel = gate Vg polysilicon + + V C V gate source gs g gd drain W - - Vs channel Vd t ox n+ - + n+ Vds L SiO2 gate oxide n+ n+ (good insulator, = 3.9) εox p-type body p-type body 3: CMOS Transistor Theory CMOS VLSI Design Slide 20 Channel Charge q MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel q Qchannel = CV q C = gate Vg polysilicon + + V C V gate source gs g gd drain W - - Vs channel Vd t ox n+ - + n+ Vds L SiO2 gate oxide n+ n+ (good insulator, = 3.9) εox p-type body p-type body 3: CMOS Transistor Theory CMOS VLSI Design Slide 21 Channel Charge q MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel q Qchannel = CV q C = Cg = εoxWL/tox = CoxWL Cox = εox / tox C = 8.6*fF/um2 q V = ox gate Vg polysilicon + + V C V gate source gs g gd drain W - - Vs channel Vd t ox n+ - + n+ Vds L SiO2 gate oxide n+ n+ (good insulator, = 3.9) εox p-type body p-type body 3: CMOS Transistor Theory CMOS VLSI Design Slide 22 Channel Charge q MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel q Qchannel = CV q C = Cg = εoxWL/tox = CoxWL Cox = εox / tox q V = Vgc – Vt = (Vgs – Vds/2) – Vt gate Vg polysilicon + + V C V gate source gs g gd drain W - - Vs channel Vd t ox n+ - + n+ Vds L SiO2 gate oxide n+ n+ (good insulator, = 3.9) εox p-type body p-type body 3: CMOS Transistor Theory CMOS VLSI Design Slide 23 Carrier velocity q Charge is carried by e- q Carrier velocity v proportional to lateral E-field between source and drain q v = 3: CMOS Transistor Theory CMOS VLSI Design Slide 24 Carrier velocity q Charge is carried by e- q Carrier velocity v proportional to lateral E-field between source and drain q v = µE µ called mobility q E = 3: CMOS Transistor Theory CMOS VLSI Design Slide 25 Carrier velocity q Charge is carried by e- q Carrier velocity v proportional to lateral E-field between source and drain q v = µE µ called mobility q E = Vds/L q Time for carrier to cross channel: – t = 3: CMOS Transistor Theory CMOS VLSI Design Slide 26 Carrier velocity q Charge is carried by e- q Carrier velocity v proportional to lateral E-field between source and drain q v = µE µ called mobility q E = Vds/L q Time for carrier to cross channel: – t = L / v 3: CMOS Transistor Theory CMOS VLSI Design Slide 27 nMOS Linear I-V q Now we know – How much charge Qchannel is in the channel – How much time t each carrier takes to cross Ids = 3: CMOS Transistor Theory CMOS VLSI Design Slide 28 nMOS Linear I-V q Now we know – How much charge Qchannel is in the channel – How much time t each carrier takes to cross Q I = channel ds t = 3: CMOS Transistor Theory CMOS VLSI Design Slide 29 nMOS Linear I-V q Now we know – How much charge Qchannel is in the channel – How much time t each carrier takes to cross Q I = channel ds t W ⎛⎞Vds =µCVVox ⎜⎟gs−− t V ds L ⎝⎠2 W ⎛⎞Vds = C =β ⎜⎟VVgs−− t V ds βµox ⎝⎠2 L 3: CMOS Transistor Theory CMOS VLSI Design Slide 30 Computed Curves Linear Resistor Vgs = 5v Vgs = 4.5v Vgs = 4.0v © Digital Integrated Circuits2nd Devices nMOS Saturation I-V q If Vgd < Vt, channel pinches off near drain – When Vds > Vdsat = Vgs – Vt q Now drain voltage no longer increases current Ids = 3: CMOS Transistor Theory CMOS VLSI Design Slide 32 nMOS Saturation I-V q If Vgd < Vt, channel pinches off near drain – When Vds > Vdsat = Vgs – Vt q Now drain voltage no longer increases current ⎛⎞Vdsat IVVVds=β ⎜⎟ gs−− t dsat ⎝⎠2 3: CMOS Transistor Theory CMOS VLSI Design Slide 33 nMOS Saturation I-V q If Vgd < Vt, channel pinches off near drain – When Vds > Vdsat = Vgs – Vt q Now drain voltage no longer increases current ⎛⎞Vdsat IVVVds=β ⎜⎟ gs−− t dsat ⎝⎠2 β 2 =VV− 2 ( gs t ) 3: CMOS Transistor Theory CMOS VLSI Design Slide 34 Computed Curves Linear Resistor Vgs = 5v Vgs = 4.5v Vgs = 4.0v 3: CMOS Transistor Theory CMOS VLSI Design Slide 35 nMOS I-V Summary q Shockley 1st order transistor models ⎧ ⎪ 0 VVgs< t cutoff ⎪ ⎪ V IVVVVV⎛⎞ds linear ds=⎨β ⎜⎟ gs−− t2 ds ds < dsat ⎪ ⎝⎠ ⎪ β 2 VV− VV>saturation ⎩⎪ 2 ( gs t) ds dsat 3: CMOS Transistor Theory CMOS VLSI Design Slide 36 Example q We will be using a 0.180 µm process for your project – From TSMC Semiconductor – tox = 40 Å – µ = 180 cm2/V*s – Vt = 0.4 V q Plot Ids vs.