DOCSLIB.ORG

Miniaturization of CMOS

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Miniaturization of CMOS micromachines Review Miniaturization of CMOS 1,2,3, , 1, 1,4, 1, 5, Henry H. Radamson * y, Xiaobin He y, Qingzhu Zhang y, Jinbiao Liu y, Hushan Cui y, 1, 1, 1,2, 1,2, 1, Jinjuan Xiang y, Zhenzhen Kong y, Wenjuan Xiong y, Junjie Li y, Jianfeng Gao y, 1,2, 1,6, 1,7, 1,2, 1, Hong Yang y , Shihai Gu y, Xuewei Zhao y, Yong Du y, Jiahan Yu y and 1,2, , Guilei Wang * y 1 Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; [email protected] (X.H.); [email protected] (Q.Z.); [email protected] (J.L.); [email protected] (J.X.); [email protected] (Z.K.); [email protected] (W.X.); [email protected] (J.L.); [email protected] (J.G.); [email protected] (H.Y.); [email protected] (S.G.); [email protected] (X.Z.); [email protected] (Y.D.); [email protected] (J.Y.) 2 Microelectronics Institute, University of Chinese Academy of Sciences, Beijing 100049, China 3 Department of Electronics Design, Mid Sweden University, Holmgatan 10, 85170 Sundsvall, Sweden 4 State Key Laboratory of Advanced Materials for Smart Sensing, General Research Institute for Nonferrous Metals, Beijing 100088, China 5 Fert Beijing Institute, Big Data Brain Computing (BDBC), Beihang University, Beijing 100191, China; [email protected] 6 School of Artificial Intelligence, University of Chinese Academy of Sciences, Beijing 100049, China 7 School of Microelectronics, University of Science and Technology of China, Anhui 230026, China * Correspondence: [email protected] (H.H.R.); [email protected] (G.W.); Tel.: +86-010-8299-5793 (G.W.) The authors have equally contributed in this article. y Received: 3 March 2019; Accepted: 11 April 2019; Published: 30 April 2019 Abstract: When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era. Keywords: FinFETs; CMOS; device processing; integrated circuits 1. Introduction In 1965, Gordon Moore, the founder of Intel, published his famous paper describing the evolution of transistor density in integrated circuits. Although his first insight was to establish a business roadmap to increase the profit of the company, he later built the fundaments for technology roadmap in the semiconductor industry. Moore’s idea was based on doubling the transistor density in the chip every 18 months, which causes the transistors to become smaller in size and consumes lower power while performing at higher speed [1]. With years of continuing MOSFETs (metal oxide effect transistor) down-scaling, different non-ideal factors e.g., short channel effects (SCEs), poor electrostatics integrity, and large device variability appeared. Therefore, conventional bulk FinFET and fully depleted silicon on the insulator (FDSOI) are proposed to improve the above problems by applying low gate voltage to fully deplete the ultra-thin silicon [2]. Currently, bulk FinFET has been widely used in mass production from 22 nm to 10 nm Micromachines 2019, 10, 293; doi:10.3390/mi10050293 www.mdpi.com/journal/micromachines Micromachines 2019, 10, 293 2 of 52 node and will be extended to the 5-nm node [3–6]. In fact, the critical dimension (CD) of the device, e.g., gate length (Lg), applied voltage (VDD), and effective oxide thickness (EOT) are not strictly scaling, according to the Moore’s law. The foundries seek an improvement of driving current (IDS) at the same leakage or achieve the smaller leakage at the same IDS. On the approach to the end of the technology roadmap, the 3-nm node and the traditional bulk FinFET technologies would suffer from enormous challenges [7]. Thus, new device structures, new materials, and new integration approaches have to provide new solutions. Therefore, novel promising device architectures like fin-on-insulator (FOI) FinFET [8–11], scalloped fin FinFET [12], nanowire (NW) FETs, and the stacked NW device [13–15] have demonstrated great improvement for short channel effects (SCEs), leakage control, and higher electron and whole mobility. The fin-on-insulator (FOI) FinFET, fabricated on the bulk Si substrate with a special process takes both advantages of bulk FinFET and SOI technologies. Therefore, it may be one of the most promising candidates for further device scaling. In addition, the low cost and fully Metallic Source and Drain (MSD) process is extensively investigated for the FOI FinFET [9]. Other architecture such as scalloped fin FinFETs with mainstream all-last HKMG (high-k and metal-gate) technology could provide a larger control area and obtain a great improvement for SCEs. Stacked gate-all-around (GAA) NW or nano-sheet is also receiving increasing attention among all device structures. This is considered to be the most promising candidate beyond FinFET technologies for a 3-nm node due to its special characteristic, such as quasi-ballistic transport, steep sub-threshold slope, and one-dimensional channel geometry [13,14]. 3D-monolithic or 3D sequential CMOS technology is based on stacking active device layers on top of each other with very small 3D contact pitch (similar pitch as a standard contact) [16,17]. This approach could achieve a 14-nm circuit performance by using 3D sequential CMOS technology with lower parasitic resistance, capacitor, and signal delay. In addition, this integration scheme offers a wide spectrum of applications including (i) increasing integration density beyond device scaling, (ii) enabling neuromorphic integration where RRAM is placed between top and bottom tiers, and (iii) enabling low-cost heterogeneous integration for e.g., smart sensing arrays. However, such an integration process faces the challenges of fabricating high-performance devices in the top tier without degrading the electrical characteristics of the bottom tier [18,19]. The CMOS scaling-down in process, VDD, and temperature (PVT) are becoming a major issue for the nanoscale IC design. The need for low power induces supply voltage scaling, which makes voltage variations a significant design challenge. Moreover, the operation frequency is sensitive to die temperature variations. Therefore, it is increased at high junction temperatures. It is known that process variations are a serious concern due to uncertainty in the device and interconnects characteristics. Process variations negatively impact the speed, stability, and power consumption of traditional transistor designs. With the continuing scaling of devices, the driving current would become bigger and the frequencies of transmitted signals become higher [20,21]. This article presents how the technology roadmap deal with miniaturization of CMOS including advanced lithography for patterning nano-scaled transistors, process integration, (wet and dry) etching, strain engineering with an emphasis on SiGe epitaxy for source/drain (S/D), dopant implantation, gate formation including deposition of high-k material, and the metal gate using the atomic layer deposition (ALD) technique, and III-V materials for high carrier mobility in the channel for FinFETs. The discussions have a focus on the challenges and difficulties of the path of More Moore and even provide a glimpse of the beyond Moore era for CMOS. 2. Miniaturization Principles Figure1 shows the o fficial technology roadmap, which was originally established in the early 1970s and the semiconductor industries began to down scale the transistors [22]. In 2003, when the transistor size shrunk to sub 100 nm, the nano-electronic era was inaugurated. The continuation of down-scaling lead to the parasitic capacitance and the resistance increased. Lastly, the 2D transistors Micromachines 2019, 10, 293 3 of 52 Micromachines 2019, 10, x FOR PEER REVIEW 3 of 52 Micromachines 2019, 10, x FOR PEER REVIEW 3 of 52 were abandoned and 3D FinFETs were introduced. This is considered as a revolutionary design in the the transistor world, which paved the path for sub 22 nm FinFETs with high performance and full transistorthe transistor world, world, which which paved paved the path the for path sub for 22 su nmb 22 FinFETs nm FinFETs with high with performance high performance and full and control full control on the carrier transport in the channel. oncontrol the carrier on the transport carrier transport in the channel. in the channel. Figure 1.Miniaturization of the transistor gate length in different technology nodes and production FigureFigure 1. 1.MiniaturizationMiniaturization ofof thethe transistortransistor gategate lengthlength inin didifferentfferent technology technology nodes nodes and and production production years [22]. yearsyears [ 22[22].]. TheThe down-scalingdown-scaling ofof thethe transistorstransistors resultsresults inin operationoperation atat lowerlower supplysupply voltagesvoltages asas wellwell asas The down-scaling of the transistors results in operation at lower supply voltages as well as switchingswitching with with less less current. current. switching with less current. OnOn one one hand, hand, the the shorter shorter channel channel causes causes lower lower gate capacitance gate capacitance and higher and drive higher current drive resulting current On one hand, the shorter channel causes lower gate capacitance and higher drive current inresulting faster transistors. in faster transistors. On the other On hand, the other the shorter hand, channels the shorter contribute channels to contribute higher S/D to and higher Gate leakageS/D and resulting in faster transistors. On the other hand, the shorter channels contribute to higher S/D and DD sinceGate gateleakage oxide since becomes gate thinner.oxide becomes The smaller thinner.
Load more

Recommended publications
  • Imperial College London Department of Physics Graphene Field Effect
    Imperial College London Department of Physics Graphene Field Effect Transistors arXiv:2010.10382v2 [cond-mat.mes-hall] 20 Jul 2021 By Mohamed Warda and Khodr Badih 20 July 2021 Abstract The past decade has seen rapid growth in the research area of graphene and its application to novel electronics. With Moore's law beginning to plateau, the need for post-silicon technology in industry is becoming more apparent. Moreover, exist- ing technologies are insufficient for implementing terahertz detectors and receivers, which are required for a number of applications including medical imaging and secu- rity scanning. Graphene is considered to be a key potential candidate for replacing silicon in existing CMOS technology as well as realizing field effect transistors for terahertz detection, due to its remarkable electronic properties, with observed elec- tronic mobilities reaching up to 2 × 105 cm2 V−1 s−1 in suspended graphene sam- ples. This report reviews the physics and electronic properties of graphene in the context of graphene transistor implementations. Common techniques used to syn- thesize graphene, such as mechanical exfoliation, chemical vapor deposition, and epitaxial growth are reviewed and compared. One of the challenges associated with realizing graphene transistors is that graphene is semimetallic, with a zero bandgap, which is troublesome in the context of digital electronics applications. Thus, the report also reviews different ways of opening a bandgap in graphene by using bi- layer graphene and graphene nanoribbons. The basic operation of a conventional field effect transistor is explained and key figures of merit used in the literature are extracted. Finally, a review of some examples of state-of-the-art graphene field effect transistors is presented, with particular focus on monolayer graphene, bilayer graphene, and graphene nanoribbons.
    [Show full text]
  • Analog/Mixed-Signal Design in Finfet Technologies A.L.S
    Analog/Mixed-Signal Design in FinFET Technologies A.L.S. Loke, E. Terzioglu, A.A. Kumar, T.T. Wee, K. Rim, D. Yang, B. Yu, L. Ge, L. Sun, J.L. Holland, C. Lee, S. Yang, J. Zhu, J. Choi, H. Lakdawala, Z. Chen, W.J. Chen, S. Dundigal, S.R. Knol, C.-G. Tan, S.S.C. Song, H. Dang, P.G. Drennan, J. Yuan, P.R. Chidambaram, R. Jalilizeinali, S.J. Dillen, X. Kong, and B.M. Leary [email protected] Qualcomm Technologies, Inc. September 4, 2017 CERN ESE Seminar (Based on AACD 2017) Mobile SoC Migration to FinFET Mobile SoC is now main driver for CMOS scaling • Power, Performance, Area, Cost (PPAC) considerations, cost = f(volume) • Snapdragon™ 820 - Qualcomm Technologies’ first 14nm product • Snapdragon™ 835 – World’s first 10nm product Not drawn to scale Plenty of analog/mixed-signal content Display • PLLs & DLLs Camera • Wireline I/Os Memory • Data converters BT & WLAN • Bandgap references DSP GPU • Thermal sensors • Regulators • ESD protection CPU Audio Modem SoC technology driven by logic & SRAM scaling needs due to cost Terzioglu, Qualcomm [1] Loke et al., Analog/Mixed-Signal Design in FinFET Technologies Slide 1 Outline • Fully-Depleted FinFET Basics • Technology Considerations • Design Considerations • Conclusion Loke et al., Analog/Mixed-Signal Design in FinFET Technologies Slide 2 Towards Stronger Gate Control log (I ) gate D VGS IDsat Cox I VDS S Dlin drain I source ϕs T I CB CD off lower supply lower power DIBL body VBS VGS VTsat VTlin VDD • Capacitor divider dictates source-barrier ϕs & ID • Fully-depleted finFET weakens CB, CD steeper
    [Show full text]
  • Design of Finfet Based 1-Bit Full Adder
    ISSN (Print) : 2320 – 3765 ISSN (Online): 2278 – 8875 International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (A High Impact Factor, Monthly, Peer Reviewed Journal) Website: www.ijareeie.com Vol. 8, Issue 6, June 2019 Design of Finfet Based 1-Bit Full Adder Priti Sahu1, Ravi Tiwari2 M.Tech Scholar, Department of Electronics and Tele-Communication Engineering, Shri Shankaracharya Group of Institutions Engineering (SSGI), CSVTU, Bhilai, Chattisgarh, India Department of Electronics and Tele-Communication Engineering, Shri Shankaracharya Group of Institutions Engineering (SSGI), CSVTU, Bhilai, Chattisgarh, India ABSTRACT: This paper proposes a 1-bit Full adder using Fin type Field Effect Transistor (FinFETs) at 250nm CMOS technology. The paper is intended to reduce leakage current and leakage power, chip area, and to increase the switching speed of 1-bit Full Adder while maintaining the competitive performance with few transistors are used. In this paper, we are designed a double-gate (DG) FinFETs and extracting their transfer characteristics by using Synopsys TANNER- EDA simulation tool. We investigate the use of Double Gate FinFET technology which provides low leakage and high- performance operation by utilizing high speed and low threshold voltage transistors for logic cells. Which show that it is particularly effective in sub threshold circuits and can eliminate performance variations with Low power. A 22ns access time and frequency 0.045GHz provide 250nm CMOS process technology with 5V power supply is employed to carry out 1-bit Full Adder of speed, power and reliability compared to Metal Oxide Semiconductor Field Effect Transistor (MOSFET) based full adder designs. Hence FinFET is a promising candidate and is a better replacement for MOSFET.
    [Show full text]
  • Hybrid Memristor–CMOS Implementation of Combinational Logic Based on X-MRL †
    electronics Article Hybrid Memristor–CMOS Implementation of Combinational Logic Based on X-MRL † Khaled Alhaj Ali 1,* , Mostafa Rizk 1,2,3 , Amer Baghdadi 1 , Jean-Philippe Diguet 4 and Jalal Jomaah 3 1 IMT Atlantique, Lab-STICC CNRS, UMR, 29238 Brest, France; [email protected] (M.R.); [email protected] (A.B.) 2 Lebanese International University, School of Engineering, Block F 146404 Mazraa, Beirut 146404, Lebanon 3 Faculty of Sciences, Lebanese University, Beirut 6573, Lebanon; [email protected] 4 IRL CROSSING CNRS, Adelaide 5005, Australia; [email protected] * Correspondence: [email protected] † This paper is an extended version of our paper published in IEEE International Conference on Electronics, Circuits and Systems (ICECS) , 27–29 November 2019, as Ali, K.A.; Rizk, M.; Baghdadi, A.; Diguet, J.P.; Jomaah, J. “MRL Crossbar-Based Full Adder Design”. Abstract: A great deal of effort has recently been devoted to extending the usage of memristor technology from memory to computing. Memristor-based logic design is an emerging concept that targets efficient computing systems. Several logic families have evolved, each with different attributes. Memristor Ratioed Logic (MRL) has been recently introduced as a hybrid memristor–CMOS logic family. MRL requires an efficient design strategy that takes into consideration the implementation phase. This paper presents a novel MRL-based crossbar design: X-MRL. The proposed structure combines the density and scalability attributes of memristive crossbar arrays and the opportunity of their implementation at the top of CMOS layer. The evaluation of the proposed approach is performed through the design of an X-MRL-based full adder.
    [Show full text]
  • Three-Dimensional Integrated Circuit Design: EDA, Design And
    Integrated Circuits and Systems Series Editor Anantha Chandrakasan, Massachusetts Institute of Technology Cambridge, Massachusetts For other titles published in this series, go to http://www.springer.com/series/7236 Yuan Xie · Jason Cong · Sachin Sapatnekar Editors Three-Dimensional Integrated Circuit Design EDA, Design and Microarchitectures 123 Editors Yuan Xie Jason Cong Department of Computer Science and Department of Computer Science Engineering University of California, Los Angeles Pennsylvania State University [email protected] [email protected] Sachin Sapatnekar Department of Electrical and Computer Engineering University of Minnesota [email protected] ISBN 978-1-4419-0783-7 e-ISBN 978-1-4419-0784-4 DOI 10.1007/978-1-4419-0784-4 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2009939282 © Springer Science+Business Media, LLC 2010 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com) Foreword We live in a time of great change.
    [Show full text]
  • Memristive-Finfet Circuits for FFT & Vedic Multiplication
    Special Issue - 2016 International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 NCETET - 2016 Conference Proceedings Threshold Logic Computing: Memristive-FinFET Circuits for FFT & Vedic Multiplication Nasria A Divya R PG Scholar Assistant Professor Applied Electronics and instrumentation Electronics and Communication Younus College of Engineering and Technology Younus College of Engineering and Technology Kollam, India Kollam, India Abstract—Threshold logic computing is the simplest kind of expensive because of their area, power, and delay overhead. computing units used to build artificial neural networks. Brain In the beginning stage, threshold gates have been mimic circuits can be developed electronically in different ways. implemented using CMOS devices, Single Electron But using Memristive Threshold Logic (MTL) cells have various Transistors and Monostable-Bistable Logic Elements and advantages than Logic gates. MTL cell is used for designing FFT resonant tunnelling diodes. Capacitor-based Threshold Logic computing useful for signal processing applications and Vedic addition and multiplications for efficient Arithmetic Logic unit gates (CTL) are implemented using capacitors as weights design. MTL cell is the basic cell which consist of two parts: along with CMOS-based comparator circuits. In CMOS CTL Memristor based input voltage averaging circuits and an output gates, sum of weighted input voltage is compared with a threshold circuit. The threshold circuit is the combination of fixed reference voltage, and based on this comparison, a Op-amp and FinFET circuit. FinFET circuits indicate much logical output is produced. CTL gates are used for 2D image lower power consumption, lower chip area and operates at filtering in. These CTL gates have many advantages such as lower voltages.
    [Show full text]
  • LDMOS for Improved Performance
    > Submitted to IEEE Transactions on Electron Devices < Final MS # 8011B 1 Extended-p+ Stepped Gate (ESG) LDMOS for Improved Performance M. Jagadesh Kumar, Senior Member, IEEE and Radhakrishnan Sithanandam Abstract—In this paper, we propose a new Extended-p+ Stepped Gate (ESG) thin film SOI LDMOS with an extended-p+ region beneath the source and a stepped gate structure in the drift region of the LDMOS. The hole current generated due to impact ionization is now collected from an n+p+ junction instead of an n+p junction thus delaying the parasitic BJT action. The stepped gate structure enhances RESURF in the drift region, and minimizes the gate-drain capacitance. Based on two- dimensional simulation results, we show that the ESG LDMOS exhibits approximately 63% improvement in breakdown voltage, 38% improvement in on-resistance, 11% improvement in peak transconductance, 18% improvement in switching speed and 63% reduction in gate-drain charge density compared with the conventional LDMOS with a field plate. Index Terms—LDMOS, silicon on insulator (SOI), breakdown voltage, transconductance, on- resistance, gate charge I. INTRODUCTION ATERALLY double diffused metal oxide semiconductor (LDMOS) on SOI substrate is a promising Ltechnology for RF power amplifiers and wireless applications [1-5]. In the recent past, developing high voltage thin film LDMOS has gained importance due to the possibility of its integration with low power CMOS devices and heterogeneous microsystems [6]. But realization of high voltage devices in thin film SOI is challenging because floating body effects affect the breakdown characteristics. Often, body contacts are included to remove the floating body effects in RF devices [7].
    [Show full text]
  • The Economic Impact of Moore's Law: Evidence from When It Faltered
    The Economic Impact of Moore’s Law: Evidence from when it faltered Neil Thompson Sloan School of Management, MIT1 Abstract “Computing performance doubles every couple of years” is the popular re- phrasing of Moore’s Law, which describes the 500,000-fold increase in the number of transistors on modern computer chips. But what impact has this 50- year expansion of the technological frontier of computing had on the productivity of firms? This paper focuses on the surprise change in chip design in the mid-2000s, when Moore’s Law faltered. No longer could it provide ever-faster processors, but instead it provided multicore ones with stagnant speeds. Using the asymmetric impacts from the changeover to multicore, this paper shows that firms that were ill-suited to this change because of their software usage were much less advantaged by later improvements from Moore’s Law. Each standard deviation in this mismatch between firm software and multicore chips cost them 0.5-0.7pp in yearly total factor productivity growth. These losses are permanent, and without adaptation would reflect a lower long-term growth rate for these firms. These findings may help explain larger observed declines in the productivity growth of users of information technology. 1 I would like to thank my PhD advisors David Mowery, Lee Fleming, Brian Wright and Bronwyn Hall for excellent support and advice over the years. Thanks also to Philip Stark for his statistical guidance. This work would not have been possible without the help of computer scientists Horst Simon (Lawrence Berkeley National Lab) and Jim Demmel, Kurt Keutzer, and Dave Patterson in the Berkeley Parallel Computing Lab, I gratefully acknowledge their overall guidance, their help with the Berkeley Software Parallelism Survey and their hospitality in letting me be part of their lab.
    [Show full text]
  • Advanced MOSFET Structures and Processes for Sub-7 Nm CMOS Technologies
    Advanced MOSFET Structures and Processes for Sub-7 nm CMOS Technologies By Peng Zheng A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Engineering - Electrical Engineering and Computer Sciences in the Graduate Division of the University of California, Berkeley Committee in charge: Professor Tsu-Jae King Liu, Chair Professor Laura Waller Professor Costas J. Spanos Professor Junqiao Wu Spring 2016 © Copyright 2016 Peng Zheng All rights reserved Abstract Advanced MOSFET Structures and Processes for Sub-7 nm CMOS Technologies by Peng Zheng Doctor of Philosophy in Engineering - Electrical Engineering and Computer Sciences University of California, Berkeley Professor Tsu-Jae King Liu, Chair The remarkable proliferation of information and communication technology (ICT) – which has had dramatic economic and social impact in our society – has been enabled by the steady advancement of integrated circuit (IC) technology following Moore’s Law, which states that the number of components (transistors) on an IC “chip” doubles every two years. Increasing the number of transistors on a chip provides for lower manufacturing cost per component and improved system performance. The virtuous cycle of IC technology advancement (higher transistor density lower cost / better performance semiconductor market growth technology advancement higher transistor density etc.) has been sustained for 50 years. Semiconductor industry experts predict that the pace of increasing transistor density will slow down dramatically in the sub-20 nm (minimum half-pitch) regime. Innovations in transistor design and fabrication processes are needed to address this issue. The FinFET structure has been widely adopted at the 14/16 nm generation of CMOS technology.
    [Show full text]
  • Physical Structure of CMOS Integrated Circuits
    Physical Structure of CMOS Integrated Circuits Dae Hyun Kim EECS Washington State University References • John P. Uyemura, “Introduction to VLSI Circuits and Systems,” 2002. – Chapter 3 • Neil H. Weste and David M. Harris, “CMOS VLSI Design: A Circuits and Systems Perspective,” 2011. – Chapter 1 Goal • Understand the physical structure of CMOS integrated circuits (ICs) Logical vs. Physical • Logical structure • Physical structure Source: http://www.vlsi-expert.com/2014/11/cmos-layout-design.html Integrated Circuit Layers • Semiconductor – Transistors (active elements) • Conductor – Metal (interconnect) • Wire • Via • Insulator – Separators Integrated Circuit Layers • Silicon substrate, insulator, and two wires (3D view) Substrate • Side view Metal 1 layer Insulator Substrate • Top view Integrated Circuit Layers • Two metal layers separated by insulator (side view) Metal 2 layer Via 12 (connecting M1 and M2) Insulator Metal 1 layer Insulator Substrate • Top view Connected Not connected Integrated Circuit Layers Integrated Circuit Layers • Signal transfer speed is affected by the interconnect resistance and capacitance. – Resistance ↑ => Signal delay ↑ – Capacitance ↑ => Signal delay ↑ Integrated Circuit Layers • Resistance – = = = Direction of • : sheet resistance (constant) current flows ∙ ∙ • : resistivity (= , : conductivity) 1 – Material property (constant) – Unit: • : thickess (constant) Ω ∙ • : width (variable) • : length (variable) Cross-sectional area = • Example ∙ – : 17. , : 0.13 , : , : 1000 • = 17.1
    [Show full text]
  • Nanoelectronics
    Highlights from the Nanoelectronics for 2020 and Beyond (Nanoelectronics) NSI April 2017 The semiconductor industry will continue to be a significant driver in the modern global economy as society becomes increasingly dependent on mobile devices, the Internet of Things (IoT) emerges, massive quantities of data generated need to be stored and analyzed, and high-performance computing develops to support vital national interests in science, medicine, engineering, technology, and industry. These applications will be enabled, in part, with ever-increasing miniaturization of semiconductor-based information processing and memory devices. Continuing to shrink device dimensions is important in order to further improve chip and system performance and reduce manufacturing cost per bit. As the physical length scales of devices approach atomic dimensions, continued miniaturization is limited by the fundamental physics of current approaches. Innovation in nanoelectronics will carry complementary metal-oxide semiconductor (CMOS) technology to its physical limits and provide new methods and architectures to store and manipulate information into the future. The Nanoelectronics Nanotechnology Signature Initiative (NSI) was launched in July 2010 to accelerate the discovery and use of novel nanoscale fabrication processes and innovative concepts to produce revolutionary materials, devices, systems, and architectures to advance the field of nanoelectronics. The Nanoelectronics NSI white paper1 describes five thrust areas that focus the efforts of the six participating agencies2 on cooperative, interdependent R&D: 1. Exploring new or alternative state variables for computing. 2. Merging nanophotonics with nanoelectronics. 3. Exploring carbon-based nanoelectronics. 4. Exploiting nanoscale processes and phenomena for quantum information science. 5. Expanding the national nanoelectronics research and manufacturing infrastructure network.
    [Show full text]
  • Characterization of the Cmos Finfet Structure On
    CHARACTERIZATION OF THE CMOS FINFET STRUCTURE ON SINGLE-EVENT EFFECTS { BASIC CHARGE COLLECTION MECHANISMS AND SOFT ERROR MODES By Patrick Nsengiyumva Dissertation Submitted to the Faculty of the Graduate School of Vanderbilt University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY in Electrical Engineering May 11, 2018 Nashville, Tennessee Approved: Lloyd W. Massengill, Ph.D. Michael L. Alles, Ph.D. Bharat B. Bhuva, Ph.D. W. Timothy Holman, Ph.D. Alexander M. Powell, Ph.D. © Copyright by Patrick Nsengiyumva 2018 All Rights Reserved DEDICATION In loving memory of my parents (Boniface Bimuwiha and Anne-Marie Mwavita), my uncle (Dr. Faustin Nubaha), and my grandmother (Verediana Bikamenshi). iii ACKNOWLEDGEMENTS This dissertation work would not have been possible without the support and help of many people. First of all, I would like to express my deepest appreciation and thanks to my advisor Dr. Lloyd Massengill for his continual support, wisdom, and mentoring throughout my graduate program at Vanderbilt University. He has pushed me to look critically at my work and become a better research scholar. I would also like to thank Dr. Michael Alles and Dr. Bharat Bhuva, who have helped me identify new paths in my research and have been a constant source of ideas. I am also very grateful to Dr. W. T. Holman and Dr. Alexander Powell for serving on my committee and for their constructive comments. Special thanks go to Dr. Jeff Kauppila, Jeff Maharrey, Rachel Harrington, and Tim Haeffner for their support with test IC designs and experiments. I would also like to thank Dennis Ball (Scooter) for his tremendous help with TCAD models.
    [Show full text]