micromachines Review Miniaturization of CMOS 1,2,3, , 1, 1,4, 1, 5, Henry H. Radamson * y, Xiaobin He y, Qingzhu Zhang y, Jinbiao Liu y, Hushan Cui y, 1, 1, 1,2, 1,2, 1, Jinjuan Xiang y, Zhenzhen Kong y, Wenjuan Xiong y, Junjie Li y, Jianfeng Gao y, 1,2, 1,6, 1,7, 1,2, 1, Hong Yang y , Shihai Gu y, Xuewei Zhao y, Yong Du y, Jiahan Yu y and 1,2, , Guilei Wang * y 1 Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; [email protected] (X.H.); [email protected] (Q.Z.); [email protected] (J.L.); [email protected] (J.X.); [email protected] (Z.K.); [email protected] (W.X.); [email protected] (J.L.); [email protected] (J.G.); [email protected] (H.Y.); [email protected] (S.G.); [email protected] (X.Z.); [email protected] (Y.D.); [email protected] (J.Y.) 2 Microelectronics Institute, University of Chinese Academy of Sciences, Beijing 100049, China 3 Department of Electronics Design, Mid Sweden University, Holmgatan 10, 85170 Sundsvall, Sweden 4 State Key Laboratory of Advanced Materials for Smart Sensing, General Research Institute for Nonferrous Metals, Beijing 100088, China 5 Fert Beijing Institute, Big Data Brain Computing (BDBC), Beihang University, Beijing 100191, China; [email protected] 6 School of Artificial Intelligence, University of Chinese Academy of Sciences, Beijing 100049, China 7 School of Microelectronics, University of Science and Technology of China, Anhui 230026, China * Correspondence: [email protected] (H.H.R.); [email protected] (G.W.); Tel.: +86-010-8299-5793 (G.W.) The authors have equally contributed in this article. y Received: 3 March 2019; Accepted: 11 April 2019; Published: 30 April 2019 Abstract: When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era. Keywords: FinFETs; CMOS; device processing; integrated circuits 1. Introduction In 1965, Gordon Moore, the founder of Intel, published his famous paper describing the evolution of transistor density in integrated circuits. Although his first insight was to establish a business roadmap to increase the profit of the company, he later built the fundaments for technology roadmap in the semiconductor industry. Moore’s idea was based on doubling the transistor density in the chip every 18 months, which causes the transistors to become smaller in size and consumes lower power while performing at higher speed [1]. With years of continuing MOSFETs (metal oxide effect transistor) down-scaling, different non-ideal factors e.g., short channel effects (SCEs), poor electrostatics integrity, and large device variability appeared. Therefore, conventional bulk FinFET and fully depleted silicon on the insulator (FDSOI) are proposed to improve the above problems by applying low gate voltage to fully deplete the ultra-thin silicon [2]. Currently, bulk FinFET has been widely used in mass production from 22 nm to 10 nm Micromachines 2019, 10, 293; doi:10.3390/mi10050293 www.mdpi.com/journal/micromachines Micromachines 2019, 10, 293 2 of 52 node and will be extended to the 5-nm node [3–6]. In fact, the critical dimension (CD) of the device, e.g., gate length (Lg), applied voltage (VDD), and effective oxide thickness (EOT) are not strictly scaling, according to the Moore’s law. The foundries seek an improvement of driving current (IDS) at the same leakage or achieve the smaller leakage at the same IDS. On the approach to the end of the technology roadmap, the 3-nm node and the traditional bulk FinFET technologies would suffer from enormous challenges [7]. Thus, new device structures, new materials, and new integration approaches have to provide new solutions. Therefore, novel promising device architectures like fin-on-insulator (FOI) FinFET [8–11], scalloped fin FinFET [12], nanowire (NW) FETs, and the stacked NW device [13–15] have demonstrated great improvement for short channel effects (SCEs), leakage control, and higher electron and whole mobility. The fin-on-insulator (FOI) FinFET, fabricated on the bulk Si substrate with a special process takes both advantages of bulk FinFET and SOI technologies. Therefore, it may be one of the most promising candidates for further device scaling. In addition, the low cost and fully Metallic Source and Drain (MSD) process is extensively investigated for the FOI FinFET [9]. Other architecture such as scalloped fin FinFETs with mainstream all-last HKMG (high-k and metal-gate) technology could provide a larger control area and obtain a great improvement for SCEs. Stacked gate-all-around (GAA) NW or nano-sheet is also receiving increasing attention among all device structures. This is considered to be the most promising candidate beyond FinFET technologies for a 3-nm node due to its special characteristic, such as quasi-ballistic transport, steep sub-threshold slope, and one-dimensional channel geometry [13,14]. 3D-monolithic or 3D sequential CMOS technology is based on stacking active device layers on top of each other with very small 3D contact pitch (similar pitch as a standard contact) [16,17]. This approach could achieve a 14-nm circuit performance by using 3D sequential CMOS technology with lower parasitic resistance, capacitor, and signal delay. In addition, this integration scheme offers a wide spectrum of applications including (i) increasing integration density beyond device scaling, (ii) enabling neuromorphic integration where RRAM is placed between top and bottom tiers, and (iii) enabling low-cost heterogeneous integration for e.g., smart sensing arrays. However, such an integration process faces the challenges of fabricating high-performance devices in the top tier without degrading the electrical characteristics of the bottom tier [18,19]. The CMOS scaling-down in process, VDD, and temperature (PVT) are becoming a major issue for the nanoscale IC design. The need for low power induces supply voltage scaling, which makes voltage variations a significant design challenge. Moreover, the operation frequency is sensitive to die temperature variations. Therefore, it is increased at high junction temperatures. It is known that process variations are a serious concern due to uncertainty in the device and interconnects characteristics. Process variations negatively impact the speed, stability, and power consumption of traditional transistor designs. With the continuing scaling of devices, the driving current would become bigger and the frequencies of transmitted signals become higher [20,21]. This article presents how the technology roadmap deal with miniaturization of CMOS including advanced lithography for patterning nano-scaled transistors, process integration, (wet and dry) etching, strain engineering with an emphasis on SiGe epitaxy for source/drain (S/D), dopant implantation, gate formation including deposition of high-k material, and the metal gate using the atomic layer deposition (ALD) technique, and III-V materials for high carrier mobility in the channel for FinFETs. The discussions have a focus on the challenges and difficulties of the path of More Moore and even provide a glimpse of the beyond Moore era for CMOS. 2. Miniaturization Principles Figure1 shows the o fficial technology roadmap, which was originally established in the early 1970s and the semiconductor industries began to down scale the transistors [22]. In 2003, when the transistor size shrunk to sub 100 nm, the nano-electronic era was inaugurated. The continuation of down-scaling lead to the parasitic capacitance and the resistance increased. Lastly, the 2D transistors Micromachines 2019, 10, 293 3 of 52 Micromachines 2019, 10, x FOR PEER REVIEW 3 of 52 Micromachines 2019, 10, x FOR PEER REVIEW 3 of 52 were abandoned and 3D FinFETs were introduced. This is considered as a revolutionary design in the the transistor world, which paved the path for sub 22 nm FinFETs with high performance and full transistorthe transistor world, world, which which paved paved the path the for path sub for 22 su nmb 22 FinFETs nm FinFETs with high with performance high performance and full and control full control on the carrier transport in the channel. oncontrol the carrier on the transport carrier transport in the channel. in the channel. Figure 1.Miniaturization of the transistor gate length in different technology nodes and production FigureFigure 1. 1.MiniaturizationMiniaturization ofof thethe transistortransistor gategate lengthlength inin didifferentfferent technology technology nodes nodes and and production production years [22]. yearsyears [ 22[22].]. TheThe down-scalingdown-scaling ofof thethe transistorstransistors resultsresults inin operationoperation atat lowerlower supplysupply voltagesvoltages asas wellwell asas The down-scaling of the transistors results in operation at lower supply voltages as well as switchingswitching with with less less current. current. switching with less current. OnOn one one hand, hand, the the shorter shorter channel channel causes causes lower lower gate capacitance gate capacitance and higher and drive higher current drive resulting current On one hand, the shorter channel causes lower gate capacitance and higher drive current inresulting faster transistors. in faster transistors. On the other On hand, the other the shorter hand, channels the shorter contribute channels to contribute higher S/D to and higher Gate leakageS/D and resulting in faster transistors. On the other hand, the shorter channels contribute to higher S/D and DD sinceGate gateleakage oxide since becomes gate thinner.oxide becomes The smaller thinner.