Integration of 100V LDMOS Devices in 0.35Μm CMOS Technology

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Proceedings of the 23rd International Symposium on Power Semiconductor Devices & IC's May 23-26, 2011 San Diego, CA Integration of 100V LDMOS Devices in 0.35µm CMOS Technology Soon Tat Kong, Paul Stribley, Chris Lee, * Michaelina Ong X-FAB Semiconductor Foundries AG, Tamerton Road, Roborough, Plymouth, UK, PL6 7BQ *X-FAB Sarawak Sdn. Bhd. Kuching, Sarawak, Malaysia E-mail: [email protected] Ph: +44 1752693235, Fax: +44 1752693200

Abstract—Successful integration of 100V can be easily observed and identified by electrical LDMOS devices in 0.35µm CMOS technology is characteristics, e.g. a breakdown on the output presented in this paper. These integrated devices are characteristics. Device power dissipation has also been enhanced N-type and P-type LDMOS which are shown and cause “self-heating” effects which reduce the compatible with thin (14nm) and thick (40nm) layers efficiency of the device and modify its electrical of gate oxide. A breakdown voltage of more than 100V properties. 2 with RDS (ON) =200/180mΩ.mm for N-type LDMOS 2 2. DEVICE STRUCTURES AND OPERATIONS and RDS (ON) =690/640mΩ.mm for P-type LDMOS with 14nm/40nm gate oxide thickness.

1. INTRODUCTION Today, integration of High-Voltage (HV) Lateral Diffused MOS transistors (LDMOS) and low-voltage CMOS devices are the key solution for the smart-power, mixed signals ASICs (Application-Specific Integrated Circuits) and power IC applications [1-3]. Also, there are ever increasing demands for routinely integrating low voltage and high voltage devices on the same wafer

driven by the trend of System on Chip (SOC) technology. Fig.1: The simplified cross-section of 100V N-type LDMOS Such integration provides the benefits of miniaturisation, low energy consumption, high-level of integration, Fig.1 and 2 show the simplified cross-sections of 100V performance and cost effectiveness that enable SOC N- type and P-type transistors respectively. These devices manufactures to create lower-power, high-density, can be easily fabricated with low-voltage CMOS circuitry higher-performing systems. on the same chip. The cross-section of the N-type Basically, an integrated circuit may contain transistor with linearly graded doping (Deep N-well) in either an HV N-type LDMOS or HV P-type LDMOS the whole drift region is used, in order to achieve very structure or even both, commonly used for output power high breakdown voltage. Also, the deep N-well region is stages of an integrated circuit that comprise a signal used under the P-Well region to give a high side processing and control circuitry [4-5]. In this work, we breakdown voltage. In general, this device structure is propose 100V HV N-type and P-type LDMOS devices in appropriate for high and low side circuits. standard 0.35µm technology [6]. From the design of HV devices point of view, the following hot topics need to be mentioned: - firstly, the device breakdown and RDS(ON) resistance; secondly, the maximum voltage or current boundaries, and finally temperature dependent characteristics during operation. Basically, reduced RDS(ON) resistance gives a smaller temperature rise and therefore reduces the risk of device destruction during switching. Also, it can reduce the cost of packaging and avoids the need for a cooling system. In addition, maximum voltage or current boundaries of HV Fig.2 : The simplified cross-section of 100V P-type LDMOS devices are defined as the voltage and current conditions within which the device can be expected to operate The 100V P-type LDMOS structure is designed reliably for long time periods. Beyond maximum voltage for high side only. The deep N-well doping has been or current boundaries, the transistors suffer electrical optimized to achieve low RDS(ON) resistance for 100V wear-out and possibly device destruction through charge breakdown. The P-well diffuses both vertically and capture, self-heating or breakdown mechanisms. These laterally to optimize the drift region of the P-type effects are present only at very large drain voltages and LDMOS.

The enhanced 100V N-type and P-type transistors were tested on a Signatone probe station with a Keithley Model-4200SCS semiconductor characterization system. The maximum applicable gate voltage is 5V for the devices with gate oxide thickness of 14nm. The device dimensions (W x L) of the N-type and P-type LDMOS devices are 20 µm x 1.1µm and 20 µm x 2µm T =27ºC respectively. J TJ=125ºC . A. Breakdown Voltage

TJ=27ºC VGS [V] ID TJ=125ºC [A] (a) N-type LDMOS with 14nm gate oxide thickness

TJ=27ºC TJ=125ºC

VDS [V]

(a) N-type LDMOS with 14nm gate oxide thickness

TJ=27ºC VGS [V] TJ=125ºC ID [A] (b) P-type LDMOS with 14nm gate oxide thickness

Fig. 4 Typical transfer characteristics of 100V N-type and P- type LDMOS transistors at TJ=27ºC and TJ=125ºC

Fig. 4(a) and (b) show the transfers characteristic curves of N-type and P-type devices at room temperature (blue

trace) and high temperature (red trace). Threshold voltage was extracted from these characteristics at a VDS [V] current level of 1µA. It can be seen that the threshold voltage of 100V devices changes with temperature and (b) P-type LDMOS with 14nm gate oxide thickness that the drive current reduces. At TJ=27ºC, it was shown that P-type LDMOS Fig. 3: Typical Drain-Source breakdown voltage of 100V had a higher threshold voltage of about -1.12V compared LDMOS devices at TJ=27ºC and TJ=125ºC to 0.88V for the N-type LDMOS. This variation comes from the difference in doping density and channel length The breakdown voltage characteristic of N-type and P- in the P-type LDMOS channel compared with that in the type LDMOS are measured as shown in Fig.3 (a) and (b). N-type LDMOS channel. The measured peak In this case, the leakage currents of N-type LDMOS at transconductance values of the N-type and P-type TJ=27ºC (blue trace) and 125ºC (red trace) are transistors at TJ=27ºC are 9.6E-5 A/V and 3.0E-5 A/V approximate equal to 2pA and 0.5nA respectively. The respectively. breakdown voltage of N-type & P-type LDMOS are approximately 120V & 135V at TJ=27ºC and 125ºC.

177 C. Output Characteristics Table 1: Typical RDS(ON) resistance of N-type and P-type transistors for thin gate oxide (14nm) and thick gate oxide (40nm) structures T =27ºC TJ =27ºC T =125ºCJ Device type Ω 2 I TJ =125ºC Specific RDS(ON) resistance [m .mm ] D J (BV=100V) [mA] VGS= 5V Thin gate oxide Thick gate oxide

thickness (14nm) thickness (40nm) N-type 200 180

V = 4V P-type 690 640 GS

VGS = 3V D. 1/f Flicker Noise

It is well known that flicker noise is strongly dependent V = 2V GS on the interface quality of the gate oxide [7]. Thus, the

flicker noise of the 100V N-type and P-type devices with gate oxide thickness of 14nm was measured with a BTA 9812A system. It consists of a controller unit and an (a) N-type LDMOS with 14nm gate oxide thickness amplifier/filter unit used for detection and amplification of the noise current generated by the 100V devices. Flicker noise model, which is always associated with a power spectral density (Sid). It has been described VGS = -2V in SPICE noise models [8] as:-

I D V = -3V (1) [mA] Id GS

Where KF is a flicker noise coefficient, AF is a flicker noise exponent (typically between 0.5-2) and f is the VGS = -4V analysis frequency. The frequency exponent (EF) is bias-

dependent. COX is the gate oxide capacitance and Leff is the effective channel length of the 100V LDMOS VGS = -5V T =27ºC devices. It is important to note that reduced LDMOS T =27ºCJ JT =125ºC dimensions are accompanied by an increased level of T =125ºCJ J noise. Fig.6 (a) and (b) show a typical drain current noise characteristic measured in the saturation region (VDS= (b) P-type LDMOS with 14nm gate oxide thickness 20V) for the 100V N-type and P-type devices. The measured frequency range is between 25 Hz to 100K Hz. Fig. 5: Typical output characteristics of 100V N-type and P- It was shown that the flicker noise spectrum for both type LDMOS transistors at TJ=27ºC and TJ=125ºC devices clearly exhibits good low-frequency noise spectra. Fig. 5 (a) and (b) show the measured output In this work, the flicker noise of the 100V N- characteristics of the 100V N-type and P-type transistors type and P-type devices have been modeled based on at TJ=27ºC and 125ºC. These curves were obtained by equation 1. A pragmatic approach has been taken to sweeping the drain voltage from 0 to 100V for each value include the effect of this form of noise in 100V transistors of gate voltage sweeping from 0V to 5V in steps of 1V. such that the modelled flicker noise can be included in Self heating is observed in the negative slope of the circuit simulations. Thus, the LDMOS devices were curves at high VGS. It was shown that both devices can simulated using HSPICE simulator with BSIM3V3 operate up to the maximum VGS rating of 5 V with VDS = models for a fixed combination of the drain (+/- 20V) and 100V. Table 1 shows the summary of the RDS(ON) the gate voltages at TJ=27ºC. resistance of N-type and P-type transistors for the thin The measured noise characteristics are compared gate oxide (14nm) and thick gate oxide (40nm) structures. with the simulations. The KF and AF values of N-type The maximum applicable gate voltages of the thin and LDMOS used in the simulations are 2.82E-28 and 1.1 thick gate-oxide devices are 5V and 12V respectively. respectively. For P-type LDMOS, parameter extraction values of KF and AF are 1.06E-28 and 1.42. The EF parameter values of N-type and P-type LDMOS devices

are 0.96 and 1.11 respectively.

178 Conference, 1992. ESSDERC '92. 22nd European, PP.555-558. VDS= 20V [2] M.Elwin et al, “Optimization of 100V high side LDMOS using multiple simulation techniques” ISPSD 2009, PP. 104-107.

[3] J. Van der Pol et al., "A-BCD, An economic l00V RESURF silicon-on-insulator BCD technology for VGS= 5V, IG=1.37E12 consumer and automotive applications, ISPSD 2000, VGS= 1.5V, IG=5.60E13 PP. 327-330. [4] P.Igic et al, “Perspective on Power IC technology: VGS= 1.0V, IG=1.40E13 From design lab to wafer fab”, MIEL 2010, PP. 73- 77. [5] Xiaorong Luo et al, “A High-Voltage LDMOS

Compatible With High-Voltage Integrated Circuits

(a) N-type LDMOS on p-Type SOI Layer”, IEEE Electron Device Letters, 2009, PP.1093-1095. [6] XFAB Process & Device Specification XH035

VDS= -20V [7] K.K.Hung et al, “Flicker noise characteristics of advanced MOS technologies”, IEDM 1988, PP.34- 37. VGS= -5V, IG=-1.12E12 [8] N.H.Hamid et al, “Time-domain modeling of low- frequency noise in deep-sub micrometer MOSFET”, VGS= -2V, IG=-2.50E13 IEEE Transactions on Circuits and Systems, PP. 245- 257. VGS= -1.5V, IG=-8.0E14

(b) P-type LDMOS

Fig. 6: Typical drain current flicker noise characteristics of 100V N-type and P-type LDMOS transistors at TJ=27ºC

4. CONCLUSION

The 100V high-voltage LDMOS transistor structures integrated within 0.35µm technology have been successfully implemented and tested. This process development is compatible with CMOS standard processing. Experimental results show that the LDMOS structure has a breakdown voltage of more than 100 volts for both N-type LDMOS and P-type LDMOS transistor structures. Moreover, these 100V devices characteristics show excellent performances in term of breakdown voltage, RDS(ON) resistance, high temperature and normal flicker noise.

ACKNOWLEDGMENT

The authors would like to thank Suba Subramania, Ian Macpherson and Roberto Gaertner for their support of this work.

4. REFERENCES [1] J.S. Writter, “A modular BICMOS technology includilng 85V DMOS devices for analogue/digital ASIC applications”, Solid State Device Research

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