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RF CMOS Technology for MMIC Microelectronics Reliability 42 (2002) 721–733 www.elsevier.com/locate/microrel RF CMOS technology for MMIC Chun-Yen Chang *, Jiong-Guang Su, Shyh-Chyi Wong, Tiao-Yuan Huang, Yuan-Chen Sun Department of Electronics Engineering, Institute of Electronics, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan, ROC Received6 December 2001 Abstract This paper presents a high performance RF CMOS technology with a complete portfolio of RF andbase band components for single-chip systems. Using an optimized0.13 lm CMOS topology, fT of 86 GHz and fmax of 73 GHz are obtained, in addition to a NFmin of 1.5 dB without ground-shielded signal pad. The high-Q accumulation-mode and diode varactors are optimized to perform a high tuning range of 47% and 25%, respectively. Inductors with a quality factor of 18 at 1.7 nH are obtainedusing copper interconnect, while capacitors with high unit capacitance andquality factor are fabricated with metal-insulator-metal structures. Finally, a deep n-well isolation is adopted to suppress the interblock coupling noise penetrating through substrate by 40 and25 dBat 0.1 and2.4 GHz, respectively. These results clearly demonstrate that CMOS technology can provide a complete solution for single-chip wireless systems. Ó 2002 Elsevier Science Ltd. All rights reserved. 1. Introduction used in advanced CMOS technologies. Thirdly, the coupling noise propagation through the substrate, due Successful implementation of the entire circuit blocks to noise generated during CMOS digital switching, in a single-chip requires the integration of precise and complicates the integration of digital, analog and RF high performance passive as well as active components blocks on the same chip [4,5]. Isolation among each [1]. In recent years CMOS technologies have become individual RF blocks become crucial in implementing quite attractive for RF circuit implementation due to high precision andhigh quality RF circuits. aggressive scaling, high-speedperformance, andcost In this paper, optimization of device design using an reduction. In the development of short-range wireless existing logic CMOS baseline for RF circuit applications communications, CMOS has receivedtremendousin- is discussed [3,6–11]. This approach is quite promising terest by integration with high performance digital cir- because of its compatibility with existing logic CMOS cuits andhigh-speedanalog circuits [2]. Nonetheless, technology andinherent reliability. Various high- Q var- several major issues need to be addressed for adopting actors are investigated. The resultant integrated varac- CMOS to RF products. First of all, the RF performance tors can be successfully implementedas the capacitive of MOS transistor itself represents a bottleneck due to tuning elements for monolithic microwave ICs (MMIC). limitedcut-off frequency ( fT), maximum oscillation fre- The on-chip inductors, which often are a performance quency (fmax), andhigh-frequency noise performance limiting component in many important RF circuits, such (NFmin) [3]. Secondly, the fabrication of RF passive as voltage-controlledoscillators (VCO) phase noise [12], components with high quality factor (Q) is in direct low-noise amplifiers (LNA) bandwidth [13], and passive conflict with the fine-pitch andthin-line metallization filters loss, are also presented. Additionally, the metal- insulator-metal (MiM) capacitors with their highly linearity, are discussed by observing their RF charac- * Corresponding author. Tel.: +886-3-571-8083; fax: +886-3- teristics. Finally, the use of a deep n-well isolation for 572-1500. integrating RF blocks with low coupling noise is also E-mail address: [email protected] (C.-Y. Chang). discussed. 0026-2714/02/$ - see front matter Ó 2002 Elsevier Science Ltd. All rights reserved. PII: S0026-2714(02)00006-9 722 C.-Y. Chang et al. / Microelectronics Reliability 42 (2002) 721–733 This paper is organizedas follows. After a brief in- Lastly, the extrinsic gate-to-body capacitance Cgbe and troduction in Section 1, RF performance of MOSFET is intrinsic capacitance Cgbi can be incorporatedinto the described in Section 2. Section 3 describes the varactors, whole gate-to-body capacitance Cgb, as shown below: while Section 4 discusses the on-chip inductors. The C ¼ C þ C : ð4Þ MiM capacitors are discussed in Section 5, and the gb gbi gbe substrate coupling is discussed in Section 6. Finally, a Hence, the small-signal equivalent circuit can be brief conclusion is given in Section 7. further constructedas shown in Fig. 2(b) by taking into account (2)–(4). For two-port common-source S- parameter measurements, the source andbodyare tied 2. RF performance of MOSFET to the ground, while the gate and drain are connected to the input andoutput ports respectively. So to obtain Y- 2.1. Small-signal model analysis of MOSFET parameters that reflect the configuration of measure- ment, source and body nodes in Fig. 2(b) should be To investigate the RF figure of merit (FOM) for grounded. The Y-parameters can be derived according MOSFET, we first concentrate on the small-signal to Fig. 2(b), andis shown below [15,16]: model of MOSFET. The cross-section of a MOSFET is shown in Fig. 1. The intrinsic parts of the MOSFET, jxCgg 2 2 y11 ffi ffi x RgCgg þ jxCgg; enclosedin the box with broken lines in Fig. 1, are re- 1 þ jxRgCgg sponsible for the transistor action, andconsist of the ÀjxC y ffi gd ffiÀx2R C C À jxC ; gate, gate oxide, inversion layer and the depletion region 12 1 jxR C g gg gd gd þ ÀÁg gg between source anddrain.The extrinsic parts of MOS- gm À jx Cm þ Cgd FET, which are locatedoutsidethe box, consist of all the y ffi 21 1 þ jxR C parasitics. The complete small-signal equivalent circuit g Àgg Á 2 ð5Þ for RF application is as shown in Fig. 2(a). The gate ffi gm À x ÀRgCgg Cm þ Cgd Á transconductance gm, source-drain conductance gds and À jx C þ C þ g R C ; ÀÁm gd m g gg body transconductance gmb describe the channel trans- gds þ jx Cbd þ Cgd port current [14] with the following relation: y ffi 22 1 jxR C þ g Àgg Á iT ¼ gmvgsi þ gdsvdsi þ gmbvbsi; ð1Þ 2 ffi gds þ x ÀRgCgg Cbd þ Cgd Á where vgsi, vdsi and vbsi represent the voltage changes of þ jx Cbd þ Cgd À gdsRgCgg ; the intrinsic parts. In addition to the transport current, charge storage effects are governedby the intrinsic ca- where Cgg ¼ Cgs þ Cgd þ Cgb, and Cm is the transcapac- itance that equals to the difference between intrinsic pacitance Cgsi, Cgdi, Csbi, Cdbi and Cgbi. drain-to-gate capacitance and gate-to-drain capacitance The gate resistance Rg is composedof the resistance of polygate andcontact, while the source/drainresis- (i.e., Cdgi À Cgdi). The derivation of (5) neglects the source/drain resistance and the p-well resistance, and tance Rs=Rd includes the spreading resistance, diffusion resistance, andcontact resistance of source/drain.The p- assumes RgCgg 1. The Y-parameters are very useful for analyzing RF FOM of MOSFET. well resistance is modeled by Rsb, Rdb and Rdsb which is the proximity resistance between source anddrain[15, 16]. Finally, capacitance Cgse and Cgde comprise the 2.2. Layout of MOSFET cell overlap capacitance andthe outer fringing capacitance between gate andsource/drain,which is in parallel with The schematic top-view of MOSFET with finger-type Cgsi and Cgdi. Hence, the whole gate-to-source capaci- gate andp-well contacts, which will be called‘‘MOSFET tance Cgs andgate-to-draincapacitance Cgd can be rep- cell’’ in this paper, is shown in Fig. 3(a). All fingers have resentedas the same gate length Lg. The total gate width Wt thus equals to the unit finger length (Wf ) multipliedby the Cgs ¼ Cgsi þ Cgse; total finger number (m). A wide gate width is often used ð2Þ Cgd ¼ Cgdi þ Cgde: to improve the transconductance of the MOSFET cell, however, gate resistance increases because of the wide In addition, source and drain junction capacitance Cjsb gate width. To alleviate this undesirable effect, multi- and Cjdb are in parallel with Csbi and Cdbi, respectively. finger gate structure is generally employedto effectively Hence, the whole source-to-body capacitance Csb and reduce the gate resistance. For MOSFET cell with multi- drain-to-body capacitance Cdb can be representedas finger gate structure, the gate resistance is reduced by the square of the finger number. Further, since gate contacts Csb ¼ Csbi þ Cjsb; ð3Þ are designed on both sides of each finger, the gate re- Cdb ¼ Cdbi þ Cjdb: sistance is reduced by a factor of 12 due to the distri- C.-Y. Chang et al. / Microelectronics Reliability 42 (2002) 721–733 723 Fig. 1. The cross-section of MOSFET including the parasitics for small-signal equivalent circuit. Fig. 2. Quasi-static small-signal model of MOSFET for RF Fig. 3. (a) Top-view of MOSFET cell with multi-finger gates applications: (a) incorporating all parasitics, and(b) a simpli- for RF applications. The gate contacts are locatedat the two fiedversion. ends of polygate. Wf and m represent unit finger length and finger number, respectively. (b) Three methods to scale up Wt. bution nature in high-frequency range [17]. In this study, multiple ohmic contacts to p-well substrate are formed substrate resistance andcoupling noise [18,19]. It should to surroundthe active region, as shown in Fig. 3(a). be notedthat ohmic contacts to p-well substrate can also These contacts serve as guard-ring to further reduce the be designed on only the two sides of the active region. 724 C.-Y. Chang et al. / Microelectronics Reliability 42 (2002) 721–733 The latter layout has the advantages of easy character- ization andmodelingof the substrate resistance [20,21].
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