MOSFET Modeling for RF IC Design Yuhua Cheng, Senior Member, IEEE, M

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1286 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY 2005 MOSFET Modeling for RF IC Design Yuhua Cheng, Senior Member, IEEE, M. Jamal Deen, Fellow, IEEE, and Chih-Hung Chen, Member, IEEE

Invited Paper

Abstract—High-frequency (HF) modeling of MOSFETs for focus on the dc drain current, conductances, and intrinsic charge/ radio-frequency (RF) integrated circuit (IC) design is discussed. capacitance behavior up to the megahertz range.1 However, as Modeling of the intrinsic device and the extrinsic components is the operating frequency increases to the gigahertz range, the im- discussed by accounting for important physical effects at both dc and HF. The concepts of equivalent circuits representing both portance of the extrinsic components rivals that of the intrinsic intrinsic and extrinsic components in a MOSFET are analyzed to counterparts. Therefore, an RF model with the consideration obtain a physics-based RF model. The procedures of the HF model of the HF behavior of both intrinsic and extrinsic components parameter extraction are also developed. A subcircuit RF model in MOSFETs is extremely important to achieve accurate and based on the discussed approaches can be developed with good predicts results in the simulation of a designed circuit. model accuracy. Further, noise modeling is discussed by analyzing the theoretical and experimental results in HF noise modeling. Compared with the MOSFET modeling for digital and low- Analytical calculation of the noise sources has been discussed frequency analog applications, the HF modeling of MOSFETs is to understand the noise characteristics, including induced gate more challenging. All of the requirements for a MOSFET model noise. The distortion behavior of MOSFET and modeling are also in low-frequency application, such as continuity, accuracy, and discussed. The fact that a MOSFET has much higher “low-fre- scaleability of the dc and capacitance models should be main- quency limit” is useful for designers and modelers to validate the distortion of a MOSFET model for RF application. An RF model tained in an RF model. In addition, there are further important could well predict the distortion behavior of MOSFETs if it can requirements of the RF models. accurately describe both dc and ac small-signal characteristics 1) The model should accurately predict bias dependence of with proper parameter extraction. small-signal parameters at HF operation. Index Terms—High-frequency (HF) MOSFET model, MOSFET 2) The model should correctly describe the nonlinear be- modeling, MOS noise, noise modeling, radio-frequency (RF) IC de- havior of the devices in order to permit accurate simu- sign, radio-frequency (RF) modeling, RFCMOS, RF noise. lation of intermodulation distortion and high-speed large- signal operation. I. INTRODUCTION 3) The model should correctly and accurately predict HF noise which is important for the design of, for example, ITH fast growth in the radio-frequency (RF) wireless low-noise amplifiers (LNAs). communications market, the demand for high-per- W 4) The model should include the non-quasi-static (NQS) ef- formance but low-cost RF solutions is rising. This advanced fect so it can describe the device behavior at very high performance of MOSFETs is attractive for HF circuit de- frequency range in which NQS effect will degrade the design in view of a system-on-a-chip realization, where digital, vice performance significantly and cannot be ignored. mixed-signal baseband, and RF transceiver blocks would be 5) The gate resistance should be modeled and included in the integrated on a single chip [1]–[3]. For RF products, time simulation. to market and design cycle reduction depend greatly on the 6) The extrinsic source and drain resistances should be mod- capability of the design environment to predict circuit perfor- eled as real external resistors, instead of only a correction mance accurately using simulation. To have an efficient design to the drain current with a virtual component. environment, design tools with accurate models for devices and 7) Substrate coupling in a MOSFET, that is, the contribution interconnect parasitics are essential. It has been known that for of substrate resistance, needs to be modeled physically analog and RF applications, the accuracy of circuit simulation is and accurately using appropriate substrate network for the strongly determined by device models. Accurate device models model to be used in RF applications. become crucial to predict the circuit performance correctly. 8) A bias dependent overlap capacitance model, which accu- MOS transistor models have been originally developed for rately describes the parasitic capacitive contributions be- digital and low-frequency analog circuit design [4]–[6] which tween the gate and drain/source, needs to be included. 9) All external components (if it is a subcircuit model) Manuscript received August 30, 2004; revised December 20, 2004. The re- should be physics-based and geometrically scaleable so view of this paper was arranged by Editor A. Wang. Y. Cheng is with Siliconlinx, Inc., Irvine, CA 92619 USA (e-mail: that the model can be used in predictive and statistical [email protected]). modeling for RF applications. M. J. Deen and C.-H. Chen are with McMaster University, Hamilton L8S 4K1 ON, Canada (e-mail: 2. [email protected]; [email protected]. 1See also http://www.semiconductors.philips.com/Philips_Models for the Digital Object Identifier 10.1109/TED.2005.850656 Mos9 manual.

A. Modeling of the Intrinsic MOSFET To meet the requirements discussed above, an RF MOSFET model should be derived with the inclusions of most (if not all) important physical effects in a modern MOSFET, such as normal and reverse short-channel and narrow-width effects, channel length modulation, drain-induced barrier lowering (DIBL), velocity saturation, mobility degradation due to vertical electric field, impact ionization, band-to-band tunneling, polysilicon depletion, velocity overshoot, self-heating, and channel quantization [17]. A compact model includes many mathematical Fig. 1. MOSFET schematic cross section with the parasitic components [39]. equations for different physical mechanisms. The most important and essential parts are the dc and capacitance models. It has A common modeling approach for RF applications is to build been found that the model accuracy in fittings of HF small-signal subcircuits based on the intrinsic MOSFET that has been mod- parameters and large-signal distortion of an RF MOSFET is eled well for analog applications [7]–[11]. The accuracy of such basicallydeterminedbythedcandcapacitancemodels[18],[19]. a model depends on how to establish subcircuits with the cor- In the dc model, the channel charge and mobility need to be rect understanding of the device physics in HF operation, how modeled carefully to describe the current characteristics accu- to model the HF behavior of intrinsic devices and extrinsic par- rately and physically, based on which, different physical effects asitics, and how to extract parameters appropriately for the el- can be added. In modeling the channel charge, physical effects ements of the subcircuit. Currently, most RF modeling activi- such as short-channel effect, narrow-width effect, nonuniform ties focus on the above subcircuit approach based on different doping effect, and quantization effect, etc. should be accounted compact MOSFET models that are developed for digital and for in order to describe the charge characteristics accurately in low-frequency analog applications [10]–[14]. With added par- todays devices. Mobility will influence the accuracy and distor- asitic components at the gate, at the source, at the drain, and at tion behavior of the model significantly [17], [22]. Based on the the substrate [9], [15], [16], these models can reasonably well charge and mobility models, complete – equations can be predict the HF ac small-signal characteristics of short channel developed with further inclusions of many important physical ( m) devices up to gigahertz range. However, the RF effects listed above. In order to meet the requirements for both MOSFET modeling is still at a preliminary stage compared with ac small-signal and large-signal applications, the continuity and the modeling work for digital and low-frequency analog appli- distortion behavior of the – model should be ensured in de- cations. Efforts from both industry and universities are needed riving the equations for these physical effects. to bring RF MOSFET models to a mature level in further im- In a real circuit operation, the device operates under time- proving the RF models in describing the ac characteristics more varying terminal voltages. Depending on the magnitude of the accurately, and in improving the prediction of noise character- time-varying signals, the dynamic operation can be classified as istics, distortion behavior, and NQS behavior. a large- or small-signal operation. Both types of dynamic opera- This paper reviews the efforts of MOSFET modeling for RF tion are influenced by the capacitive effects of the device. Many applications. Section II analyzes the ac small-signal modeling MOSFET intrinsic capacitance models have been developed. with emphasis in concepts and basic modeling approaches as Basically, they can be categorized into two groups: 1) Meyer well as the data deembedding and model parameter extrac- and Meyer-like capacitance models [26] and 2) charge-based tion. Section III presents the HF noise modeling with some capacitance models [4], [27], [28]. The Meyer and Meyer-like detailed analysis of channel noise, induced gate noise, and their modelsaresimplerthancharge-basedmodelssotheyareefficient correlation. Section IV addresses larger signal modeling with and faster in computations. Charge-based models ensure the the discussion of MOSFET distortion behavior and modeling charge conservation and consider the nonreciprocal property challenges. of the capacitances in a MOSEFT. These features are required to describe the capacitive effects in a MOSFET, especially for RF applications where the influence of transcapacitances are II. AC SMALL-SIGNAL MODELING critical and should be considered in the model. The development As shown in Fig. 1, a four-terminal MOSFET can be di- of an intrinsic capacitance model of modern MOSFETs is an- vided into two portions: intrinsic part and extrinsic part. The other challenging issue in RF modeling. To meet the needs in extrinsic part consists of all the parasitic components, such as RF applications, besides ensuring charge conservation and non- the gate resistance , gate/drain overlap capacitance , reciprocity, an intrinsic MOSFET capacitance model should at gate/bulk overlap capacitance , source series resistance least have the following features such as: 1) guaranteeing model , drain series resistance , source/bulk junction diode continuity and smoothness in all the bias regions; 2) providing , drain/bulk junction diode , and substrate resistances model accuracy for devices with different geometry and different , , and . The intrinsic part is the core of the bias conditions; and 3) ensuring model symmetry at the bias of device without including those parasitics. Even though it would V. be desirable to design and fabricate MOSFETs without those parasitics, they cannot be avoided in reality. Some of them may B. Modeling of the Extrinsic MOSFET not be noticeable in dc and low-frequency operation. However, As we discussed above, a MOSFET contains many extrinsic they will influence significantly the device performance at HF. components such as gate resistance, source/drain series resis- 1288 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY 2005 tance, substrate resistance and capacitance, and gate overlap capacitance. It has been well known that the gate resistance impacts impedance matching to achieve maximum power transfer and increases the noise figure of the transistor due to the thermal noise introduced by the gate resistance. Furthermore, the gate resistance also reduces (the frequency at which the maximum available power gain of the device equals to 1), which is an important device parameter in RF circuit design. The gate resistance is in principle a bias-independent component at dc and low frequency, but may contain the contribution of an additional component with bias dependence at HF due to two additional physical effects. One is the distributed transmis- Fig. 2. Equivalent gate resistance consists of the contributions from the sion line effect on the gate, and the other is the distributed effect distributed gate poly resistance and distributed channel resistance [39]. or the NQS effect in the channel [7], [15]. The distributed transmission line effect on the gate at HF has been studied [6]. It will become more severe as the gate width becomes wider at higher operation frequency. Therefore, multifinger devices are used in the circuit design with narrow gate width for each finger to reduce the influence of this effect. A simple expression of gate resistance , based on that in dc or low frequency, has been used to calculate the value of gate resistance with the influence of the distributed gate effect (DGE) at HF. However, a factor of is introduced, which is 1/3 or Fig. 3. Equivalent circuit of the substrate network [39]. 1/12 depending on the layout structures of the gate connection to account for the distributed RC effects at RF, as given in the following: It has been known that the source/drain resistances are bias dependent. However, a model without the bias dependence can work reasonably well in todays MOSFETs, because the (1) LDD region in these devices with advanced technologies (0.18 m and less) has a very high doping concentration, which where is the gate sheet resistance, is the channel width results in a weak bias dependence of and . Typically, per finger, is the channel length, and is the number of the source/drain resistances and without including any fingers, is the extension of the polysilicon gate over the bias dependence can be described by active region. Complex numerical models for the gate delay have been pro- (3) posed [29]. However, the simple gate resistance model with the factor for the distributed effect has been found accurate up to (4) 1 /2 for a MOSFET without significant NQS effects [10]. The NQS effect or the distributed RC effect in the channel is another effect that should be accounted for in modeling the HF where and are the parasitic drain and source resistances behavior of a MOSFET. For the devices with NQS effects, addi- with unit width, and account for the part of the series tional bias and geometry dependences of the gate resistance are resistances without the width dependence. needed to account for the NQS effect [7], [15]. It has been pro- The influence of the substrate resistance is usually ignored posed that an additional resistive component in the gate should in compact models for digital and analog circuit simulation be added to represent the channel distributed RC effect [7]. at low frequency. However, at high frequencies, the signal at As discussed above, when a MOSFET operates at high fre- the drain couples to the source and bulk terminals through the quencies, the contribution to the effective gate resistance is not source/drain junction capacitance and the substrate resistance. only from the physical gate electrode resistance but also from The substrate resistance influences mainly the output charac- the distributed channel resistance, which can be “seen” by the teristics, and can contribute as much as 20% or more of the signal applied to the gate, as shown in Fig. 2. Thus, the effective total output admittance [8], [10]. It has been known that the gate resistance consists of two parts substrate components become distributed at HF. Although it is always desirable to have a detailed distributed RC network (2) to account for the contribution of the substrate components, it is too complex to be implemented in a compact model. A where is the distributed gate electrode resistance from good compromise is still to use a lumped RC network, if it is the polysilicon gate material and is given by (17), is the accurate in the required operation frequency range, to simu- NQS distributed channel resistance seen from the gate and is a late the contribution of the substrate components. A simple function of both biases and geometry [7], [15]. equivalent circuit for the substrate network shown in Fig. 3 has CHENG et al.: MOSFET MODELING FOR RF IC DESIGN 1289

Fig. 4. Illustration of different capacitance components in a MOSFET (after [31]).

Fig. 5. Illustration of subcircuit model with intrinsic and extrinsic components been used to analyze the HF substrate-coupling effect and the (after [31]). characteristics of substrate resistance at HF [30]. Generally, assuming that the device is symmetric between to the existing models (either intrinsic or extrinsic capacitance source and drain and that it has no difference between the outer models) if they cannot meet the accuracy requirements at RF. and inner source/drain regions in a multifinger device, we have The substrate capacitance is an extrinsic capacitance that should be included in a subcircuit model for ultra HF (much (5) higher than 10 GHz) applications. C. Subcircuit RF Model where is the sheet resistance in the substrate between the With the consideration of parasitic resistances at the drain, at source and drain. the gate, at the source, and at the substrate, a complete subcircuit According to the layout, and should be functions of model for a MOSFET at HF can be given in Fig. 5. In the subcir- the channel width of the device. The following equations have cuit model, the characteristics of the intrinsic device is described been proven by the measurements for the devices with substrate by a MOS transistor compact model implemented in the circuit ties, in parallel to the gate, outside the source/drain regions (iso- simulator, and all the extrinsic components have to be located lated by shallow trench between the substrate ties and the active outside the intrinsic device, so that the MOS transistor symbol region): in the subcircuit only represents the intrinsic part of the device.2 For example: 1) the source and drain series resistors have been (6) added outside the MOS intrinsic device to make them visible in ac simulation; 2) the gate resistance is added to the subcir- (7) cuit model; 3) the substrate resistors are added to account for the signal coupling through the substrate; and 4) two external where and are the substrate resistances per diodes are added in order to account for the influence of the unit-channel width. substrate resistance at HF (the source-to-bulk and drain-to-bulk It has been found that the bias dependence of the substrate diodes are part of the compact model but their anodes are con- resistances is actually very weak for the devices with substrate nected to the same substrate node, which will short the ac signal ties isolated by shallow trench from the active region, and the at HF so the diodes internal to the compact model should be above simple substrate resistance network is accurate up to 10 turned off). Note that the intrinsic substrate node should be con- GHz [16], [30]. nected at some point along the resistor , but simulations As shown in Fig. 4, the parasitic capacitances in a MOSFET have shown that connecting the intrinsic substrate to the source can be divided into the following components: 1) the outer or the drain side has little influence on the simulated ac param- fringing capacitance between the polysilicon gate and the eters. In some RF models [8], [10], the intrinsic substrate has source/drain, ; 2) the inner fringing capacitance between been connected to the source side in order to save one node and the polysilicon gate and the source/drain, ; 3) the overlap one component for the subcircuit model. Two external overlap capacitances between the gate and the heavily doped S/D capacitances, and as shown in Fig. 5, with bias regions (and the bulk region) and ( ), dependence can be added, but this is not always required, de- which are relatively insensitive to terminal voltages; 4) the pending on the compact model used. overlap capacitances between the gate and lightly doped S/D An equivalent circuit to understand the components (both in- region and , which change with biases; 5) the trinsic and extrinsic) in the model is given in Fig. 6 [31], where source/drain junction capacitances and ; and 6) the , , and are the differences of the transcapacitances substrate capacitance, . Most of them have been included 2It may include the overlap capacitances at the source, at the drain and at the in models for digital/analog applications [17]. However, addi- bulk, depending on the intrinsic compact MOSFET model used in the imple- tional parasitic capacitance components may have to be added mentation. 1290 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY 2005

Fig. 7. Equivalent circuit used for two-step deembedding of measured HF data of MOSFETs (after [31]).

the carriers in the channel do not respond to the signal immedi- ately, and hence, the channel charge is not a unique function of the instantaneous terminal voltages (quasi static) but a function of the history of the voltages (non-quasi-static [NQS]) [32]. This problem may become pronounced in RF applications, where the Fig. 6. Equivalent circuit with both intrinsic and extrinsic components (after input signals may have rise or fall times comparable to, or even [31]). smaller than, the channel transit time. NQS effect should be included for an RF model to accurately describe the HF charac- between the drain and the gate, between the drain and the bulk, teristics of devices, if the devices themselves exhibit this effect and between the gate and the bulk, and given by at the operating frequency. The NQS effect can be modeled with different approaches for (8a) RF applications [33]. Ideally, the NQS effect should be included (8b) in the core intrinsic model if the model can predict both NQS and noise characteristics without a large penalty in the model (8c) implementation and simulation efficiency. NQS modeling is one of the interesting topics in RF modeling. However, it is not a where and are intrinsic trancapacitances between the focus here due to the length limitation of this paper. source and the drain, and between the bulk and the source and have the following relationships with other capacitances [31]: D. Parameter Extraction (9a) 1) RF Measurement and Deembedding Techniques: For a (9b) model to describe the device characteristics accurately, all important model parameters should be extracted from the mea- (10a) sured data. To extract the RF model parameters, on-chip HF (10b) measurements are performed by using specifically designed test (10c) structures. Also, a deembedding methodology has to be devel- (10d) oped to remove the influence of the parasitics in the test structure from the measured raw data in order to obtain the data for the (10e) characteristics of the device-under-test (DUT). where and are intrinsic and extrinsic capacitances Different deembedding techniques have been developed between the gate and the source, and are intrinsic based on different calibration test structures [34]–[36]. Here, and extrinsic capacitances between the gate and the drain, the deembedding procedure based on the above open and short and are intrinsic and extrinsic capacitances between the calibration test structures is discussed. gate and the bulk, and are intrinsic and junction ca- Typically, a DUT with parasitics from the test structures can pacitances between the bulk and the source, and and be represented by the equivalent circuit in Fig. 7 [31], where are intrinsic and junction capacitances between the bulk and the , , and represent the influence of the parallel para- drain [31]. sitics and , , and describe the influence of the series It should be noted that most MOSFET models available in parasitics. These parallel elements , , and can be ob- circuit simulators use the quasi-static (QS) approximation. In a tained from the measured data of the open structure, i.e., QS model, the channel charge is assumed to be a unique func- (11a) tion of the instantaneous biases, i.e., the charge responds to a change in voltages with infinite speed. Thus, the finite charging (11b) time of the carriers in the inversion layer is ignored. In reality, (11c) CHENG et al.: MOSFET MODELING FOR RF IC DESIGN 1291

Fig. 9. (a) Another example to show the importance of the deembedding of Fig. 8. (a) Illustration of the necessity of the deembedding of the real part the real part of measured (after [31]). (b) The ﬁgure shows a signiﬁcant of the measured data (after [31]). (b) Illustration of the necessity of the difference between the imaginary part of the measured before and after deembedding of the imaginary part of measured (after [31]). deembedding (after [31]).

The series elements , , and can be obtained from converting from according to the following the measured data of both open and short structures, i.e., equation: (12) (16) The measured data corresponding to the transistor can be obtained according to the following equation: Figs. 8 and 9 show the data of the measured and before and after one-step and two-step deembedding [31]. Sig- nificant difference between the data before and after one-step (13) deembedding has been observed. Thus, the data deembedding Thus, according to the above, the procedures of the two-step with the open calibration structure is absolutely necessary to ex- deembedding technique can be given as follows. tract accurate parameters of an RF model. A minor difference 1) Measure the -parameters ( , , and ) for between the data after the one-step and the two-step deembed- DUT, open and short test structures and convert them to ding indicate that the calibration with the short structure may be parameters ( , , and ); ignored for the MOSFETs at the frequency range in this mea- 2) Perform the first step deembedding by removing the par- surement. However, for the device to work at a much higher fre- allel parasitics from both and according to quency range, the importance of the calibration with the short the following equations: structure should be considered. Also, the short calibration may have to be used to obtain the measured data for other devices (14) such as inductors because the devices themselves are very sen- (15) sitive to the influence of the series parasitics. 2) Parameter Extraction: Depending on the equivalent cir- 3) Perform the second deembedding by removing the series cuit used in the model, methodologies of HF parameter extrac- parasitics , converting from , from , tion have been developed [31], [37]. Usually, the -parameter 1292 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY 2005 analysis of the equivalent circuit is adopted to obtain the nec- To extract the parameters for the substrate network, additional essary equations to extract the values of some resistive and ca- analysis for the parameter ( ) is needed. By pacitive components. It has been known that the poles due to performing a tedious but straightforward parameter analysis the terminal resistances (that usually are small because of the [30], we finally obtain the following equations: large finger numbers) are at a much higher frequency than typ- ical transit frequencies, so that they basically can be neglected Re Re (26a) when calculating the -parameters and the related quantities. The substrate resistances in the small-signal circuit is also ne- Im Im (26b) glected when analyzing the -parameters ( , , and where is the without the influence of , is the except the ) to obtain expressions that are suitable for use in output admittance of the substrate network [30], and parameter extraction. is the operation frequency. The parameters related to the dc characteristics are extracted The parameters of and can be obtained as discussed with the data from the dc measurements. The methodologies earlier. Thus, the data deembedded from the measured for the dc model parameter extraction have been well developed data according to the above equations represents the contribu- [17], [38]. By applying a gate bias high enough to operate the tion of the substrate network [39]. device in strong inversion regime, the intrinsic gate-to-bulk ca- To extract the substrate resistance and junction capacitances, pacitance is small enough and can be neglected. The equiv- we further derive the following equation by doing a -param- alent circuit for the parameter analysis is obtained [31]. eter analysis of the substrate network The following approximate equations for -parameters can be obtained:

(17a) (27) (17b) where , , and (17c) . These assumptions are valid in the frequency range up to 10 GHz [33]. Direct extraction of the ac parameters can be performed from Therefore, we have the measured data according to the above equations Im Im (28) (18) Re Im (29) (19) Im (20) The extracted includes the contribution of both the intrinsic capacitance and the drain junction capacitance (21) . The can be separated from the extracted with Re (22) the measured data at different because is a function Im Im of drain bias and is approximately independent of drain Re Re bias in the saturation regime. But, typically the capacitance (23) Im is dominated by . The value of capacitance at Re zero bias can be extracted from (28) with the measured data at (24) Im V. The parameters to describe the bias dependence of capacitance can be extracted according to (28) with the Depending on the measured data, which can be inﬂuenced by measured data at different . the design of the test structure, the calibration of the measure- Fig. 10 shows the extracted device parameters as a function ment system, the experience of the measurement person, and of frequency with the transistor at the given bias condition. It the accuracy of the deembedding procedures, the values of is shown that those components are frequency-independent in and extracted from the -parameter measurements may or the devices used for this study. In the devices with strong NQS may not equal the ones extracted from dc measurements. To en- effects, some device components become frequency dependent sure the dc characteristics predicted by the model parameters [40], and a more complex equivalent circuit should be used to extracted from dc measurements not to be disturbed by the pos- understand the device behavior. sible different and extracted from the measured -parameters, it is recommended that the values of and ex- III. NOISE MODELING tracted from dc measurements are used in extracting the ac parameters. In that case, the parameter can be extracted with Physics-based modeling of the high-frequency (HF) noise sources – channel noise, induced gate noise and their correlation the following equation: in MOSFETs has recently received much intention [41]–[49] Re because the MOSFET-based RF ICs are increasingly used in (25) Im electronic systems. In this section, different physics-based HF CHENG et al.: MOSFET MODELING FOR RF IC DESIGN 1293

Fig. 10. (a) Extracted values of , , and at given bias condition (after [31]). (b) Extracted values of g , g , and g at a given bias condition (after [31]). (c) Extracted values of substrate resistance at several different bias conditions [33]. noise models for these noise sources of interest in MOSFETs will be reviewed and discussed. In addition, the methods of implementing these noise sources based on compact MOSFET models for RF applications are presented.

A. Modeling of Channel Noise Due to the down scaling of the MOSFET dimension to deep submicron values and the increasing importance of the transistors noise, many publications on the high-frequency channel noise modeling for short-channel MOSFETs have appeared [41]–[49]. The channel noise is white (or frequency independent) and can be included in the equivalent circuit (as shown in Fig. 11) by adding a noise current source between the intrinsic drain and source terminals. The conventional channel noise model for long-channel transistors [32] based on the Fig. 11. Noise-equivalent circuit of a MOSFET including parasitic resistance ( , , and ), substrate network (h , h , , , and ), thermal noise theory (or Nyquist theory) and the dc character- enhanced channel noise (i ), and induced gate noise (i ) for RF IC istics of MOSFETs successfully predicted the channel noise of applications. short-channel devices operating in the linear region. However, for RF ICs, transistors operate in the saturation region for most MOSFETs. In this section, the channel noise models [41]–[49] applications. It is observed that the channel noise generated in will be brieﬂy reviewed. the short-channel transistors operating in the saturation region 1) Noise Current Calculation: The total noise current at the is higher than the predicted noise by the conventional channel drain terminal is obtained by integrating the noise contribution noise models [44], [45], [50]. Therefore, an explanation of from each section in the channel. There have been two different the noise enhancement in short-channel MOSFETs becomes calculation approaches presented in the literature to compute crucial for the channel noise modeling of deep-submicron the total noise spectral density at the drain terminal. The 1294 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY 2005

first approach is to obtain the noise spectral density con- tributed from each channel section at the drain terminal, and then integrate along the channel [41]–[47]. The second approach is to integrate each noise voltage density along the channel first and then multiply the total spectral density of the noise voltage by , where is the output conductance [48], [49]. The second approach is essentially not appropriate because for a nonlinear resistor like a MOSFET, a local noise fluctuation cannot be directly translated into a terminal fluctuation . Therefore, from the model derivation in [51] and [52], the channel noise current from each section in the channel should be calculated based on the first approach, i.e., (30) where and arethelocalconductanceandthenoise voltage fluctuation at the position , respectively. Based on the Nyquist theory and the dc characteristics of MOSFETs in the absence of velocity saturation, (30) can be simplified to [32] Fig. 12. Cross section of a MOSFET channel divided into a gradual channel (31) region (I) and a velocity saturation region (II). where is Boltzmann’s constant, is the lattice tempera- Therefore, the thermal noise theory cannot be applied in region ture ( ) at the position , is the local mobility (cm II [53]. ), is the electron concentration ( cm ) at the po- 3) Cause of Channel Noise Enhancement: Based on the sition , is the channel width, is the channel length of two-section channel model, there is finite inversion charge the transistor, and is the bandwidth. The term is in region II, and therefore region II is expected to contribute positive because of the negative charge for electrons in noise current to the total channel noise. Because of the failure n-channel MOSFETs. of the thermal noise theory in region II, it was proposed that 2) Modeling of a MOSFETs Channel: After reviewing the the diffusion noise becomes the main noise source [53], even calculation method of these proposed models, what is the phys- though the diffusion current is negligible in this region [54]. ical cause of the channel noise enhancement in short-channel The question is how to calculate the noise current based on the devices, and how to properly model the noise enhancement diffusion noise theory? According to the approach in [53], the are the two key issues to be solved in the proposed models noise current at the drain terminal from a section in region II is [41]–[47]. In general, these models can be divided into two calculated by multiplying the noise voltage obtained from the categories according to the model of the transistor’s channel. diffusion noise theory by its local conductance. However, based The first approach is based on a one-section channel model on (30), this approach should predict zero noise current because in which the channel (or the inversion charge) only exists in the carriers in region II travel at their saturation velocities and the gradual channel region which is from the intrinsic source the carriers will not respond to the local change of the electric terminal to the pinch-off point [41], [42]. The hot-electron field caused by the noise voltage fluctuation (i.e., ). effect in this region is proposed as the physical cause of the This does not mean that the noise voltage in region II will not noise enhancement, and it is included in the noise model by contribute noise current at the drain terminal. It might do so by treating the in (31) as the electron temperature. modulating the channel length and create a noise current The second approach [43]–[47] is to develop the noise model at the drain terminal. On the other hand, the noise current in based on a two-section channel model in which the channel of a region II might be calculated directly from the noise current MOSFET is divided into two regions – a gradual channel region of length (region I in Fig. 12) and a velocity predicted by the diffusion noise theory, but how to obtain the saturation region of length (region II in Fig. 12). When a diffusion constant of the carriers under the high dc electric transistor operates in the linear region, is the same as . field directly from measurements becomes the key issue in There are two physical reasons proposed to explain the noise en- this approach. Therefore, more investigation is required to hancement based on this two-section model – extra noise from characterize the noise contribution from this region. region II due to the hot-electron effect [43], [44] and the channel In addition to the extra noise contribution from region II, length modulation (CLM) effect in region I [45]–[47]. The noise the channel noise enhancement in short-channel MOSFETs can models presented in [43] and [44] are questionable because the be explained through the channel-length modulation (CLM) ef- equations used to calculate the noise contribution from the sec- fect [45]. From the derivation of (31) based on the two-section tions in region II is based on (31) which is only true in the ab- channel model, if we treat the part of the channel in the gradual sence of velocity saturation [32], and therefore cannot be ap- channel region as a single transistor with the channel length plied in region II. On the other hand, because the Ohm’slawis , then the local conductance will become not valid in the velocity saturation region, the local resistance used in the thermal noise equation [32], [52] is not defined. (32) CHENG et al.: MOSFET MODELING FOR RF IC DESIGN 1295

According to the channel noise derivation in [51] and [52], B. Induced Gate Noise and Its Correlation With the Channel the mean square value of the noise current delivered Noise to the drain terminal from a local resistance is given When transistors operate in the gigahertz range, the random by multiplied by the square of its local conductance potential fluctuations resulting in the channel noise will be cou- , and it becomes [45] pled to the gate terminal through the gate oxide capacitance. This noise coupling causes the induced gate noise which is usu- (33) ally correlated with the channel noise [52], [56]–[59]. Similar to the channel noise modeling, these proposed models can be characterized into two categories according to the channel model Because of the local conductance enhancement caused used: the one-section channel model [52], [56]–[58] or the two- by the CLM effect in short-channel MOSFETs, more noise cur- section channel model [59]. The model proposed in [59] as- rent power will be delivered to the drain terminal from sumes that there is induced gate noise generated in the velocity the same local noise power fluctuation which causes saturation region (region II). However, as discussed in the pre- the channel noise enhancement. Finally, the substrate resistance vious section, the proposed noise voltage [59] in region II will will also contribute some noise current to the drain terminal predict zero channel noise because of the zero local conduc- through the bulk transconductance [55]. tance, and therefore zero induced gate noise and zero corre- 4) Velocity Saturation Effect in Gradual Channel Re- lation noise because the induced gate noise is fully correlated gion: As discussed in [45], the derivation of (33) is based with the channel noise [52]. Again this does not mean that there on the assumption that the electric field in the longitudinal is no induced gate noise generated from region II, but alterna- direction for most of the sections in the gradual channel region tive approaches using proper physical mechanisms such as is much less than the critical field , i.e., the velocity modulation or diffusion noise current should be considered. An- saturation effect for sections in region I close to the boundary other mechanism which might generate the induced gate noise of regions I and II is ignored. As suggested in [41] and [52], is through the inversion charge variation caused by the substrate the velocity saturation effect should be included in the channel noise [55] via the bulk transconductance . In this paper, be- noise modeling, especially for short-channel devices. If the fore the channel noise in region II is fully characterized, the in- velocity saturation effect in region I is included by modeling duced gate noise and its correlation with the channel noise are the local mobility with the empirical relation [32], [52] only calculated within region I. Based on the induced gate noise in [52] without the velocity saturation effect and the hot-elec- (34) tron effect, and the channel noise from (33), the induced gate noise power ( ) and its correlation noise power with the channel noise ( ) from a section in region I can be ob- where is the local electric field at the position and tained by is the effective mobility depending on the vertical field only, then the dc drain current becomes

(35) (36) and where is the local channel resistance at the position . It is difﬁcult to derive an analytical expression for (37) from (35), but it can be observed quantitatively that where the local channel resistance is increased due to the velocity saturation effect (i.e., ), where (38) is the local resistance without the velocity saturation effect. This implies that a higher thermal noise voltage is generated (39) from the section at the position close to . However, as can be seen from (32), the local conductance (40) at position including the velocity saturation effect will be decreased because the local mobility is reduced (i.e., ). Therefore, the product and is the channel potential at the position referred is approximately equal to [45]. to the source. Equation (40) is obtained by assuming that the It has been shown that the maximum difference between these velocity saturation effect for the sections in region I close to two products is less than 5% [47]. This means that the impact the boundary of regions I and II can be ignored and the impact of the velocity saturation effect in region I on the channel noise of this assumption was discussed in the previous section. In modeling is not as pronounced as that on the modeling of dc cur- addition, becomes when transistors operate in satu- rent, and it can be considered as a secondary effect compared to ration. By integrating and the CLM effect in the channel noise modeling of short-channel over region I, the total spectral densities of the induced gate MOSFETs. noise and the correlation noise from the gradual 1296 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY 2005 channel region are then obtained by the integration of (36) and (37) from to divided by , and they are

(41) and Fig. 13. Noise reference circuits to generate noise currents for (a) the enhanced channel noise i and (b) the induced gate noise i shown in Fig. 11.

2) Induced Gate Noise: The induced gate noise can be naturally generated by using the segmentation method as presented in [46]. However, a disadvantage of this approach is that it increases the number of transistors and therefore the (42) simulation complexity, especially for the distortion analysis. In this paper, the induced gate noise shown in Fig. 11 is where . implemented by using a current controlled current source (CCCS). Because there is no induced gate noise generated in C. Noise Source Implementation the BSIM3v3 model and the induced gate noise is proportional Any physics-based noise model has to be implemented into to frequency square (as seen in (41)), the task is to find a the circuit simulators before they can be used by IC designers. reference circuit for whose spectral density is proportional This is usually done through the software vendor or model de- to frequency square without worrying about the contribution velopers. Assuming that the noise spectral densities of channel from the compact model. It is found that the reference circuit noise and induced gate noise are obtained from either shown in Fig. 13(b) can generate the noise spectral density with theoretical calculation based on any noise model mentioned in the desired frequency dependency by a proper selection of the previous sections or experimental results [44], [46], [61], this capacitance value and the resistance value as [64] section provides a simple method to implement the enhanced channel noise and the induced gate noise for RF IC applica- (45) tions by using a subcircuit approach. This approach is general and can work with any compact model (e.g., BSIM, MOS 11 or and EKV model) and circuit simulator (e.g., SpectreRF or ELDO). (46) In this paper, BSIM3v3 compact model is used to demonstrate the implementation method based on the noise equivalent circuit shown in Fig. 11. Because most of the circuit simulators where is the maximum frequency up to which the simula- cannot handle correlated noise sources, the correlation noise is tion will be valid, and represents the coefficient in the not implemented in this paper. versus frequency characteristics, i.e., 1) Enhanced Channel Thermal Noise: The enhanced channel thermal noise shown in Fig. 11 is implemented by (47) using a current controlled current source (CCCS), and its value is determined by the noise current generated by the reference resistance as shown in Fig. 13(a). With the noise flag D. Experimental Results and Discussions noiMod in BSIM3v3 noise model set to 4, the spectral density After reviewing the noise models from the theoretical view of the channel noise generated by the BSIM compact model is point, the possible candidates based on hot-electron effects [41], given by [63] [52] and CLM effects [45]–[47] will be verified experimen- tally. The DUTs are fabricated in a 0.18 m CMOS technology (43) with channel width m and channel lengths m, 0.42 m and 0.97 m, respectively. To compare where is Boltzmann’s constant, is the absolute tempera- the best fit from different noise models including the hot-elec- ture, is the effective mobility, is the effective channel tron effect, Fig. 14 shows the extracted (symbols) and simu- length and is the inversion channel charge. Therefore, the lated (lines) spectral densities of the channel noise versus proposed noise power source should only compensate the characteristics for the n-type MOSFETs biased at difference between and . So the value of is deter- V. The solid lines are obtained by using the noise model in mined by [64] [45], the inversion charge model in [63] and the channel length model in [60] without including the hot-electron effects. On the (44) other hand, the dotted–dashed lines are obtained using the noise model in [52] with the hot-electron effect factor , and CHENG et al.: MOSFET MODELING FOR RF IC DESIGN 1297

Fig. 15. Extracted (symbols) and simulated (lines) spectral densities of the induced gate noise versus characteristics for the n-type MOSFETs Fig. 14. Extracted (symbols) and simulated (lines) spectral densities of the aIH T " v aHXWU " with channel width m and channel lengths m, channel noise versus characteristics for the n-type MOSFETs with 0.42 "m, and 0.18 "m, respectively biased at aIXS V. channel width aIH T "m and channel lengths v aHXWU "m, 0.42 "m, and 0.18 "m, respectively biased at aIXS V. the dashed lines are obtained based on the noise model in [41] with the fitting parameter . It is shown that the proposed models in [41] and [52] including the hot-electron effect predict slightly different slopes in the versus characteristics compared to the measured data. For the induced gate noise and its correlation with the channel noise, Figs. 15 and 16 show the extracted (symbols) and simulated (lines) spectral densities of the induced gate noise and the correlation noise versus characteristics for the n-type MOSFETs biased at V. The solid lines are obtained by using (41) and (42) and the dashed lines are obtained based on the noise model in [52] with the velocity saturation effect. In addition, the dotted-dashed and the dashed lines are Fig. 16. Extracted (symbols) and simulated (lines) spectral densities of the calculated with ( ) and without ( ) the hot-electron correlation noise versus characteristics for the n-type MOSFETs effect, respectively. It is shown that the model with the velocity with channel width aIH T "m and channel lengths v aHXWU "m, saturation effect, (dashed lines) predicts lower and be- 0.42 "m, and 0.18 "m, respectively biased at aIXS V. cause of the neglect the enhancement of the local channel resistance as discussed in (35). In addition, the model including quency characteristics for transistors with two different channel the hot-electron effect can reasonably solve the discrepancy in lengths working in the linear region, where the BSIM3 channel , but it degrades the prediction of . This is because the noise model is accurate (as seen in Fig. 17(c) for the equivalent hot-electron term in [52] enhances the negative value caused by noise resistance ). Note that the NQS effect is implemented the term in (37) when is close to . This does in the BSIM3 model. All the parameter values are directly cal- not mean that the concept of hot-electron effect is proven phys- culated based on the BSIM3v3 model parameters without any ically incorrect, but the way of modeling this effect should be fitting parameters. From Fig. 17(a) and (b), it is shown that with reconsidered. On the other hand, as shown in Figs. 15 and 16, the proposed induced gate noise model given by (41) and the the CLM effect does not significantly affect and be- implementation method, the noise parameters can be accurately cause the net effect of the appears at the numerator of (41) predicted. and (42), not at the denominator as shown in (33) for the channel For most of the RF applications, transistors will work in the noise. Therefore, the noise model based on the CLM effect (e.g., saturation region. Fig. 18 shows the noise parameters in the sat- models in [45]–[47] for channel noise, (41) for the induced gate uration region. It can be seen from Fig. 18(a) and (b) that the noise and (42) for the correlation noise) can consistently predict induced gate noise also has a significant impact in the modeling the high-frequency noise performance of a MOSFET. of and of long channel transistors working in the After verifying the physics-based noise sources, they are im- saturation region. On the other hand, as shown in Fig. 18(c), the plemented into circuit simulators, and the next step is to verify enhanced channel noise due to the CLM effect can be accurately the implementation method. Because the induced gate noise is included in the simulation through the help of . pronounced in the long-channel transistors due to the higher For short-channel devices, Fig. 19 shows the versus gate capacitance, and it mainly affects the minimum noise figure frequency characteristics for a 0.18 m transistor working in ( ) and the magnitude of optimized source reflection co- the saturation region. All short-channel effects are taken care efficient ( ) [64], Fig. 17(a) and (b) shows the measured of by the BSIM3 model. The induced gate noise does not af- (symbols) and simulated (lines) and versus fre- fect the as much as it does in long-channel transistors. 1298 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY 2005

Fig. 17. (a) Measured (symbols) and simulated (lines) NF versus frequency characteristics for long-channel transistors working in the linear region. (b) Measured (symbols) and simulated (lines) j j versus frequency characteristics for long-channel transistors working in the linear region. (c) Measured (symbols) and simulated (lines) r versus frequency characteristics for long-channel transistors working in the linear region.

On the other hand, the CLM effect becomes the most important advantageous for the design of active RF applications. For most effect in the noise modeling of short-channel transistors. Note of the active blocks, such as LNAs, drivers, and active mixers, that if the channel width of the transistor is not wide enough, where a certain amount of amplification is always desired, the both measured and simulated will fluctuate as shown in transistors are selected under the condition that the operating Fig. 19, and then it becomes difficult to measure the noise pa- frequency is mostly below the LFL of the transistor. rameters of short-channel devices accurately. Another important behavior observed from measured data is the distortion behavior of MOSFETs in different operation regimes. As shown in Fig. 21, as the transistor operates in the IV. DISTORTION AND LARGE SIGNAL MODELING linear region, the distortion behavior changes dramatically with The capability of a HF device model to predict large-signal . However, as the device enters into saturation, it exhibits a and intermodulation distortion is very critical. A good RF fairly “constant” distortion behavior over , even for the de- model should predict well not only the ac small-signal and vice with a short . This characteristic simplifies the design for noise characteristics, but also large-signal distortion. It has large-signal application, such as power amplifierss and drivers, been studied that MOSFETs exhibit fairly constant distortion where a constant distortion behavior can be assumed for a tran- characteristics over frequencies, implying a relatively high sistor with very large-signal swing at the output, as long as the “low-frequency limit” (LFL), as show in Fig. 20 [18], [19]. transistor maintains its operation in the saturation regime. The LFL can be considered as a frequency below which the It has been reported that a model with good fittings in both distortion characteristics behave like those in low frequency. dc (both current and the derivatives) and ac (both capacitance This is a very useful characteristic of CMOS technology for and -parameters) characteristics can predict the distortion be- RF design, as its HF distortion behavior is mainly determined havior of a transistor up to a operating frequency at which the de- by the dc and low-frequency ac characteristics of the device. vice is still capable of delivering decent power gain, if physical Therefore, the MOSFET distortion behavior should be well and proper parameter extraction procedures are adopted [18], predicted by a model generated with an appropriate dc and ac [19]. Fig. 22 shows the comparison results between measured modeling procedure. The LFL decreases as the gate length of data and the subcircuit RF model [18], [19]. The model can ac- the MOSFET increases. The LFL behavior of MOSFETs is curately describe the fundamental, second and third harmonics CHENG et al.: MOSFET MODELING FOR RF IC DESIGN 1299

Fig. 18. (a) Measured (symbols) and simulated (lines) NF versus frequency characteristics for long-channel transistors working in the saturation region. (b) Measured (symbols) and simulated (lines) j j versus frequency characteristics for long-channel transistors working in the saturation region. (c) Measured (symbols) and simulated (lines) r versus frequency characteristics for long-channel transistors working in the linear region.

Fig. 19. Measured (symbols) and simulated (lines) xp versus frequency characteristics for a short-channel transistor working in the saturation region. over a wide range of bias conditions and frequencies. The model Fig. 20. Measured versus drain current s for a 10 12 "m 0.36 "m device (finger aIH, channel width per finger aIP"m, and channel length is generated with special care about parameter extraction based aHXQT "m) at four different frequencies (f aSHMHz, 100 MHz, 900 MHz, on dc and ac but no additional extraction effort against the data and 1.8 GHz, respectively) [19]. of distortion characterization [39]. The influence of some important device parameters such as has been studied [18], [19]. It has been known that the distor- oxide thickness and channel length to the distortion behavior tion behavior as a function of does not strongly depend on 1300 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY 2005

Fig. 21. Measured versus drain current s for the 10 12 0.36 device at several different drain biases when f aIXV GHz and a IS dfm; (a) drain-source voltage aHXS V, (b) aIV, (c) aIXS V, and (d) aPXS V [19].

distortion performance can be achieved by taking advantage of the third harmonic dip, i.e., the sweet spot, without considering the potential variation over and . It has also been found that the distortion behavior of a MOSFET strongly depends on the saturation velocity ( ) and the effective mobility ( ) [18], [19]. The change in saturation velocity significantly influences the distortion behavior even if is represented as a function of . Also the third harmonic dip, i.e., the sweet spot, moves along with the versus curve shift, which can be observed as indicated in the figure. Compared to the distortion simulation with variation, where a greater than change in is introduced, but only a little change is observed in the distortion simulation, the distortion sensitivity on is manifested even at low frequencies, i.e., 50 MHz. This is because the dc of a MOSFET depends nonlinearly on and its effect permeates to all the frequencies. The saturation velocity has effect only when the device operates in the saturation region, i.e., when the channel is pinched off near the drain region at high s, but the effective mobility has similar dominant effect on at all Fig. 22. Modeled (solid lines) and measured (symbols) s versus the drain current s for the 10 12 "m 0.36 "m device at different frequencies when operating regimes. The effect of the mobility to the distortion aHXS V and a IH dfm; (a) f aSHMHz, (b) f a IHH MHz, simulation at low ’s, where is changed so that the drain (c) f a WHH MHz, and (d) f aIXV GHz [19]. current is altered . Similar to that of , the effect of also moves the third harmonic dips along with the the effective gate length , even if the versus charac- versus shift as indicated in the figure. Although only low teristics is significant changed. Similar steadiness can also be simulation is shown here, the same level of influence of observed in the simulation with variation [18], [19]. This exhibits at also high , as it determines at all operating weak dependence of the distortion behavior on and is regimes. extremely useful for design of a MOSFET stage at high As one of the most important short-channel effects, the drain- frequencies, because the distortion behavior can be readily esti- induced barrier lowering (DIBL) alters the channel current drive mated with a model fitting well the dc characteristics. A superior through changing the effective threshold voltage. The sensitivity CHENG et al.: MOSFET MODELING FOR RF IC DESIGN 1301 of the distortion to DIBL increases as the drain voltage increases channel region seem to be negligible in the channel noise mod- [18], [19]. The DIBL effect on the distortion is most significant eling of deep submicron MOSFETs. The channel noise is fre- when the device operates at moderate region, i.e., when is quency independent and will increase when the channel length slightly higher than the . The DIBL effect to distortion de- is reduced. This can be caused by the CLM effect and the noise creases as increases. Moreover, when a MOSFET contribution for substrate resistance through . On the other is completely off, i.e., at , a MOSFET should be- hand, and are proportional to and , respectively, have very linearly as compared with that at any active opera- and they both decrease when the channel length is reduced be- tion. Therefore, the effect of DIBL to distortion appears only cause of the decrease of . From the simulated noise param- at a small window for the technology we present here. As eters with the noise sources implemented, it is found that the the channel length decreases, the sensitive window as a per- induced gate noise has strong impact on the noise performance centage of the total range allowed for reliability should be of long-channel devices, especially for and .On broadened. the other hand, for short-channel devices, the enhanced channel It should be noted that the above discussion is primarily on noise will play the dominant role in the prediction of their noise the HF distortion behavior of a MOSFET when used in an ac- performance. Further efforts are needed to model the induced tive operation, as in an amplifier. For MOSFETs employed in gate noise, the correlation with channel thermal noise and its hard-switching application, i.e., hard turn–on and turn-off, such influence to the circuits at RF. as in a passive mixer, the distortion behavior is different and spe- The distortion behavior of MOSFET is reviewed. The fact cific treatment is needed to use BSIM3v3 model for accurately that MOSFETs have much higher LFLs as compared with BJTs is useful for both RF IC design and modeling. An RF model with predicting the distortion behavior. The distortion behavior of a accurate dc and ac fitting can predict the distortion behavior of a MOSFET used as a switch is very important in RF circuit design device up to a very high frequency, enabling prediction of distor- and further efforts are needed to develop MOSFETs models for tion behavior with the given modeling methodology. A study of such applications. the sensitivity of device distortion behavior to physical effects is Also, as a broad-band 1-tone measurement provides the most discussed. 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Yuhua Cheng (M’96–SM’99) received the B.S. de- M. Jamal Deen (F’03) was born in Georgetown, gree from Shandong University, Jinan, China, the M. Guyana. He received the B.Sc. degree in physics S. degree from Tianjin University, Tianjin, China, and and mathematics from the University of Guyana, the Ph.D. degree from Tsinghua University, Beijing, Georgetown, and the M.S. and Ph.D. degrees in China, in 1982, 1985, and 1989, respectively, all in electrical engineering and applied physics from Case electrical engineering. Western Reserve University (CWRU), Cleveland, In 1990, he joined in the Institute of Microelec- OH, in 1978, 1982, and 1985, respectively. tronics (IME), Peking University, Beijing, as a Re- From 1978 to 1980, he was an Instructor of physics search Fellow. From 1992 to 1996, he was an As- at the University of Guyana, and from 1980 to 1983, sociate Professor in the IME and the Department of he was a Research Assistant at Case Western Reserve Computer Science and Technology, Peking Univer- University. He was a Research Engineer from 1983 to sity. From 1994 to 1995, he was a Visiting Professor at the University of Trond- 1985 and then an Assistant Professor from 1985 to 1986 at Lehigh University, heim, Norway, and a Research Fellow of the Norwegian Research Council. Bethlehem, PA. In 1986, he joined the School of Engineering Science, Simon From 1995 to 1997, he was a Research Associate at the Department of Electrical Fraser University, Vancouver, BC, Canada, as an Assistant Professor, and from Engineering and Computer Sciences, University of California, Berkeley, where 1993 to 2002, he was a Full Professor. In 1999, he assumed his current posi- he was working on the BSIM3 model development and providing technical sup- tion as Professor of electrical and computer engineering, McMaster University, port to the BSIM3 users from both industry and academics. He was the Project Hamilton, ON, Canada. In July 2001, he was awarded a Senior Canada Research Coordinator of the BSIM3v3 model development and was one of the principal Chair in Information Technology. He was a Visiting Scientist at the Herzberg contributors of the BSIM3v3 model that has been chosen as an industry stan- Institute of Astrophysics, National Research Council, Ottawa, ON, in summer dard model for IC simulation by the Electronics Industry Association/Compact 1986, and spent his sabbatical leave as a Visiting Scientist at Northern Telecom, Model Council. In 1997, he worked in Cadence Design Systems as a Member Ottawa, from 1992 to 1993. He was a Visiting Professor in the Faculty of Elec- of the Consultant Staff. From 1997 to 2004, he worked for Skyworks Solutions trical Engineering, Delft University of Technology, Delft, The Netherlands, in (formerly Conexant Systems), where he was a Senior Manager of the device the summer of 1997 and a CNRS Directeur de Recherche at the Physics of Semi- (bipolar, MOS and passive) modeling and technology service team responsible conductor Devices Laboratory, Grenoble, France, in the summer of 1998, and for mixed-signal/RF device modeling and CMOS/BICMOS technology evalu- at the Université de Montpellier, France from 2002 to 2003. He has edited two ation/support for various (ASIC, mixed-signal, RF) circuit designs. He is cur- research monographs and eight conference proceedings. He has written 14 in- rently the President and CTO of Siliconlinx, Inc., which offers products and vited book chapters, has been awarded six patents, has published more that 300 services to bridge the gap between IC designers and manufacturing foundries. peer-reviewed articles, and has given more than 60 invited/keynote/plenary con- His interests include CMOS/BICMOS technologies, high-speed bulk and sil- ference presentations. His current research interests include physics, modeling, icon-on-insulator (SOI) devices, BJT/MOS/passive device modeling, physical reliability, and parameter extraction of semiconductor devices, optical detec- veriﬁcation and parasitics extraction, and mixed-signal/RF IC design. He has tors and receivers, polymer and organic semiconductor devices, and low-power, authored and coauthored over 80 research papers, several book chapters, and low-noise, high-frequency circuits. He is Executive Editor of Fluctuations and the books MOSFET Modeling & BSIM3 User’s Guide (Norwell, MA: Kluwer, Noise Letters and a member of the editorial board of Interface, an Electrochem- 1999) and Device Modeling for Analog/RF Circuit Design (New York: Wiley, ical Society journal. 2003). Dr. Deen was awarded the 2002 Thomas D. Callinan Award from the Elec- Dr. Cheng has served on technical program committees in several interna- trochemical Society—Dielectric Science and Technology Division, and the Dis- tional conferences including the IEEE Custom Integrated Circuits Conference tinguished Researcher Award, Province of Ontario in July, 2001. He is a Dis- (CICC) and IEEE Radio Frequency Integrated Circuits Symposium. He serves tinguished Lecturer of the IEEE Electron Devices Society. He is currently an in the regions/chapter committees of IEEE Electron Devices Society (EDS) and Editor of the IEEE TRANSACTIONS ON ELECTRON DEVICES. He was elected a is the Vice-Chair of the North America West subcommittee for regions/chapters Fellow of Engineering Institute of Canada and a Fellow of The Electrochemical (SRC-NAW) of the EDS regions/chapters Committee. He is an EDS Distin- Society. He is a member of Eta Kappa Nu and the American Physical Society. guished Lecturer. He was a Fulbright-Laspau Scholar from 1980 to 1982, an American Vacuum Society Scholar from 1983 to 1984, and an NSERC Senior Industrial Fellow in 1993.

Chih-Hung Chen (S’95–M’03) received the B.S. degree in electrical engineering from the National Central University, Chungli, Taiwan, R.O.C., the M.S. degree in engineering science from Simon Fraser University, Burnaby, BC, Canada, and the Ph.D. degree in electrical and computer engineering, McMaster University, Hamilton, ON, Canada, in 1991, 1997, and 2002, respectively. For three consecutive summers from 1998, he was with Conexant Systems Inc., Newport Beach, CA, where he was involved in the high-frequency noise characterization and modeling of MOSFETs and BJTs. During the summer of 2001, he was with Transilica Inc. (now Microtune Inc.), San Diego, CA, where he was engaged in the design of differential LNAs and VCOs for Bluetooth. In 2002, he joined the Faculty of McMaster University, as an Assistant Pro- fessor of electrical and computer engineering, where his research interests are high-frequency noise characterization and modeling of MOSFETs and design of low-noise, RF CMOS integrated circuits for wireless applications. Dr. Chen was awarded the 2002 Dean’s Award of Excellence in Graduate Research at McMaster University and was the Co-Recipient of the Best In- vited Paper Award from the 2002 IEEE Custom Integrated Circuits Conference (CICC).