Memristor-Based Loop Filter Design for Phase Locked Loop

Journal of Low Power Electronics and Applications

Article Memristor-Based Loop Filter Design for Phase Locked Loop

Naheem Olakunle Adesina and Ashok Srivastava * Division of Electrical and Computer Engineering, Louisiana State University, Baton Rouge, LA 70803, USA * Correspondence: [email protected]; Tel.: +(225)-578-5022

Received: 30 May 2019; Accepted: 26 July 2019; Published: 29 July 2019

Abstract: The main challenge in designing a loop ﬁlter for a phase locked loop (PLL) is the physical dimensions of the passive elements used in the circuit that occupy large silicon area. In this paper, the basic features of a charge-controlled memristor are studied and the design procedures for various components of a PLL are examined. Following this, we propose a memristor-based ﬁlter design which has its resistance being replaced by a memristor in order to reduce the die area and achieve a low power consumption. We obtained a tuning range of 741–994 MHz, a stable output frequency of 1 GHz from the transfer characteristics of voltage-controlled oscillator (VCO), and an improved settling time. In addition to reduced power consumption and area occupied on the chip, our design shows a high reliability over wider range of temperature variations.

Keywords: ﬁlter; hysteresis curve; memristor; phase locked loop; voltage controlled oscillator

1. Introduction A phase locked loop (PLL) is a mixed-signal feedback system which consists of both analog and digital blocks including the loop filter. Though studies have shown that a voltage-controlled oscillator (VCO) is the most important component of a PLL, the loop filter is equally important because it removes remaining high frequency components in the output of the charge pump and thus stabilizes the control input to the VCO. It is highly notable that PLL applications, in the fields of communications, control systems and power electronics have evolved greatly in recent times. This complements the fact that although the PLL is an old technology, it has proven to be relevant in current trend devices and for future technological advancements. It is, however, desirable to improve the performance of the phase locked loop in terms of its power consumption, tuning range, reliability, lock time, phase noise etc. [1–3]. Apparently, a short frequency hop time would quickly bring the PLL back to normal oscillation when it is shifted to an undesirable frequency. The main goal of this paper was to propose a memristor based filter design for phase locked loop. A loop filter eliminates the high frequency components from the phase comparator so that only the direct current component is provided to the VCO. A memristor is considered a nanoscale device, so it is useful for more applications such as nonvolatile memory applications, low power and remote sensing applications, cross bar latches as transistor replacements, and analog computation and circuit applications [4]. Memristors’ ability to maintain a state without requiring external biasing can significantly reduce overall power consumption, while the deep-nanoscale physical dimensions of the device (minimum reported: 5 5 nm) are ideal for its implementation in the field of VLSI (very large-scale integration) [5] × and can thus provide a much-needed extension to Gordon Moore’s law. Emerging devices, such as memristors, when compared with established elements, tend to manifest advanced properties and often exhibit novel characteristics that can be exploited for enhancing the performance of conventional circuitry (e.g., a loop filter) as well as developing novel designs and applications. In the literature, many memristor-based analog applications have been presented since the announcement of the Helwett

J. Low Power Electron. Appl. 2019, 9, 24; doi:10.3390/jlpea9030024 www.mdpi.com/journal/jlpea J. Low Power Electron. Appl. 2019, 9, 24 2 of 13

Packard (HP) memristor. Though a memristor is not available yet as a discrete component, the simulation results and analytical models of memristor-based circuits obtained using memristor models available in literature can be used to explain how to design memristor-based ﬁlters [6].

2. Memristor A memristor is considered as a potential candidate for low power circuit design because it can use any value between 0 and 1, unlike conventional devices which use only 0 and 1. The word memristor is derivedJ. Low from Power twoElectron. words: Appl. 2019 MEMory, 9, x FOR PEER and REVIEW ResISTOR. It is a passive element similar to fundamental 2 of 14 devices like the resistor, inductor, and capacitor, in which these express the relations between voltage of the Helwett Packard (HP) memristor. Though a memristor is not available yet as a discrete and current,component, flux andthe simulation current, andresults voltage and analytical and charge, models respectively.of memristor-based A memristor, circuits obtained as a using component which wasmemristor first introduced models available by Leonin literature Chua can in be 1971 used [7 to], explain is also how considered to design memristor-based as the fourth fundamental filters passive[6]. device that expresses the relation between charge and flux [8,9]. Though a memristor could be charge or flux-controlled, we employed a charge-controlled Helwett Packard (HP) titanium oxide 2. Memristor (TiO2) memristor model in this work. A memristorA memristor is said is toconsidered be charge-controlled as a potential candidate if the relation for low between power circuit flux anddesign charge because is expressedit can as a factionuse of any the value charge, between a property 0 and referred1, unlike toconvention as memristanceal devices (M).which use only 0 and 1. The word memristor is derived from two words: MEMory and ResISTOR. It is a passive element similar to fundamental devices like the resistor, inductor, and capacitor,dΦ in which these express the relations between voltage and current, flux and current,M(q and) = voltage and charge, respectively. A memristor, as (1) dq a component which was first introduced by Leon Chua in 1971 [7], is also considered as the fourth where øfundamental and q are fluxpassive and device charge, that respectively. expresses the Memristancerelation between can charge also and be representedflux [8,9]. Though in relation a to memristor could be charge or flux-controlled, we employed a charge-controlled Helwett Packard other storage passive elements such as the inductor and capacitor. (HP) titanium oxide (TiO2) memristor model in this work. The voltageA memristor across is an said inductor to be charge-controlled and current flowing if the relation through between a capacitor flux and arecharge described is expressed as follows. as a faction of the charge, a property referred to as memristance (M). dΦ di 𝑀(𝑞V) (t=) = L (1) (2) l dq dt where ø and q are flux and charge, respectively. Memristance can also be represented in relation to other storage passive elements such as the inductor anddv capacitor. Ic(t) = C (3) The voltage across an inductor and current flowingdt through a capacitor are described as follows. 𝑑𝑖 By combining Equations (2) and (3), we𝑉 (𝑡 obtain.) = 𝐿 (2) 𝑑𝑡 𝑑𝑣 𝐼(𝑡) = V𝐶(t) L di (3) M(q) = l 𝑑𝑡 = (4) By combining Equations (2) and (3), we obtain.Ic(t ) C dv 𝑉(𝑡) 𝐿 𝑑𝑖 𝑀(𝑞) = = (4) From Equations (1) and (4), it is evident that𝐼(𝑡) the𝐶 memristor𝑑𝑣 is a charge-controlled device. In orderFrom to designEquations a memristor-based(1) and (4), it is evident loop that filter, the memristor understanding is a charge-controlled the behavior device. of a memristor is In order to design a memristor-based loop filter, understanding the behavior of a memristor is paramount. Figure1 shows equivalent circuit of a memristor for simulation in SPICE. We obtained paramount. Figure 1 shows equivalent circuit of a memristor for simulation in SPICE. We obtained SPICE simulatedSPICE simulated results results of some of some of theof the characteristics characteristics of a a memristor. memristor.

FigureFigure 1. SPICE 1 SPICE simulation simulation circuit circuit of of the the memristor. memristor.

Figures 2–5 show the simulation results of a memristor with a sinusoidal input, Vsource = Asin(wt), where A = 1.2 V and w = 2 π rad/s. However, the basic characteristics of a memristor are described in Figures 3–5.

J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 3 of 14

The HP memristor model parameters used are [10,11]: 𝑅 =11 kΩ, 𝑅 = 100 Ω, 𝑅 = -12 2 16 kΩ, D = 10nm, µv = (10 ) m /V-sec and 𝑝=10.The 𝑅 𝑎𝑛𝑑 𝑝parameters denote the initial resistance and exponent of window function, respectively. 𝑅 is the resistance of the doped memristor and 𝑅 is for the undoped memristor. D is the width of the thin film and µ is the dopant mobility.

J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 3 of 14

J. Low PowerThe Electron. HP memristor Appl. 2019, 9model, 24 parameters used are [10,11]: 𝑅 =11 kΩ, 𝑅 = 100 Ω, 𝑅 =3 of 13 -12 2 16 kΩ, D = 10nm, µv = (10 ) m /V-sec and 𝑝=10.The 𝑅 𝑎𝑛𝑑 𝑝parameters denote the initial resistance and exponent of window function, respectively. 𝑅 is the resistance of the doped memristorFigures2– and5 show 𝑅 the is simulationfor the undoped results memristor. of a memristor D is the with width a sinusoidal of the thin input, film V andsource µ= isAsin( the wt), wheredopant A = mobility.1.2 V and w = 2 π rad/s. However, the basic characteristics of a memristor are described in Figures3–5.

(a) (b)

Figure 2. Simulation output of the memristor model: (a) Voltage output of the memristor; (b) current output of the memristor.

Since input voltage and output current have the same zero crossing, as shown in Figure 2, this infers that the memristor is not a voltage storage device. The resistance versus time characteristics of the memristor are presented in Figure 3. The

instantaneous resistance is in the range [𝑅,𝑅 ], depending on the applied voltage. While a memristor can be used at its extreme resistance values in order to provide digital memory, it can also

be made to behave in an analog manner. The dynamic negative effect is due to the charge-dependent change in memristor resistance(a) [8]. Similarly, Figure 4 depicts (bresistance) versus voltage characteristics.FigureFigure 2. Simulation 2. Simulation The memristance output output of of the the value memristor memristor depends model: not (a ( a)only )Voltage Voltage on outputthe output magnitude of ofthe the memristor; memristor; but also (b on) current (b the) current sign of 𝑉(𝑡). 𝑅 ,𝑅 ] 𝑉(𝑡) <0 𝑅 ,𝑅 ] 𝑉(𝑡) > 0. outputoutput In of other theof the memristor. words, memristor. resistance [ for and [ for

instantaneous resistance is in the range [𝑅,𝑅 ], depending on the applied voltage. While a memristor can be used at its extreme resistance values in order to provide digital memory, it can also be made to behave in an analog manner. The dynamic negative effect is due to the charge-dependent change in memristor resistance [8]. Similarly, Figure 4 depicts resistance versus voltage characteristics. The memristance value depends not only on the magnitude but also on the sign of

𝑉(𝑡). In other words, resistance [𝑅,𝑅] for 𝑉(𝑡) <0 and [𝑅,𝑅] for 𝑉(𝑡) > 0.

J. Low Power Electron. Appl. 2019, 9, x FORFigure PEERFigure REVIEW 3. 3.Memristance Memristance waveform.waveform. 4 of 14

Figure 3. Memristance waveform.

FigureFigure 4. Resistance–voltage4. Resistance–voltage loop.loop.

Figure 5 shows the current–voltage characteristics of the memristor, where it exhibits a pinched hysteresis loop. The shape of the pinched hysteresis loop will change with frequency. We see in Figure 6 that the size of hysteresis loops decreases by increasing the frequency. This is due to the fact that the ions have a low mobility and slow inherent motions, and, as such, they finally lose their effectiveness on changing memristor resistance. In this way, the memristor reduces to a simple resistor.

Figure 5. Pinched hysteresis loop of the memristor.

J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 4 of 14

Figure 4. Resistance–voltage loop.

FigureFigure 5. 5.Pinched Pinched hysteresis hysteresis loop of of the the memristor. memristor.

The HP memristor model parameters used are [10,11]: Rinit = 11 kΩ, RON = 100 Ω, ROFF = 16 kΩ, -12 2 D = 10nm, µv = (10 ) m /V-sec and p = 10. The Rinit and p parameters denote the initial resistance and exponent of window function, respectively. RON is the resistance of the doped memristor and ROFF is for the undoped memristor. D is the width of the thin film and µv is the dopant mobility. Since input voltage and output current have the same zero crossing, as shown in Figure2, this infers that the memristor is not a voltage storage device. The resistance versus time characteristics of the memristor are presented in Figure3. The instantaneous resistance is in the range [RON, ROFF], depending on the applied voltage. While a memristor can be used at its extreme resistance values in order to provide digital memory, it can also be made to behave in an analog manner. The dynamic negative effect is due to the charge-dependent change in memristor resistance [8]. Similarly, Figure4 depicts resistance versus voltage characteristics. The memristance value depends not only on the magnitude but also on the sign of V(t). In other words, resistance [Rinit, ROFF] for V(t) < 0 and [RON, Rinit] for V(t) > 0. Figure5 shows the current–voltage characteristics of the memristor, where it exhibits a pinched hysteresis loop. The shape of the pinched hysteresis loop will change with frequency. We see in Figure6 that the size of hysteresis loops decreases by increasing the frequency. This is due to the fact that the ions have a low mobility and slow inherent motions, and, as such, they finally lose their J.e ffLowectiveness Power Electron. on changing Appl. 2019, memristor9, x FOR PEER resistance. REVIEW In this way, the memristor reduces to a simple resistor. 5 of 14

FigureFigure 6. 6. CurrentCurrent (I)–voltage (I)–voltage (V) (V) characteristics characteristics of of the the memristor memristor at at high high frequency. frequency.

3. PLL Building Blocks The architecture of the PLL is shown in Figure 7 In the following, we will describe the building blocks of the PLL.

Figure 7. Basic blocks of the phase locked loop (PLL).

3.1. Phase Detector A phase detector (PD) or phase comparator (PC) detects any phase difference between the off- chip (external) reference input and the clock generated by the frequency divider. A PD is therefore considered as a functional block having an output signal proportional to the phase difference between the two input signals [12]. Figure 8 shows the logic diagram of the phase detector.

J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 5 of 14

J. Low Power Electron. Appl. 2019, 9, 24 5 of 13 Figure 6. Current (I)–voltage (V) characteristics of the memristor at high frequency.

3. PLL Building Blocks The architecture of the PLL is shown in Figure7 7 In In thethe following,following, wewe willwill describedescribe thethe buildingbuilding blocks of the PLL.

Figure 7. Basic blocks of the phase locked loop (PLL). 3.1. Phase Detector 3.1. Phase Detector A phase detector (PD) or phase comparator (PC) detects any phase difference between the A phase detector (PD) or phase comparator (PC) detects any phase difference between the off- off-chip (external) reference input and the clock generated by the frequency divider. A PD is therefore chip (external) reference input and the clock generated by the frequency divider. A PD is therefore considered as a functional block having an output signal proportional to the phase difference between considered as a functional block having an output signal proportional to the phase difference theJ. Low two Power input Electron. signals Appl. [201912]., 9 Figure, x FOR8 PEER shows REVIEW the logic diagram of the phase detector. 6 of 14 between the two input signals [12]. Figure 8 shows the logic diagram of the phase detector.

Figure 8. Phase frequency detector. Figure 8. Phase frequency detector. The UP and DN signals in Figure8 function as control signals to the charge pump. In this work, the PLLThe architecture UP and DN and signals the phasein Figure frequency 8 function detector as co werentrol implementedsignals to the incharge a conventional pump. In Dthis flip-flop work, (DFF)the PLL based architecture topology. and The the DFF phase in Figure frequency8 was designed detector usingwere implemented D-latch because in ita providesconventional a very D high flip- speedflop (DFF) of operation, based topology considering [Reviewer’s the minimum 2 comment]. transistor The sizeDFF [in13 ],Figure for 0.5 8 umwas process designed technology using D-latch [14]. becauseWhen it provides the reference a very signal high isspeed leading of operation, or lagging considering the feedback the signal minimum from frequencytransistor size divider, [13], thefor di0.5ff erenceum process between technology the phases [14]. of two clock signals is represented by UP or DN pulses, respectively, as shownWhen in the Figure reference9. signal is leading or lagging the feedback signal from frequency divider, the difference between the phases of two clock signals is represented by UP or DN pulses, respectively, as shown in Figure 9.

(a)

J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 6 of 14

Figure 8. Phase frequency detector.

The UP and DN signals in Figure 8 function as control signals to the charge pump. In this work, the PLL architecture and the phase frequency detector were implemented in a conventional D flip- flop (DFF) based topology [Reviewer’s 2 comment]. The DFF in Figure 8 was designed using D-latch because it provides a very high speed of operation, considering the minimum transistor size [13], for 0.5 um process technology [14]. When the reference signal is leading or lagging the feedback signal from frequency divider, the difference between the phases of two clock signals is represented by UP or DN pulses, respectively, as shown in Figure 9. J. Low Power Electron. Appl. 2019, 9, 24 6 of 13

J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 7 of 14 (a)

(b)

Figure 9. SPICESPICE simulation simulation of of phase phase detector detector (PD) (PD) output output waveforms: waveforms: (a) (UPa)UP signal signal in Figure in Figure 8; (8b;) (DOWNb) DOWN signal signal in Figure in Figure 8. 8.

3.2. Charge PumpPump/Loop/Loop FilterFilter A chargecharge pump,pump, asas shown shown in in Figure Figure 10 10 below, below, translates translates the the digital digital UP UP and and DN DN voltages voltages from from the I phasethe phase detector detector into into a current a current signal, signal,cp [ 15𝐼], which [15], which is required is required to charge to charge or discharge or discharge the loop the filterloop in order to give the desired control voltage, V . In Figure 10, the loop resistance is replaced with filter in order to give the desired control voltage,ctrl 𝑉. In Figure 10, the loop resistance is replaced thewith memristor. the memristor. This isThis because is because the resistor the resistor in the loopin the filter loop introduces filter introduces a ripple a in ripple the control in the voltagecontrol ofvoltage the voltage-controlled of the voltage-controlled oscillator oscillator (VCO), even (VCO), when even the loopwhen is lockedthe loop [14 is,16 locked,17]. This [14,16,17]. undesirable This rippleundesirable may cause ripple a may modulation cause a ofmodulation the VCO outputof the VC frequencyO output and, frequency therefore, and, jitter therefore, in its output. jitter in We its showedoutput. earlierWe showed that the earlier memristor that the acts memristor like a linear acts resistor like a at linear high frequencies,resistor at high which frequencies, makes it suitable which formakes the it filter suitable circuit for in the our filter proposed circuit phasein our lockedproposed loop phase design. locked The loop memristor, design. owingThe memristor, to its nanoscale owing size,to its occupies nanoscale less size, die occupies area and less consumes die area less and power. consumes Therefore, less power. the existing Therefore, analog the loop existing filter analog circuit topologiesloop filter withcircuit characteristics topologies with that dependcharacteristics on resistance that depend can be madeon resistance with the can memristor be made [18 ,with19]. Thethe tolerancememristor of [18,19]. integrated The resistorstolerance due of tointegrated process andresistors temperature due to process variations and is temperature large, and this variations could lead is tolarge, performance and this could variations lead ofto frequencyperformance synthesizers variations using of frequency the integrated synthesizers RC loop using filter the consisting integrated of RC loop filter consisting of resistor (R) and capacitor (C) network [20]. Furthermore, it might degrade phase margin and even cause loop instability. Hence, the use of the memristor in place of the resistor is desirable.

Figure 10. Charge pump/loop filter.

J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 7 of 14

(b)

Figure 9. SPICE simulation of phase detector (PD) output waveforms: (a) UP signal in Figure 8; (b) DOWN signal in Figure 8.

3.2. Charge Pump/Loop Filter A charge pump, as shown in Figure 10 below, translates the digital UP and DN voltages from the phase detector into a current signal, 𝐼 [15], which is required to charge or discharge the loop filter in order to give the desired control voltage, 𝑉. In Figure 10, the loop resistance is replaced with the memristor. This is because the resistor in the loop filter introduces a ripple in the control voltage of the voltage-controlled oscillator (VCO), even when the loop is locked [14,16,17]. This undesirable ripple may cause a modulation of the VCO output frequency and, therefore, jitter in its output. We showed earlier that the memristor acts like a linear resistor at high frequencies, which makes it suitable for the filter circuit in our proposed phase locked loop design. The memristor, owing to its nanoscale size, occupies less die area and consumes less power. Therefore, the existing analog loop filter circuit topologies with characteristics that depend on resistance can be made with the memristorJ. Low Power Electron.[18,19]. Appl. The2019 tolerance, 9, 24 of integrated resistors due to process and temperature variations7 of is 13 large, and this could lead to performance variations of frequency synthesizers using the integrated RC loop filter consisting of resistor (R) and capacitor (C) network [20]. Furthermore, it might degrade phaseresistor margin (R) and and capacitor even cause (C) loop network instability. [20]. Furthermore, Hence, the use it mightof the memristor degrade phase in place margin of the and resistor even iscause desirable. loop instability. Hence, the use of the memristor in place of the resistor is desirable.

J. Low Power Electron. Appl. 2019, 9, x FOR FigurePEER REVIEW 10. Charge pump/loop ﬁlter. 8 of 14 Figure 10. Charge pump/loop filter. StudiesStudies have have also also shown shown that that the the loop loop ﬁlter filter resistor resistor variation variation is compensated is compensated by using by using an on-chip an on-

bandgapchip bandgap reference reference voltage voltage and another and another resistor resistor [21], which [21], which incurs incurs a prohibitively a prohibitively large costlarge for cost filter for design.filter design. In this In work, this wework, proposed we proposed a memristor-based a memristor-based loop filter loop whose filter memristance whose memristance is least a ffisected least byaffected process by parameter process parameter and temperature and temperature variations; variations; it also occupies it also smalloccupies die small area. die area. Similarly,Similarly, thethe widewide diversity diversity ofof memristor memristor characteristicscharacteristics withwith dependencydependency onon frequencyfrequency andand devicedevice sizesize makesmakes itit aa valuablevaluable circuitcircuit componentcomponent forfor variousvarious applications,applications, suchsuch asas thethe looploop filterfilter shownshown in in Figure Figure 10 10.. InIn addition,addition, memristormemristor technologytechnology ooffersffers lower lower heat heat generation, generation, as as it it utilizes utilizes less less energy.energy. AsAs aa newnew nanoscalenanoscale device,device, itit providesprovides aa lotlot ofof advantageousadvantageous featuresfeatures suchsuch asas high-density,high-density, non-volatility,non-volatility, low low power power and and good good scalability scalability [ 22[22].]. FromFrom Figure Figure 10 10,, the the digital digital values values 1 and 1 0and in the0 in transmission the transmission gates represent gates represent UP/DN andUP/DN inverted and signals,inverted respectively. signals, respectively. The loop filterThe loop is equally filter is highlighted equally highlighted in Figure in10 Figure. It integrates 10. It integrates the error the current error

tocurrent generate to controlgenerate voltage control for voltage the VCO. for Inthe the VCO. loop In ﬁlter, the Cloop1 is addedfilter, in𝐶 parallelis added to in series parallel combination to series ofcombination the memristor, of the M, memristor, and capacitor M, andC2 tocapacitor reduce cycle𝐶 to to reduce cycle cycle jitter atto thecycle output jitter at [23 the,24 output]. The output[23,24]. waveformThe output of waveform charge pump of charge/loop ﬁlter pump/loop (CP/LF) filter is shown (CP/LF) in Figure is shown 11. in Figure 11.

FigureFigure 11.11. OutputOutput waveformwaveform ofof chargecharge pumppump/loop/loop ﬁlter filter (CP (CP/LF)./LF).

Whenever the UP signal is high, it forces the current into the loop filter. Hence, the VCO control voltage rises, as shown in the figure. As shown in Figure 11, we obtained a settling time of 67.89 nS, which is considered shorter than the conventional design using a constant RC loop filter [25]. Additionally, PLLs designed based on the proposed method exhibit less ripple in the VCO control voltage and therefore less jitter in the output.

3.3. Voltage Controlled Oscillator The voltage-controlled oscillator (VCO) is the most important and complex component of the overall PLL design. In this work, we used single-ended current starved VCO, as shown in Figure 12 [26,27]. The simulation result of the output waveform is shown in Figure 13. Figure 14 shows the plot of transfer characteristics of the VCO. It shows that the VCO is a linear

system because the frequency of oscillator varies linearly with the control voltage, 𝑉 This is consistent with the existing PLL design [26,27]. Additionally, it is desirable for the voltage (V) – frequency (F) characteristic to have a positive slope, as shown in Figure 14. This means that the maximum operating frequency is achieved at maximum control voltage [28]. The tuning range of the VCO is 741–994 MHz. The result shows that the VCO in our design has a wider tuning range when compared and validated with the work described in [26].

The measurement of the VCO tuning sensitivity (𝐾) was calculated from the simulation results in Table 1 using Equation (5) and is summarized in Table 2.

J. Low Power Electron. Appl. 2019, 9, 24 8 of 13

Whenever the UP signal is high, it forces the current into the loop filter. Hence, the VCO control voltage rises, as shown in the figure. As shown in Figure 11, we obtained a settling time of 67.89 nS, which is considered shorter than the conventional design using a constant RC loop filter [25]. Additionally, PLLs designed based on the proposed method exhibit less ripple in the VCO control voltage and therefore less jitter in the output.

3.3.J. Low Voltage Power Electron. Controlled Appl. Oscillator2019, 9, x FOR PEER REVIEW 9 of 14 The voltage-controlled oscillator (VCO) is the most important and complex component of the overall PLL design. In this work, we used single-ended current starved VCO, as shown in J.Figure Low Power 12[ Electron.26,27]. Appl. The simulation2019, 9, x FORresult PEER REVIEW of the output waveform is shown in Figure 13. 9 of 14

Figure 12. The single-ended current starved voltage-controlled oscillator (VCO).

Substrates of P-channel MOS and N-channel MOS transistors are connected to supply voltage,

𝑉 and the ground, respectively. Figure 12. The single-ended current starved voltage-controlled oscillator (VCO). Figure 12. The single-ended current starved voltage-controlled oscillator (VCO).

Substrates of P-channel MOS and N-channel MOS transistors are connected to supply voltage,

𝑉 and the ground, respectively.

FigureFigure 13.13. SPICESPICE simulationsimulation outputoutput ofof aa single-endedsingle-ended currentcurrent starvedstarved VCO.VCO.

FigureTable 114 shows shows the the variations plot of transfer in frequency characteristics of the VCO of the as VCO.the control It shows voltage that theincreases. VCO is a linear system because the frequency of oscillator varies linearly with the control voltage, Vctrl This is consistent with the existingFigure PLL design13. SPICE [26 Tablesimulation,27]. 1. Additionally, Voltage/frequency output of a itsi isngle-ended desirablecaptured current data. for the starved voltage VCO. (V) – frequency (F) Control Voltage (V) VCO Frequency (GHz) Table 1 shows the variations in frequency4.450 of the VCO 0.741 as the control voltage increases. 4.726 0.846 4.876 0.926 Table 1. 4.955Voltage/frequency captured 0.971 data. 4.992 1.010 Control Voltage (V) VCO Frequency (GHz) 4.450 0.741 4.726 0.846 4.876 0.926 4.955 0.971 4.992 1.010

J. Low Power Electron. Appl. 2019, 9, 24 9 of 13 characteristic to have a positive slope, as shown in Figure 14. This means that the maximum operating frequency is achieved at maximum control voltage [28]. The tuning range of the VCO is 741–994 MHz. The result shows that the VCO in our design has a wider tuning range when compared and validated withJ. Low thePower work Electron. described Appl. 2019 in, 9 [,26 x FOR]. PEER REVIEW 10 of 14

FigureFigure 14.14. VCOVCO transfertransfer characteristics.characteristics.

The measurement of the VCOTable tuning 2. Tuning sensitivity sensitivity (KVCO calculated) was calculated data. from the simulation results in Table1 using Equation (5) and is summarized in Table2. Control Voltage (V) KVCO (GHz/V) 4.450 0.594 Table 1. Voltage4.726/ frequency captured 0.550 data. 4.876 0.592 Control Voltage (V)4.955 VCO 0.908 Frequency (GHz) 4.992 1.022 4.450 0.741

4.726 0.846 𝛥F 𝐾 = (5) 4.876 𝛥V 0.926 where F and V denote the VCO frequenc4.955y and control voltage, 0.971 respectively. Figure 15 shows a sensitivity4.992 plot of the voltage-controlled 1.010 oscillator. The gain of the VCO falls as control voltage increases. However, the gain increases linearly with the control voltage as we approach the tuning frequencies.Table 2. Tuning sensitivity calculated data.

Control Voltage (V) KVCO (GHz/V) 4.450 0.594 4.726 0.550 4.876 0.592 4.955 0.908 4.992 1.022

Substrates of P-channel MOS and N-channel MOS transistors are connected to supply voltage, VDD and the ground, respectively. Table1 shows the variations in frequency of the VCO as the control voltage increases.

∆F K = (5) VCO ∆V where F and V denote the VCO frequency and control voltage, respectively. Figure 15. VCO tuning sensitivity curve.

Since the objective of the field of electronics or VLSI design is ultimately to ensure that electronics are reliable, it is worth thinking about the relationship between temperature and reliability. Thermal analysis is important in ensuring the accuracy of timing, noise, and reliability analyses during chip design [29]. In commercial, industrial and military applications, the general temperature specifications of most integrated circuits ranges from −55 °C to 125 °C. This is because the majority of

J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 10 of 14

Figure 14. VCO transfer characteristics.

Table 2. Tuning sensitivity calculated data.

Control Voltage (V) KVCO (GHz/V) 4.450 0.594 4.726 0.550 4.876 0.592 4.955 0.908 4.992 1.022

𝛥F J. Low Power Electron. Appl. 2019, 9, 24 𝐾 = 10(5) of 13 𝛥V where F and V denote the VCO frequency and control voltage, respectively. Figure 15 shows aa sensitivitysensitivity plotplot ofof the the voltage-controlled voltage-controlled oscillator. oscillator. The The gain gain of of the the VCO VCO falls falls as ascontrol control voltage voltage increases. increases. However, However, the gain the increasesgain increases linearly linearly with the with control the voltagecontrol asvoltage we approach as we approachthe tuning the frequencies. tuning frequencies.

Figure 15. VCO tuning sensitivity curve. Figure 15. VCO tuning sensitivity curve. Since the objective of the field of electronics or VLSI design is ultimately to ensure that electronics Since the objective of the field of electronics or VLSI design is ultimately to ensure that electronics are reliable, it is worth thinking about the relationship between temperature and reliability. Thermal are reliable, it is worth thinking about the relationship between temperature and reliability. Thermal analysis is important in ensuring the accuracy of timing, noise, and reliability analyses during chip analysis is important in ensuring the accuracy of timing, noise, and reliability analyses during chip design [29]. In commercial, industrial and military applications, the general temperature specifications designJ. Low Power[29]. Electron. In commercial, Appl. 2019, 9, x FORindustrial PEER REVIEW and military applications, the general temperature 11 of 14 of most integrated circuits ranges from 55 ◦C to 125 ◦C. This is because the majority of integrated specifications of most integrated circuits −ranges from −55 °C to 125 °C. This is because the majority of circuitintegrated failure circuit mechanisms failure occur mechanisms at these temperatures occur at th [ese30]. temperatures The loop filter [30]. resistor Th contributese loop filter to phaseresistor noise,contributes which canto phase affect thenoise, performance which can ofaffect the PLL.the pe Sincerformance the control of the voltage, PLL. SinceVctrl, the is fixed control over voltage, wide range of temperatures, the simulation result in Figure 16 shows that our design is less temperature 𝑉, is fixed over wide range of temperatures, the simulation result in Figure 16 shows that our dependentdesign is less and temperature thus highly reliable.dependent and thus highly reliable.

FigureFigure 16. 16.Simulation Simulation result result of of thermal thermal analyses. analyses.

3.4. Frequency Divider 3.4. Frequency Divider A divider circuit divides the frequency of the VCO clock to generate a feedback clock for a phase A divider circuit divides the frequency of the VCO clock to generate a feedback clock for a phase comparison with reference input [24]. In this work, we employed a fractional N-divider D ﬂip-ﬂop comparison with reference input [24]. In this work, we employed a fractional N-divider D flip-flop circuitry,circuitry, which which divides divides the VCOthe VCO clock clock by the by highest the hi powerghest ofpower two factorof two to synchronizefactor to synchronize the reference the clockreference signal clock and thesignal divider and outputthe divider clock. output clock. The stable output frequency of the VCO is given as: 𝑓 =𝑁∗𝑓 (6) where N is the mod counter.

4. Results and Discussion Our proposed memristor-based loop filter PLL has a tuning range of 741–994 MHz. Figures 14 and 16 show that the target is achieved where there is a phase match between the PLL reference input,

𝑉, and feedback input from divider circuitry, 𝑉 as shown in Figure 17.

(a)

J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 11 of 14 integrated circuit failure mechanisms occur at these temperatures [30]. The loop filter resistor contributes to phase noise, which can affect the performance of the PLL. Since the control voltage,

𝑉, is fixed over wide range of temperatures, the simulation result in Figure 16 shows that our design is less temperature dependent and thus highly reliable.

Figure 16. Simulation result of thermal analyses.

3.4. Frequency Divider A divider circuit divides the frequency of the VCO clock to generate a feedback clock for a phase J.comparison Low Power Electron. with Appl.reference2019, 9 ,input 24 [24]. In this work, we employed a fractional N-divider D flip-flop11 of 13 circuitry, which divides the VCO clock by the highest power of two factor to synchronize the reference clock signal and the divider output clock. The stable output frequency of the VCO is given as: The stable output frequency of the VCO is given as: 𝑓 =𝑁∗𝑓 (6) fout = N fre f (6) where N is the mod counter. ∗ where N is the mod counter. 4. Results and Discussion 4. Results and Discussion Our proposed memristor-based loop filter PLL has a tuning range of 741–994 MHz. Figures 14 and 16Our show proposed that the memristor-based target is achieved loop where ﬁlter there PLL is hasa phase a tuning match range between of 741–994 the PLL MHz. reference Figures input, 14 and 16 show that the target is achieved where there is a phase match between the PLL reference input, 𝑉, and feedback input from divider circuitry, 𝑉 as shown in Figure 17. Vb, and feedback input from divider circuitry, Vdiv as shown in Figure 17.

J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 12 of 14 (a)

(b)

FigureFigure 17.17. SPICESPICE simulation:simulation: (a)) ReferenceReference input;input; ((bb)) feedbackfeedback input.input.

WeWe alsoalso computedcomputed thethe averageaverage powerpower andand energyenergy consumptionconsumption ofof thethe memristor,memristor, asas shownshown inin FigureFigure 1818.. TheThe valuesvalues obtainedobtained satisfysatisfy thethe conditionsconditions ofof anan energyenergy eefficientﬃcient devicedevice [[31].31]. ThoughThough wewe employedemployed thethe memristormemristor onlyonly inin thethe looploop ﬁlter,filter, thethe memristormemristor isis alsoalso compatiblecompatible withwith CMOSCMOS crossbarcrossbar architecture,architecture, soso itit cancan bebe integratedintegrated intointo otherother componentscomponents ofof thethe PLLPLL inin the the future future work. work.

Figure 18. Power consumption of the memristor.

From Figure 18, the average power consumed by the memristor is 8.65 nW, as compared to 8.637 µW, which is the total estimated power consumed by the proposed loop filter. The power consumption of the memristor device is very small, so its impact on the total power consumption in the phase locked loop design is negligible.

5. Conclusions The advantages of combining memristors and CMOS transistors for the design of a phase locked loop are highlighted in this paper. The use of a nanoscale size memristive device in loop filter design is explored to reduce power consumption and save area. The proposed PLL achieves a tuning range from 741 MHz to 994 MHz with less variations with temperature. As a future work, the fabricated area of the proposed loop filter can be effectively reduced further by replacing the conventional capacitances with nanoscale memcapacitance circuits [Reviewer’2 comments].

Author Contributions: Research problem was suggested to Naheem O. Adesina (PhD student and first author) by Prof. Ashok Srivastava. Naheem O. Adesina worked on the suggested research problem under the supervision of Prof. Srivastava, prepared first working draft of the work in JLPEA format. Extensive corrections

J. Low Power Electron. Appl. 2019, 9, x FOR PEER REVIEW 12 of 14

(b)

Figure 17. SPICE simulation: (a) Reference input; (b) feedback input.

We also computed the average power and energy consumption of the memristor, as shown in Figure 18. The values obtained satisfy the conditions of an energy efficient device [31]. Though we employed the memristor only in the loop filter, the memristor is also compatible with CMOS crossbar J. Low Power Electron. Appl. 2019, 9, 24 12 of 13 architecture, so it can be integrated into other components of the PLL in the future work.

Figure 18. Power consumption of the memristor. Figure 18. Power consumption of the memristor. From Figure 18, the average power consumed by the memristor is 8.65 nW, as compared to From Figure 18, the average power consumed by the memristor is 8.65 nW, as compared to 8.637 8.637 µW, which is the total estimated power consumed by the proposed loop filter. The power µW, which is the total estimated power consumed by the proposed loop filter. The power consumption of the memristor device is very small, so its impact on the total power consumption in consumption of the memristor device is very small, so its impact on the total power consumption in the phase locked loop design is negligible. the phase locked loop design is negligible. 5. Conclusions 5. Conclusions The advantages of combining memristors and CMOS transistors for the design of a phase locked loop areThe highlighted advantages in of this combining paper. The memristors use of a nanoscale and CMOS size transistors memristive for devicethe design in loop of a filter phase design locked is exploredloop are highlighted to reduce power in this consumption paper. The anduse of save a nano area.scale The size proposed memristive PLL achieves device ain tuning loop filter range design from 741is explored MHz to to 994 reduce MHz power with less cons variationsumption withand save temperature. area. The As proposed a future PLL work, achieves the fabricated a tuning area range of thefrom proposed 741 MHz loop to 994 filter MHz can bewith eff ectivelyless variations reduced with further temperature. by replacing As thea future conventional work, the capacitances fabricated witharea nanoscaleof the proposed memcapacitance loop filter circuits. can be effectively reduced further by replacing the conventional capacitances with nanoscale memcapacitance circuits [Reviewer’2 comments]. Author Contributions: Research problem was suggested to N.O.A. (PhD student and first author) by A.S. N.O.A. workedAuthor onContributions: the suggested Research research problem underwas suggested the supervision to Naheem of S.A., O. preparedAdesina (PhD first working student draftand first of the author) work in JLPEA format. Extensive corrections and revisions were made by S.A. including at the final correction of proof. by Prof. Ashok Srivastava. Naheem O. Adesina worked on the suggested research problem under the Both authors contributed equally. supervision of Prof. Srivastava, prepared first working draft of the work in JLPEA format. Extensive corrections Funding: This research received no external funding.

Conﬂicts of Interest: The authors declare no conﬂict of interest.

References

1. Boulghassoul, Y.; Massengill, L.W.; Sternberg, A.L.; Bhuva, B.L. Eﬀects of technology scaling on the set sensitivity of RF CMOS voltage-controlled oscillators. IEEE Trans. Nucl. Sci. 2005, 52, 2246–2432. [CrossRef] 2. Nicholas, H.T.; Samueli, H. A 150-MHz direct digital frequency synthesizer in 1.25-µm CMOS with-90-dBc spurious performance. IEEE J. Solid State Circuits 1991, 26, 1959–1969. [CrossRef] 3. Loveless, T.D.; Massengill, L.W.; Bhuva, B.L.; Holman, W.T.; Witulsk, A.F.; Boulghassoul, Y. A hardened-by-design technique for RF digital phase-locked loop. IEEE Trans. Nucl. Sci. 2006, 52, 3432–3438. [CrossRef]

4. Kyriakides, E.; Carrara, S.; De Micheli, G.; Georgiou, J. Low-cost, CMOS compatible, Ta2O5-based hemi-memristor for neuromorphic circuits. Electron. Lett. 2012, 48, 1451–1452. [CrossRef] 5. Prodromakis, T.; Toumazou, C. A review on memristor devices and applications. In Proceedings of the 17th IEEE Internal Conference on Electronics, Circuits, and Systems (ICECS), Athens, Greece, 12–15 December 2010; pp. 400–408. 6. Sahin, M.E.; Guler, H. The design of memristor based high pass ﬁlter circuit. In Proceedings of the IEEE International Conference in Electronics, Circuits and Systems, Batumi, Georgia, 5–8 December 2017; pp. 494–497. 7. Chua, L.O. Memristor–the missing circuit element. IEEE Trans. Circuit Theory 1971, 18, 507–519. [CrossRef] J. Low Power Electron. Appl. 2019, 9, 24 13 of 13

8. Strukov, D.B.; Snider, G.S.; Steward, D.R.; Williams, R.S. The Missing Memristor Found. Nature 2008, 453, 80–83. [CrossRef][PubMed] 9. Zhu, G.; Singh, C. Improving students’ understanding research-based learning tools. Phys. Rev. Spec. Top. Phys. Educ. Res. 2012, 8, 1–8. 10. Chua, L.O.; Kang, S.M. Memristive devices and systems. Proc. IEEE 1976, 64, 209–223. [CrossRef] 11. Massmilliano, D.V.; Yurry, V.P.; Chua, L.O. Circuit Elements with Memory: Memristors, Memcapacitors, and Memductors. Proc. IEEE 2009, 97, 1–6. 12. Barale, F. Frequency Dividers Design for Multi-GHz PLL Systems. Master’s Thesis, Georgia Institute of Technology, Atlanta, GA, USA, 2008. 13. Razavi, B. Design of Analog CMOS Integrated Circuits; McGraw Hill: Boston, MA, USA, 2001. 14. Razavi, B. Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design; John Wiley & Sons Inc.: Hoboken, NJ, USA, 1996. 15. Rajwardan, A. Design and Simulation of a Charge-Pump Phase-Locked Loop in 65 nm CMOS Technology. Master’s Thesis, University of Illinois, Urbana-Champaign, IL, USA, 2016. 16. Gardner, F.M. Charge-pump phase-lock loops. IEEE Trans. Commun. 1980, 3, 1849–1858. [CrossRef] 17. Johns, D.A.; Martin, K. Analog Integrated Circuit Design; John Wiley & Sons: New York, NY, USA, 1997. 18. Sangho, S.; Kyungmin, K.; Sung-Mo, K.S. Memristor applications for programmable analog ICs. IEEE Trans. Nanotechnol. 2011, 10, 266–274. [CrossRef] 19. Ascoli, A. Memristor-based filtering applications. In Proceedings of the 14th Latin American Test Workshop, Cordoba, Argentina, 3–5 April 2013; pp. 1–6. 20. Zhang, B.; Allen, P.E.; Huard, J.M. A fast switching PLL frequency synthesizer with an on-chip passive discrete-time loop filter in 0.25-µm CMOS. IEEE J. Solid State Circuits 2003, 38, 855–865. [CrossRef] 21. Wu, T.; Hanumolu, P.K.; Mayaram, K.; Moon, U. Method for a constant loop bandwidth in LC-VCO PLL frequency synthesizers. IEEE J. Solid State Circuits 2009, 44, 427–435. [CrossRef] 22. Junsangsri, P.; Lombardi, F. Design of a hybrid memory cell using memristance and ambipolarity. IEEE Trans. Nanotechnol. 2013, 62, 1402–1411. [CrossRef] 23. Djahanshahi, H.; Andre, C.; Salama, T. Differential CMOS circuits for 622–MHz/933–MHz Clock and Data Recovery Applications. IEEE J. Solid State Circuits 2000, 35, 847–855. [CrossRef] 24. Ratan, R. Design of a Phase Locked Loop Based Clocking Circuit for High Speed Serial Link Applications. Master’s Thesis, University of Illinois, Champaign, IL, USA, 2014. 25. Zhao, Y.-C.; Guo, Y.-C.; Tse, C.-K.; Feng, J.-C. Application of memristor-based controller for loop filter design in charge-pump phase-locked loop. Circuits Syst Signal Process. 2013, 32, 1013–1023. [CrossRef] 26. Liu, Y. Phase Noise in CMOS Phase Locked Loop Circuits. Ph.D. Thesis, Louisiana State University, Baton Rouge, LA, USA, 2011. 27. Minhad, K.N.; Kazemi, Z.; IbneReaz, M.B.; Jalil, J.; Kamal, N. Design of a current starved ring oscillator based VCO for phase- locked loop. Indones. J. Electr. Eng. 2014, 12, 1–3. 28. Young, I.A.; Greason, J.K.; Wong, K.I. A PLL clock generator with 5 to 110 MHz of lock range for microprocessors. IEEE J. Solid State Circuits 1992, 27, 1599–1607. [CrossRef] 29. Zhan, Y.; Kumar, S.V.; Sapatnekar, S.S. Thermally Aware Design. Found. Trends Electron. Des. Autom. 2007, 2, 255–370. [CrossRef] 30. Pecht, M.; Lall, P.; Hakim, E.B. The influence of temperature on integrated circuit failure mechanisms. Qual. Reliab. Eng. Int. 1992, 8, 159–316. [CrossRef] 31. Li, Y.; Wang, Z.; Midya, R.; Xia, Q.; Yang, J.J. Review of memristor devices in neuromorphic computing: Materials sciences and device challenges. J. Phys. D Appl. Phys. 2018, 51, 1–14. [CrossRef]

© 2019 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).