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Digital and Analog Applications of Double Gate Mosfets

Digital and Analog Applications of Double Gate Mosfets

DIGITAL AND ANALOG APPLICATIONS OF DOUBLE GATE

A thesis presented to

the faculty of the

Fritz J. and Dolores H. Russ

College of and

of

Ohio

In partial fulfillment

of the requirements for the degree

Master of

Swetha Varadharajan

November 2005

This thesis entitled

DIGITAL AND ANALOG APPLICATIONS OF DOUBLE GATE MOSFETS

by

SWETHA VARADHARAJAN

has been approved for

the School of and Science

and The Russ College of Engineering and Technology by

Savas Kaya

Assistant Professor of Electrical Engineering and

Dennis Irwin,

Dean, Russ College of Engineering and Technology

VARADHARAJAN, SWETHA. M.S. November 2005. Electrical Engineering and

Computer Science

Digital and Analog Applications of Double gate MOSFETs(72pp.)

Director of Thesis: Savas Kaya

Moore’s law a continuous scaling down of devices with time. The technological trends to keep up with this empirical observation have ascertained Double gate MOSFETs as the imminent generation . This thesis investigates the digital and analog applications of the DG-MOSFETs. We illustrate the digital circuit applications of this novel device in the pass transistor logic (PTL).The ON resistance of the Double-gate MOSFET in the PTL logic shows attractive results over the conventional MOS PTL logic circuits. Also, we have implemented the PTL logic as an XOR gate and compared the device performance. The digital applications also include configurable based on a theoretical concept put forth by Paul Beckett. Furthermore, the analog applications include the mixer applications of DG-MOSFETs demonstrating an improved performance over the traditional MOSFET mixers. The effects of varying the physical parameters of the DG-MOSFET have been studied in a mixer.

Approved:

Savas Kaya

Assistant Professor of Electrical Engineering and Computer Science

ACKNOWLEDGEMENTS

My thesis has been an extremely delightful and an enriching experience throughout. Thanks to Dr. Kaya for making my graduate a thoroughly enjoyable . His genial disposition and enthusiasm has been a constant driving force and has helped me look beyond the text .

I would like to thank Dr.Janusz Starzyk for his valuable class discussions and course work in VLSI. I also want to express my appreciation to my committee members Dr.Henryk Lozykowski and Dr.Xiaoping Shen .

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TABLE OF CONTENTS

ABSTRACT ...... 3

ACKNOWLEDGEMENTS ...... 4

LIST OF TABLES ...... 7

LIST OF FIGURES ...... 8

LIST OF ABBREVIATIONS...... 11

1. INTRODUCTION...... 12

1.1. OVERVIEW...... 12

1.2. CURRENT RESEARCH...... 14

2. BACKGROUND ...... 16

2.1. OUTLINE ...... 16

2.2. DEVICE SCALING...... 17

2.3. ON ...... 19

2.4. RF APPLICATIONS OF SOI...... 21

2.5. DOUBLE GATE MOSFET ...... 22

2.6. DEVICE SIMULATOR...... 25

2.6.1. ISE-TCAD ...... 25

2.6.2. MDRAW ...... 25

2.6.3. DESSIS ...... 27

2.6.4. INITIAL STEPS ...... 27

2.6.5. SECTION...... 28

2.6.6. CIRCUIT ...... 29

2.6.7. INSPECT AND XMGRACE...... 29

2.6.8. MATLAB ...... 29

3. DIGITAL APPLICATIONS...... 31 6

3.1. BASIC DEVICE AND SETUP...... 31

3.2. PASS GATE LOGIC ...... 33

3.3. INITIAL RESULTS...... 35

3.4. XOR ...... 36

3.5. RECONFIGURABLE STRUCTURES ...... 38

3.5.1. BIAS SUSCEPTIBILITY...... 45

3.6. NEW RECONFIGURABLE XOR GATE...... 46

4. ANALOG APPLICATIONS ...... 49

4.1. MIXER OVERVIEW...... 49

4.2. MIXING PRINCIPLE...... 51

4.3. MIXER SETUP AND RESULTS...... 53

4.4. MODIFIED MIXER CONFIGURATION ...... 58

5. SUMMARY AND CONCLUDING REMARKS...... 61

5.1. SUMMARY ...... 61

5.2. FUTURE WORK ...... 62

6. REFERENCES...... 64

7. APPENDICES...... 66

A. MATLAB CODE ...... 66

B. DESSIS COMMAND FILE ...... 67

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LIST OF TABLES

Table 2.1Comparison of the effect of scaling on MOSFET device parameters...... 17 Table 3.1 Device parameters used in the simulation setup...... 32 Table 3.2 Transitional delay comparison of transmission gate and DDG...... 38 Table 3.3 Different operating conditions of gate to derive various functionalities [13]...... 41 Table 3.4 the back gate at different levels various functionalities can be realized...... 47

8

LIST OF FIGURES

Fig 1.1 Technology node vs. time...... 13 Fig 1.2 MOSFET scaling trend for high performance [2] ...... 13 Fig 2.1 Time line of conventional MOS structure to the future transistor [4]...... 16 Fig 2.2 MOSFET device scaling [6]...... 18 Fig 2.3 A simple SOI FET ...... 20

Fig 2.4 Structure of DGMOSFET with a thin body ( tsi = 10 nm) and a gate length (Lg) of 50 nm ...... 23 Fig 2.5 Schematic band diagrams for symmetric and Asymmetric DG-MOSFET ...... 23 Fig 2.6 Variation of concentration with body thickness...... 24 Fig 2.7 MDRAW GUI showing the structure of a DGMOSFET ...... 26 Fig 2.8 Typical flows with DESSIS device simulation...... 30 Fig 3.1 Device structures used for TCAD simulation...... 32 Fig 3.2. nMOS and pMOS in pass gate configuration...... 33 Fig 3.3 Comparison of device structures transmitting low and high ...... 34 Fig 3.4 DG-MOSFET in the CMOS configuration transmits signals with the least resistance...... 35 Fig 3.5 Pass transistor implementation of an XOR gate...... 36 Fig 3.6 XOR gate implemented using DDG...... 37 Fig 3.7 Timing results of an XOR gate...... 37 Fig 3.8 Id-Vg characteristics of DG-MOSFET with fixed top gate ...... 39 Fig 3.9 DC characteristics of an held at different back gate voltages...... 40 Fig 3.10 A configurable 2-NAND gate...... 41 Fig 3.11. Figure demonstrates the condition when Vg1=-1.5V, Vg2=-1.5V and Output = 0V...... 42 9

Fig 3.12 Figure demonstrates the condition when Vg1=1.5V, Vg2=1.5V and Output = 1 V...... 43 Fig 3.13. Figure demonstrates the condition when Vg1= 0 V, Vg2= 1.5V and Output =

A ...... 43

Fig 3.14 Figure demonstrates the condition when Vg1= 0 V, Vg2= 0 V and Output =

AB ...... 44

Fig 3.15 Figure demonstrates the condition Vg1= 2 V, Vg2= 0 V and Output = B ..... 44

Fig 3.16 Circuit simulated to obtain the B ...... 46

Fig 3.17 Proposed new structure based on pass gate logic...... 47 Fig 3.18 XOR gate output for the new reconfigurable structure...... 48 Fig 4.1 The mixer circuit topology used in mixed-mode ...... 50 Fig 4.2 An independently driven double gate MOSFET – IDDG ...... 50 Fig 4.3 Symmetrically driven DG-MOSFET (SDDG)...... 50 Fig 4.4 Two frequencies f1 and f2 at different operating points A and B generating outputs of different [18] ...... 51 Fig 4.5 Output spectra of a Down converting mixer [19]...... 53 Fig 4.6 Various physical parameters of DGMOSFET varied with constant gate length of 50nm...... 54

Fig 4.7 The FFT of mixer drain current (Imix)...... 55 Fig 4.8 The DGMOSFET mixer with symmetrical gates has the most linear mixer output...... 56 Fig 4.9 Asymmetry in DG mixer has beneficial impact up to barrier difference of 0.5 eV, beyond which the spectra is cluttered with high-order terms...... 56 Fig 4.10 Dependence of DG-MOSFET mixer on the Si body thickness...... 57 Fig 4.11 Body in DG-MOSFET has minimal impact on mixer performance...... 58 Fig 4.12 A new mixer configuration...... 59 10

Fig 4.13 A modified mixer with inputs at both the gates...... 59 Fig 4.14 Comparison of two mixer outputs normalized to the 300Mhz magnitude...... 60

11

LIST OF ABBREVIATIONS

CMOS Complimentary Metal Oxide

MOSFET Metal Oxide Semiconductor Field Effect Transistor

IC

SCE Short Channel Effects

SOI

BOX Buried Oxide

FD Fully Depleted

PD Partially Depleted

DG Double Gate

RF Frequency

ISE Integrated Engineering

TCAD Technology Computer Aided Simulation

DIBL Drain-Induced Barrier Lowering

DD Drift-Diffusion

HD Hydrodynamic

QM Quantum Mechanical

PTL Pass Transistor Logic

DDG Double Gate MOSFET in transmission gate logic 12

1

1. INTRODUCTION

1.1. OVERVIEW

The driving force behind any form of the modern-day electronic gadget is an integrated circuit containing millions of transistors. In the past 50 years since the discovery of the transistor action at , these devices have undergone gargantuan changes. The of CMOS has enabled remarkable advancement in the world of providing smaller and faster transistors. The scaling of the transistor dimensions has to higher current driven and higher density chips.

Moore’s law [1] projects the shrinking dimensions on an exponential curve with the number of transistors doubling every two years. This trend extrapolates current chips to have more than a billion transistors (Fig.1.2) and channel lengths lesser than 30nm by 2010 (Fig.1.1). This race for smaller and high efficiency chips has led to the exploration of nanometer scale CMOS alternatives. Looking further down the lane, 2014 has a ~10nm length transistor in store [2].

There are various practical and theoretical challenges to be addressed if the device must be aggressively scaled to such small dimensions. Going beyond the 10nm limit, the novel revolutionary ranging from nanotubes to the molecular structures have proposed various alternatives as a potential successor to replace silicon as the medium. 13

Fig 1.1 Technology node vs. time Fig 1.2 MOSFET scaling trend for high performance [2]

Progress in the alternatives structures is based on a thorough comprehension of the underlying device physics parameters. In the nanometer regime (~10nm) the device dimensions are comparable to the de Broglie wavelength. The conventional drift diffusion models based on the macroscopic scattering models are no longer applicable at such small dimensions. Quantum effects must be included in the nanometer dimensions. Hence device designers must employ new modeling theories and effective device simulators to be able to investigate and optimize the novel device structures. The use of Technology CAD (TCAD) simulator allows such flexibility and offers means to explore new devices. As a result of which the new generation of transistors has opened vast venues for . This thesis is an endeavor to study one such emerging technology, the double gate MOSFET. 14

1.2. CURRENT RESEARCH

The main objectives of this thesis are 1) to exploit the benefits of the Double gate MOSFETs for digital applications using pass transistor logic (PTL) circuits, 2) To analyze the full potential of the dual gate MOSFET in the RF circuits as a mixer. All the simulations are carried out using ISE’s (Integrated ) TCAD (technology computer aided design) suite, which integrates many design productivity and simulation .

The thesis begins with the need for new structures and an investigation for the need of SOIs in today’s semiconductor world. The device scaling issue is discussed and an alternate form of SOI, the double gate MOSFET is put forth. It also includes an account of the ISE-TCAD simulator used for device simulation and a description of the various circuit models used for the digital and analog applications of DG-MOSFET discussed.

Chapter 3 is a discussion of the digital application of the DG-MOSFET namely in the pass gate logic and it is substantiated with the simulated results and graphs obtained. The various PTL logic circuit model gains along with curves and delay calculations are elucidated. Further, the digital applications include the demonstration of reconfigurability in double gate MOSFETs. It is the first known simulation of a theoretical concept put forward by Paul Beckett [13]. We have also put forth a new reconfigurable structure demonstrating three different functionalities including an XOR gate.

The fourth Chapter is an insight into the mixer applications of the DG-MOSFET in the RF field and its significant advantages discussed .Various characteristics of the 15 mixer are simulated changing the physical nature of the dual gate device and the most profitable device characteristics for optimum performance. New mixer structures are also presented in this chapter. The final chapter sums up the entire work and the future work in each application discussed. 16

2

2. BACKGROUND

2.1. OUTLINE

Double gate MOSFETs has been shown to be superior in the nanometer regime due to the significant area and current over their conventional counterparts [3]. They can be scaled down to ~10nm and yet have minimal . Hence it makes them an appealing replacement to the existing technology (Fig.2.1) for various applications. Since the entire report is based on a scaled device operation and its advantages a heard start about device scaling will provide the required insight into the need for a novel device.

Fig 2.1 Time line of conventional MOS structure to the future transistor [4]

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2.2. DEVICE SCALING

A lot of higher level requirements for new materials , methods and environmental control are in the forefront of the recent research discussions but primarily what lies beneath all these is the transistors limitation . The number of gates has quadrupled in the last three years .By reducing the device dimensions more gates are packed into a chip increasing the density while the overall of the chip has increased as well.

Table 2.1 Comparison of the effect of scaling on MOSFET device parameters. Compared are constant field scaling, constant voltage scaling and constant voltage scaling in the presence of velocity saturation. [5]

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There are different scaling schemes but the fundamental philosophy behind all of them is scaling the geometrical dimensions and voltage values. Table.2.1 and Fig.2.2 illustrate the constant field scaling technology with respect to the device dimensions and other scaling parameters

Fig 2.2 MOSFET device scaling [6] .

The delay and power parameters are worth considering at this juncture.

2 2 τ Min.Cycle = 12 n L min VDD / μe [V DD – V Tn ] (2.1) 2 * 2 PP ave @ Max.f = L VDD f max α μe C ox VVDD [ DD – VTn] [W min / L min] (2.2)

τ represents the gate delay and P the average capacitive power dissipated during the switching cycle. The digital circuits have the transistors toggling between ‘0’ and ‘1’ and during that the output capacitance is charged or discharged through the pMOS or nMOS transistor. Ideally, we require faster and smaller and high density gates emitting less power during those transitions from one to another. With simple math it might 19 appear that if we divide the voltage and dimension (L) by a simple scaling factor s there’s a lesser τ and P and hence a faster and smaller gate. The glitch scaling the voltage supply is that the of silicon is 1.1 eV and reducing the voltage any further below that makes is virtually impossible to operate the transistor.

If we modify the other voltage term involved, the threshold voltage (Vt), reducing it increases the and hence more gate leakage. Since voltage reduction is a good solution for low power along with its limitations, one of the alternatives is maintain the performance, scaling the voltage but keeping other parameters intact e.g. Gate leakage. Silicon on insulator devices provides this key advantage of reduced off state leakage at reduced voltages.

2.3. SILICON ON INSULATOR

The SOI market boomed because of its improvement in the CMOS performance. The need for a change to SOI lies in increasing the gate control over the channel, with decreasing gate length. It does not offer augmented but has reduced capacitance effects as well as leakage currents.

The SOI varies from its conventional counterparts with a layer of oxide acting as an insulator over the silicon and a thin body (Fig.2.3). The advantages of having a thin body over the insulator can be understood better in the capacitive point of view due to scaling. As the channel length decreases the ratio of gate-to-channel capacitance over drain-to-channel capacitance decreases gradually. This effectively means the gate gradually looses its domination of channel electrostatics, i.e. its control. 20

Fig 2.3 A simple SOI FET

Conduction in a transistor happens due to the switching activity controlled by the gate. Once gate control is reduced the leakage currents increases and other effects such as the drain induced barrier lowering are visible.

One of the ways to reduce this charge increase (depletion region) around the drain is to increase the substrate doping. It has been showed that channel doping must be increased about 1.6x per generation to prevent short channel effects [7].This in turn increases the threshold voltage which causes the MOSFET to have a thinner oxide. The main drawbacks of a thin oxide are tunneling and the gate oxide breakdown. Other ways to reduce the depletion region is by using a thin body with which the drain has a lesser control over the channel.

The primary feature of the SOI is its thin body which eliminates the total drain/source area junction capacitance. Based on the body design the SOI can be either partially depleted (PDSOI) or fully depleted (FDSOI). If the body thickness is greater 21 than the depletion width, leaving a neutral region that extends down to the buried oxide insulation layer it’s partially depleted and if the width of the body is made thinner than the channel depletion region it’s a fully depleted SOI. With increased scaling and other undesirable outcomes such the kink effects the FDSOI is preferred over the PDSOI. FDSOI offers the most performance driven advantages especially in the RF areas.

2.4. RF APPLICATIONS OF SOI

As applications become commonplace, SOI devices have witnessed a widespread use in the mixed signal and RF fields. Wireless require high- performance transistors and low-loss passive devices ( and ). The high resistivity SOI substrates (>2K Omega-cm), tender high Q for the passive elements (i.e., Q greater than 30), and hence minimized among analog and digital circuits. Thus SOI provides not only a medium to improve MOSFET performance, but also a platform for monolithic RF integration.

FD-SOI technology has a number of advantages for RF with respect to conventional bulk transistors. It is considered to be the most suitable for ultra-low-

voltage and ultra-low power operation [8]. The transconductance (gm) is better in a

FDSOI and hence their current gain cut-off frequency Ft. The maximum oscillation

frequency Fmax, the most relevant figure of merit for RF transistors, is much better for FD-SOI than for BULK due to the reduction of parasitic capacitances. This ability of the SOI devices to integrate both low power and high performance RF on the same platform has opened a variety of interesting areas to explore such as and mixed- circuit applications. 22

2.5. DOUBLE GATE MOSFET

The acceleration of Moore’s law in the last five years, coupled with rapid advancements in the wireless field has forced aggressive downscaling in the existing MOSFET structures. Higher cut-off frequencies are obtained if the gate –lengths are reduced. Though the current SOI technology has eased the trade-offs in bulk MOSFETs for optimum performance, below ~50nm various new configurations will be required to maintain the same and also mitigate the short channel effects due very small dimensions.

Reminiscing on the bulk MOS disadvantages again, whenever the electrostatic control of the channel by the gate is taken over by the source and the drain the transistor’s switching activity degrades. The transistor leaks and become ill-performing. An additional gate with the same source, drain and body enforces additional control over the channel and restores the gate control. The net gain is the current increase since they have a structure analogous to two transistors mounted back to back. As a matter of fact, close placement of two gates across a thin body results in doubling of channels, hence more current. Moreover the proximity of the two gates leads to stronger quantum mechanical confinement effects and provides additional means to control the threshold(s). The DGMOSFET (Fig.2.4) applies the SOI technology with a thin un-doped body but there is no real “depletion region” .The channels properties are modified by the gates on either side modulating the field. 23

Fig 2.4 Structure of DGMOSFET with a thin body ( tsi = 10 nm) and a gate length (Lg) of 50 nm

The electrostatics of the DGMOSFET can be divided into two broad categories as symmetrical and asymmetrical. The symmetric devices have the same gate bias and work function and hence turn ON at the same time .The asymmetric devices can have different bias and work functions (Fig.2.5).

Fig 2.5 Schematic band diagrams for symmetric and Asymmetric DG-MOSFET Figure shows different gate work functions. Adapted from [9]

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Fig 2.6 Variation of electron concentration with body thickness. The channel formation is distinguished for a SDG from an ADG when the body thickness is varied. [10]

The charge peaks corresponding to two channel locations for the symmetric and asymmetric cases as shown in Fig.2.6, they are equal for the former case whereas there is a single peak based on the work function for the latter case. The above argument holds good for a reasonably thick body but when it reaches about 5nm the peaks for both the cases merge and there’s a single peak in the middle of the body. In the current thesis I’ve considered both the symmetric and asymmetric devices with various work functions and characterized various functionalities for both the cases. All simulations have been carried out using the technology CAD (TCAD). It is one of the most versatile device simulators available in the market today.

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2.6. DEVICE SIMULATOR

The aggressive scaling of the semiconductor devices has created a need for accurate device simulators for atomic scale modeling and an in - depth appreciation of the nano- scale device operation. The predictive simulations help reduce the exorbitant costs involved with real time fabrication and testing experiments. Device simulators also enable fast of complex numerical equations. It has also been a of testing and development for many numerical tools now.

2.6.1. ISE-TCAD

ISE- TCAD [11] is one of the most advanced -state device simulation for 1D, 2D and 3D geometries. It includes extensive compact models, physical description tools and numerical devices that can be applied to a wide range of problems from simulation through physics based device modeling and mixed mode circuit simulation. Using TCAD to simulate a complete circuit begins with device description followed by device simulation.

2.6.2. MDRAW

The Double Gate MOSFET is designed for premeditated dimensions using MDRAW. The entire device is described using mesh points .MDRAW has various options wherein the structure can be changed at its boundaries, various doping profiles marked and additional refinement regions illustrated. The Fig.2.7 shows an MDRAW GUI 26 environment of the DG –MOSFET. The device editor and the mesh generator can be accessed in the script mode.

Fig 2.7 MDRAW GUI showing the structure of a DGMOSFET The boundary and mesh was created along with appropriate S/D doping.

The ability to create a precise model of the proposed structure lies in the clever design of the mesh points. The critical regions of the device are marked with increased number of points. The given double gate MOSFET has around 4000 mesh points with more importance at its gate, source and drain contact regions.

The device doping and boundaries obtained from MDRAW are described in a .dat and a .grd file. The files are exported for further circuit and device simulations using DESSIS. The .grid file containing the boundary, node and material type and the .dat file containing the doping profile information provides a virtual approximation of the actual device. 27

2.6.3. DESSIS

The salient feature of DESSIS is the electrical, thermal and optical characterization of devices in a multi-dimensional environment. The numerical on which the simulator is based are by far the most efficient providing rigorous formulations and good convergence. The devices can be simulated as a separate entity or in conjunction with an external contact circuitry or in conjunction with various other devices.

These mixed-mode circuit simulations take place on an elaborate physics based framework which includes various drift diffusion, thermodynamic, hydrodynamic ,Monte Carlo and Schrödinger solvers and physics – includes tunneling through insulators, hot carrier injection ,interface traps etc. Analyzing the various sections of a typical DESSIS command file provides an insight into the simulation approach for the model characterization. The device is described under the file section subdivided into the electrode, thermode and physics sections followed by the various maths and solve sections and a section for the plots.

2.6.4. INITIAL STEPS

The file command loads the grid and the doping information obtained from MDRAW. It also contains the device model parameters listed either in the standard or modified format. The device model parameters are given as inputs in a standard format with a .par extension. The file can also be modified and loaded to adjust parameters of the physical models. The results of the simulation are stored using the save, plot and current files and their functions synonymous with their . 28

The electrode section contains the information about the electrodes of the device such as the gate, drain, source etc. along with their voltage values. It can also refer to the type of electrode material for example, Gate: Poly silicon, barrier height, velocities for and holes and contact resistances.

2.6.5. PHYSICS SECTION

The physics section contains two key parts. The first part contains a list of parameters under a global model such as Thermodynamic or Hydrodynamic and the second section comprises of mobility, recombination and other selection commands. An overview of the various sub-sections characterizes the various features as follows.

The accuracy with which the chosen device would be resolved by the transport equations can be either using drift-diffusion, thermodynamic, hydrodynamic or Monte Carlo. The double gate MOSFETs are solved using the hydrodynamic model. In this model the energy transport of carriers are accounted and the drawbacks of drift-diffusion such as lack of velocity overshoot and overestimation of impact ionization are described well. The continuity and Poisson equations along with the current density equations are solved in this model.

The density gradient model was used for the double Gate quantization model .A numerically robust method; it provides a reasonably realistic distribution of charges inside the device. The main feature of this model is its ability to include the function of the electrons and holes in concurrence with the device scaling rules. The potential introduced as a correction can be included with the terms eQuantumpotenial and hQuantumpotential. 29

2.6.6. CIRCUIT SIMULATION

Once the basic conditioning of the device is completed using the various physics equations the circuit is solved on the basis of a SPICE model. The various components of the circuit described, nodes marked and the physical connections mentioned under the section along with any capacitive or resistive values that may appear in the circuit.

2.6.7. INSPECT AND XMGRACE

The results obtained from the DESSIS simulation are plotted using these packages. Most plots in this thesis expecting the ones from MATLAB are plotted using INSPECT or XMGRACE. The packages enable to dimensional plotting .XMGRACE has some additional functions used in transconductance calculations.

2.6.8. MATLAB

The current obtained from the mixer application of the DG-MOSFET is analyzed using MATLAB. The is interpolated on a uniform range for various simulations. Then the Discrete (DFT) and frequency shifting is used to obtain the main and difference signals. The magnitudes of the main and difference signals are obtained and plotted against various parameters and the graphs elucidates later in the thesis. The entire simulation flow is show in the Fig.2.8. 30

Fig 2.8 Typical design flows with DESSIS device simulation

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3

3. DIGITAL APPLICATIONS

DGMOSFET has proven to be one of the pioneers of a future transistor. This emergence of the DGMOSFET has sparked innumerable research venues to explore. It has also been the main motivation of our research efforts moving forward from the mere device design to its real world applications in the digital and analog fields. Electronics is broadly classified as being either analog or digital. Thus it is worthwhile look at specific applications under each category and appreciate the gain a double gate would impart for the same.

3.1. BASIC DEVICE STRUCTURE AND SETUP

The digital applications are based on the comparison between the double gate and the conventional MOSFET. It is therefore very crucial to obtain an accurate model of both the structures. The Fig.3.1 shows the general representation of the two transistors. They are designed using the parameters shown in the Table.3.1. These structures have the same gate and substrate characteristics for meaningful comparative simulations. The body thickness is kept at 10 nm for the double gate device and 30 nm for the conventional SOI and the thickness contributes significantly towards the formers performance.

The input file of DESSIS is mainly used for the declaration of the device parameter set, definition of device types and circuit , which can be either an electrical or thermal circuit. The systems section of the command file contains all the declarations of the circuit. Various parameters using DC, transient and AC simulations can be extracted from the circuits. In all the cases DESSIS has a choice of four different simulation modes based on the device and the modeling requirements as Drift-diffusion, 32

a. DG MOSFET b. SOI MOSFET

Fig 3.1 Device structures used for TCAD simulation.

Table 3.1 Device parameters used in the simulation setup.

Thermodynamic, Hydrodynamic or Monte Carlo. Various parameters using DC, transient and AC simulations can be extracted from the circuits. In all the cases DESSIS has a choice of four different transport modes based on the device and the modeling requirements as Drift-diffusion, Thermodynamic, Hydrodynamic or Monte Carlo 33

3.2. PASS GATE LOGIC

The basic principle behind the pass transistor is its transfer of logic from input to output unaltered. The transfer is controlled by the third terminal which decides the ON/OFF state of the device. The output from the ON state is held in the high Z-state when the device goes OFF. Also the basic operations of the nMOS and the pMOS that the former passes a strong zero and the latter passes a strong 1 are made use of in the PTL logic circuits

Fig 3.2. nMOS and pMOS transistors in pass gate configuration. Figure shows PTL transmitting a. high signal b. a low signal c. CMOS transmission gate and logic symbol 34

Combining both the pMOS and nMOS together a CMOS transmission gate capable of transmitting both strong zeros and ones can be achieved for better performance. A comparative figure of the various pass configurations is shown in Fig.3.2.

Since the pass is based on the transmission of either a 1 or a 0 the transmission capability is better understood analyzing the ON-resistance paths of the device. It is performed using two cases as shown in Fig.3.3 when it passes a low and a high signal. The four devices, namely the nMOS, the transmission gate, n-type double gate (DG) MOSFET and a transmission gate (DDG) with complementary DG MOSFETs are evaluated to identify their role in transmitting the same. The inputs are held at the logic 0 and logic 1 levels and the outputs observed.

Fig 3.3 Comparison of device structures transmitting low and high signals. a. nMOS device structure simulated to measure the ON-resistances when the output changes from high to low. The left inset shows the CMOS transmission gate and the right shows a DGMOSFET b. nMOS device transmitting a low to high signal. The left inset shows the conventional CMOS

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3.3. INITIAL RESULTS

The ON resistance for the devices when the input is held high is obtained using

transient simulations. The analysis is carried out with the input at VDD and the output

changes from 0 to VDD. In the case of the transmission gate the pMOS device is in

saturation and then to linear region as the output increases to VDD. The ON resistance for the four devices is shown in Fig.3.4. The results clearly show the dominance of the double gate MOSFET over the conventional counterparts with the DDG (double gate MOSFET in transmission gate configuration) exhibiting the best ON- state conduction and least resistance. The most interesting observation is the ON- resistance of a single DG-MOSFET device as compared to the conventional transmission gate device.

Fig 3.4 DG-MOSFET in the CMOS configuration transmits signals with the least resistance The ON-resistance curves illustrate the gain a single double gate MOSFET provides over two conventional MOSFETs in a CMOS transmission gate.

36

It is seen that a DG-MOSFET has a lower resistance than the transmission gate consisting of two transistors. This may imply gains in some applications where a single DG-MOSFET can replace a transmission gate with two conventional transistors and provide more current with lesser area! However, even in this case, long chains of DG MOSFETs may still be prohibitive due to degradation of ‘1’ in passing non- complementary transmission gates.

3.4. XOR IMPLEMENTATION

The transmission capability of the pass gate transistor has been used to reduce the number of transistors required to implement certain logic functions. XOR being one of the popular gates implemented, it is interesting to study the gain we obtain moving towards the double gate technology. The XOR gate (Fig.3.5) is implemented using the conventional transmission gate and the DDG configuration.

Fig 3.5 Pass transistor implementation of an XOR gate

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Fig 3.6 XOR gate implemented using DDG. Fig 3.7 Timing results of an XOR gate.

Due to absence of contact in DGMOS technology Implementation uses conventional PTL.

Bipolar logic levels + 0.3 V required

The working is the same in both the cases. It has a two gate (control) signals which decides on the output signal that passes at any given time. A conventional static CMOS gate version takes 8 gates to implement a XOR gate whereas the pass transistor logic takes only 4 transistors to implement the same logic. The difference between the conventional transmission gate and the DDG is better understood from the two waveform plots (Fig.3.6, Fig.3.7). The inputs and outputs signals from the XOR gate for the two are plotted for comparing their responses.

The rise and fall delays of the transmission gate and the DDG type XOR gates are calculated from the waveforms and listed in the Table.3.2. It is seen from the average calculated delays that the double gate MOSFET implemented as an XOR gate has about 38

20% lesser delay than the transmission gate logic. It is definitely an appreciable gain in speed along with the higher current drive of the double gate MOSFET.

Table 3.2 Transitional delay comparison of transmission gate and DDG. DDG has 25% lesser delay than the conventional counterpart.

XOR gate is just one of the applications implemented using the DG-MOSFET. With the advantages of the DG-MOSFET established it is useful to look at one of the interesting burgeoning fields of nano-scale systems, reconfigurable structures.

3.5. RECONFIGURABLE STRUCTURES

As the device dimensions reduce manipulating devices will be a major hindrance to packing multiple circuits closely together, with low manufacturing defects. If a third dimension is added to the existing devices to extract additional functionality it will be a 39

simpler compatible with the existing technology as well as a novel technology that can be extended into the future Double gate MOSFET is a fitting device that can be implemented as a reconfigurable structure without modifying the physical structure alone since one of the gates can be used to dynamically shift the threshold for the other gate.

Fig 3.8 Id-Vg characteristics of DG-MOSFET with fixed top gate voltage.

The proposed structure using the Double Gate MOSFET as a reconfigurable structure was detailed by Paul Beckett [13]. The main core of his was varying the bias voltage of the DG-MOSFET and changing the operating points of the transistor to obtain three different levels of working with a single transistor such that its there is a intermediate stage apart from the ON/OFF state. The Fig.3.8 shows the Id-Vg characteristics of the DG-MOSFET was plotted fixing the bottom gate bias at different 40

levels from -2V to 2V and then sweeping the top gate in each case to measure the output drain current. It is clear that the bias voltage of any one of the gates can be adjusted keeping the other a constant to operate the device at different regions. Thus one can obtain not only a switchable device (as a function of top gate) but also a completely ON or OFF device independent of top gate.

Fig 3.9 DC characteristics of an inverter held at different back gate voltages.

A very simple inverter demonstrates the shift in the operating conditions with various back gate voltages as shown in the Fig.3.9. The pMOS and nMOS shift in opposite directions with the application of any specific back gate voltage since they are tied together. The characteristics are consistent with the curves demonstrated in [14] for a planar “” (GP) CMOS inverter. With the given different operating points for a DG-MOSFET it was rigged with other similar transistors to achieve multi-level 41

functionality using the circuit shown in Fig.3.10.The circuit was theoretically proposed by Beckett with two input NAND gates. No detailed simulations have been done to verify operation of this compact circuit. In the following we shall use a accurate and detailed TCAD simulations to investigate the operation, performance and reliability of this reconfigurable architecture.

Fig 3.10 A configurable 2-NAND gate Table 3.3 Different operating conditions of gate Proposed in [13]. voltages to derive various functionalities [13]

In the circuit the gates are controlled by their back gate bias. With each gate having three operating conditions it can be extrapolated to 5 distinct functionalities (Table.3.3). The basic working principle behind the circuit is that the pMOS and nMOS behave like conventional way when a high/low signal is applied to their first gate irrespective of their second gate condition, i.e. pMOS is ON with a low (-2V) applied to any one of its gates and OFF when a high (2V) is applied to its gates and vice versa with the nMOS transistor. When a zero is applied is applied to either the nMOS or the pMOS the device exhibits an interesting structure. With a zero on any one of its gates the state of 42 the device as either ON/OFF is decided by the second gate. If the second gate is zero the device is just turned ON and behaves like a short circuit

With this background the circuit proposed in [13] was simulated. Though the circuit looks ideal following the table, in practicality appreciable amount of time was required to the circuit to achieve the functionality as mentioned. One of the main considerations for the overall circuit was a careful design with respect to the working voltage. Either a low or a high value of the supplied voltage rendered the output values either as high or low logic value alone. An optimum voltage of 1.5 V was required for the values of A and B for the devices in this thesis. Any value lower around 1V was not sufficient to ramp up the output to the required logic value .Similarly any value above the nominal value was too high and the output was left high irrespective of the input values. The circuit simulated under for various gate voltages is shown in the Fig.3.11 – Fig.3.15 depicts the input voltages and the outputs for the circuit.

Fig 3.11. Figure demonstrates the condition when Vg1=-1.5V, Vg2=-1.5V and Output = 0V 43

Fig 3.12 Figure demonstrates the condition when Vg1=1.5V, Vg2=1.5V and Output = 1 V

Fig 3.13. Figure demonstrates the condition when Vg1= 0 V, Vg2= 1.5V and Output = A 44

Fig 3.14 Figure demonstrates the condition when Vg1= 0 V, Vg2= 0 V and Output = AB

Fig 3.15 Figure demonstrates the condition Vg1= 2 V, Vg2= 0 V and Output = B

45

Advantages of this circuit are briefed as follows. Firstly the most apparent benefit being the number of transistors. The functionalities in a single circuit (4 transistors) have lesser number of transistors than the number required implementing all of them independently (~8-10 transistors). Secondly with scaling, circuits with configurable structures gain more importance. Double gate MOSFET now has the dual advantage as the transistor scalable up to ~10nm and configurable for multiple functionalities as well. Thirdly it’s the inherent nature of the DG-MOSFET itself, namely its higher current drive and area savings makes them as one of them most appealing transistor for novel structures.

3.5.1. BIAS SUSCEPTIBILITY

All of the above can be realized from the reconfigurable structures only when the device parameters are carefully selected. One of the most important parameters is the bias voltage. It cannot be either too high or low as shown in the Fig.3.16 which would cause a faulty output and dynamically alters the threshold for top gate At any given supply voltage, careful engineering of the threshold voltage shifts (via back gate bias ) should optimize the functionalities intended.. Furthermore, intelligent design of these circuits may even allow realization of multiple functionalities as a function of multi bias levels. In other words, one is not limited to three bias levels and more may be conceived.

46

Fig 3.16 Circuit simulated to obtain the B function

If Vin is low the output does not rise to the required output level and if Vin is too high the output is stuck high. The bias voltages must be carefully chosen for the reconfigurable structure shown in Fig.3.10

3.6. NEW RECONFIGURABLE XOR GATE

In this section, we put forth an XOR gate structure (fig.3.17) based on the reconfigurable architecture as simulated in the previous section. The structure has a two fold advantage: it barrows from the ideas in both the PTL and the reconfigurable logic structures. In other terms, this circuit has only 4 transistors as compared to the static gate logic for an XOR gate with 8 transistors and the same circuit can be configured to obtain three different functions as shown in Table 3.4 47

Fig 3.17 Proposed new structure based on pass gate Table 3.4 Biasing the back gate at different levels logic. various functionalities can be realized.

The simulated circuit is shown in fig 3.18 for the proposed XOR gate. After initial convergence issues with the simulator, it has been shown that an XOR gate is possible using this structure. The feasibility of such structures opens further venues for newer circuits. Out of the three functionalities the XOR has been successfully tested in ISE TCAD tools. However, convergence problems have prevented the demonstration of the other two cases. With further tweaking, the mathematical convergence issues of the simulator can be rectified to obtain the other two functionalities for the same circuit. 48

Fig 3.18 XOR gate output for the new reconfigurable structure.

49

4

4. ANALOG APPLICATIONS

Mixers are an part of any communication system. Sending signals reliably over the communication channels begins primarily at the mixer stage. It is required to have minimal leakage and dominant mixed signals along with the other fundamental signals. Double gate MOSFET is one of the suitable candidates for the mixer applications with its dual gates. The gates make it attractive for applications which involve interaction between signals. Applications of DG MOSFET as a mixer has been previously shown in [15] [16] and [17]. In this thesis in particular, we investigate DG-MOSFET mixer circuits containing a single DG-MOSFET with symmetric-gate architecture. Our analysis also considers asymmetric DG-MOSFETs with unequal barrier heights and devices with varying SOI channel thickness and doping scenarios. Thus we investigate the performance of mixers based on device design options.

4.1. MIXER OVERVIEW

All the configurations of the mixer are simulated using the basic circuit (Fig.4.1).

The Vdd value is fixed at 2V .The DGMOSFET is fed dc current through a current circuit consisting of two nMOS transistors. It has been shown in [15] that the double gate MOSFET can be configured in two different ways either as a independently driven double gate MOSFETs(IDDG) (Fig.4.2) or simultaneously driven double gate ’s (SDDG) as shown in Fig.4.3. The mixer configuration operating at difference frequencies is made possible through the IDDG configuration. The DGMOS is designed to be a depletion type transistor and works in saturation all the time. The gates at zero bias are connected to two independent AC sources. 50

The output is the drain current of the double gate MOSFET. The output has the main two frequencies along with other additional components .In particular various frequencies are generated based on cross of fundamental signals and their harmonics.

Fig 4.1 The mixer circuit topology used in mixed-mode simulations The current mirror provides a means to set DC operation point.

Fig 4.3 Symmetrically driven DG-MOSFET Fig 4.2 An independently driven double gate (SDDG) MOSFET – IDDG It has inputs applied at the same electrical contact and has no phase difference between them.

51

4.2. MIXING PRINCIPLE

Mixers are basically frequency translation devices. They enable conversion between the high frequency (RF) and (IF) .In a basic communication system RF is used for transmission and is converted to an IF frequency. A linear device characteristic gives the same output for a given input. For a mixer the output is the modulated by the two inputs and requires a non-linear characteristic curve.

Fig 4.4 Two frequencies f1 and f2 at different operating points A and B generating outputs of different amplitudes [18]

The I-V characteristics of a typical non linear device (Fig.4.4) can be expanded according to the Taylor’s series as

2 3 4 I = a1V + a2V + a3V + a4V … (4.1) 52

If two sinusoids are fed into the mixer the equation can be re-written as

2 I = a1 (sin (w1t ) + sin (w2t)) + (sin (w1t) + sin (w2t)) (4.2)

When expanded it is the second term 2 a2* cos(w1t)* cos(w2t) that is of importance for a mixer . The harmonics can be better understood by its trigonometric identities

sin (A) sin (B) = (1/2) cos(A + B) - (1/2) cos(A - B) (4.3)

When the two sinusoidal sources with amplitudes a1 and a2 are mixed we get the following

sin(w1.t).sin(w2.t) = (1/2) {cos[t(w2 + w1)]- cos[t(w1 - w2 )]} (4.4)

It gives to the sum and difference of two frequencies ( fo + fi ) and (fo - fi) which are the two important output frequencies for a mixer to be analyzed. It is the result of the squared term in the equation (4.2) .Hence the non-linear term is of prime importance for a mixer .To work along the non linear parts of the double-gate I-V curve the operating points are adjusted (Fig.4.4). In most mixer applications the input signal is modified to a higher frequency by the local oscillator. Sweeping the reference signal over the full non- linear region of the mixer characteristic curve produces more harmonics.

With a strong a2 signal the mixer should produce strong mixed products with given two inputs but in most cases a number of additional harmonics called the “spurs” are produced along with the main signal. The mixing term produces a range of frequencies defined as m. RF + n. LO, where RF is the RF frequency, LO is the local oscillator frequency and m and n are . 53

Fig 4.5 Output spectra of a Down converting mixer [19]

For example a down converter mixer will have the frequency terms as shown in Fig.4.5. The RF-LO is the required frequency and the other frequencies not required are usually filtered out. The spurious signals are reduced in most mixers using the filtering techniques and/or the balanced mixers.

4.3. MIXER SETUP AND RESULTS

The basic device parameters for the double gate MOSFET is the same as in the case of the pass gate logic as shown previously in Table.3.1 and Fig.3.1.We assume this because, in sub-50 nm scaling mixed-signal circuits may possess many common devices .However gate work function is adjusted to ensure analog DG MOSFETs are depletion mode devices! The transient simulations described here were performed using DESSIS in hydrodynamic transport framework to account for non-stationary effects and 1st-order quantum-mechanical corrections [11].

54

Fig 4.6 Various physical parameters of DGMOSFET varied with constant gate length of 50nm. The device works in the depletion region for all the cases.

Various mixer configurations have been implemented, while varying the device physics parameters at a fixed gate length of 50nm (Fig.4.6). In the following, we study a given structural parameter, while keeping other factors same as the nominal device for comparison purposes. The AC input magnitude was found to be optimal in the mV range for improved mixer linearity. The depletion-mode DG-MOSFET mixer is biased in the saturation region and drives a current mirror load, as also given in Fig.4.1.We assume that the current mirror load may represent more realistic operating conditions, and has negligible impact in mixing ability. 55

In any case, current mirror parameters are kept same throughout our analysis, which means that the changes observed directly relates to the DG MOSFETs performance index.

Fig 4.7 The FFT of mixer drain current (Imix) Figure shows that both the sum and difference terms are obtained from the mixer, as well as higher-order

harmonics of the main signals (w1,w2)

Fig.4.7 shows the mixer output after Fourier transformation. The output drain current of the mixer is analyzed for various frequencies and it is seen that the outputs are a mixed results of the two input signals. For the sake of simulation the input frequencies was chosen to be 225 MHz and 300 MHz. The output clearly shows the sum and difference signals at 525 MHz and 75 MHz. The results established that the double gate MOSFET was indeed can be operated as a mixer with reasonable performance. Note that this spectrum is only representative of the generic device at a particular operating condition. Actual device spectra will be different from device to device. 56

The DG-MOSFET mixer was then simulated under varying physical conditions. The first one being the gate symmetry. In a DG-MOSFET the gate alignment is one of the very important parameters that should be carefully considered. The signal for various barrier heights is plotted and the mixer with the symmetrical gates or with equal barrier height difference exhibits the most linear output for the difference signal (Fig.4.8). But when asymmetry between the gates is introduced in the DG device, the difference terms initially grow in proportion to the main terms. When the asymmetry is strong (>0.5eV), this advantage disappears (Fig.4.9). Thus, we indicate that DG mixers can tolerate a remarkable amount of asymmetry, which may happen due to manufacturing tolerances or introduced at will.

Fig 4.8 The DGMOSFET mixer with symmetrical gates Fig 4.9 Asymmetry in DG mixer has beneficial impact up has the most linear mixer output. to barrier difference of 0.5 eV, beyond which the spectra is With the increase in gate asymmetry output signal does cluttered with high-order terms. not follow the input rise and produces unwanted spurs. Note that the linear decrease on the main signal is due to

lower VT.

57

In to asymmetry, other physical factors considered was how the SOI layer parameters may affect signal mixing ability of DG-MOSFETs. It is seen that a thinner body helps DG-mixer, presumably due to the better capacitive coupling between the two gates, and thus better mixing. For the relatively short 50 nm device considered here, below a body thickness of 20nm, the difference terms double, despite the main term due to higher threshold (VT) or lower trans-conductance in thin body devices (Fig.4.10). In contrast, the body doping has no significant impact in the mixer’s performance, only affecting the power distribution among higher-order terms (Fig.4.11).Since thin body DG MOSFETs cannot integrate high doping dose, it explains the negligible impact of doping. Technologically this is also good since doping lowers mobility and complicates threshold control.

Fig 4.10 Dependence of DG-MOSFET mixer on the Si body thickness. Thinner body thickness improves coupling between the two gates and leads to higher difference terms.

58

Fig 4.11 Body doping in DG-MOSFET has minimal impact on mixer performance. Impact is mainly on the main signal power distribution to the higher order terms

4.4. MODIFIED MIXER CONFIGURATION

The mixers simulated so far had only one DG MOSFET. With its mixing capabilities established, it is an interesting proposition to extend this to circuits involving more than one DG MOSFET. One such circuit was simulated using the figure as shown in fig 4.12. The main idea behind the circuit was to examine if the two DG MOSFETs put together to add two signals (w1, w2) and fed to a third DG MOSFET in the drain, will have a better output. The bottom gates for the transistors on top are grounded. With a slight variation, another circuit as shown in fig 4.13 was also simulated. In the second configuration the transistors on top have both the gates connected to the input signal. 59

Fig 4.12 A new mixer configuration.

Fig 4.13 A modified mixer with inputs at both the gates

60

Fig 4.14 Comparison of two mixer outputs normalized to the 300Mhz signal magnitude. The output spectrum for fig 4.12 is seen at the bottom and the output plot corresponding to fig 4.13 is the plot on top.

The output from the two configurations is show in the fig 4.14. The signal magnitudes are normalized with the 300 MHz signal (highest magnitude) for easy comparison. It is seen that the higher harmonics for both the cases is reduced a lot when compared to the mixer with a single transistor. Also there are two observations from these plots. The output spectrum for circuit in fig 4.12 has a reduced magnitude presumably due to the grounded bottom gates. It remains to be investigated, how the back gate bias may be used to optimize spectral signature of the mixer. With the other alternative configuration, the output spectra is also clean and has a higher magnitude for the main and difference/sum terms. This is due to the strong mixed outputs provided by the hence better cross-modulation through the transistors. 61

5

5. SUMMARY AND CONCLUDING REMARKS

5.1. SUMMARY

The current work gives a broad outline of the advantages of DG MOSFET over the conventional MOSFETs with scaling. The scaling issues were discussed initially followed by the advantages of moving over to the SOI FETs. The SOI DG MOSFET was investigated as a possible and advantageous solution to cope up with the limitations of scaling. It was further narrowed down to specific applications to explore their advantage over the conventional MOSFETs.

The present work was substantiated with examples in the digital and analog fields. The digital examples included the pass gate implementation of the DG MOSFET. The conventional transistors and the DG MOSFETs were simulated for ON resistance and it was shown that the DG MOSFET has the least resistance and the most important characteristic of a single double gate transistor behaving better than two conventional transistors in PTL logic was seen. DGMOSFET having more transconductance was implemented as a XOR gate in the transmission gate configuration and the faster performance of the DDG-MOSFET graphically demonstrated.

The fact that the DG-MOSFET has two gates making it work at different operating conditions tweaking the gate functions led to the analysis of reconfigurable structures. The simulations demonstrate the first known results of such a circuit based on the theoretical proposition by Paul Beckett. Careful balance of the rail voltages was 62 required to obtain the proper functioning of the proposed structure. Five different functionalities were obtained from a circuit with four DG-MOSFETs.

On the Analog front, a mixer was investigated using the DG-MOSFET. The input frequency signals applied to each gate of the device. The inherent gate coupling of the DG-MOSFET makes it a natural mixer. The difference and sum signals obtained from the mixer were plotted. The device physical parameters were chosen from their Id-Vg characteristics and the structural parameters were varied one at a time to study their effects on the mixer output. The body effects was found to have a considerable effect on the mixer output with the strongest difference signals obtained for a thin body (~ 10nm). When the doping was changed it has little or no effect on the output signals. The symmetry of the gate had a profound effect with the mixer withstanding asymmetry between the gates up to ~0.5eV. This can be of significant importance when the device has asymmetry due to manufacturing defects and still maintain good mixing characteristics until a tolerable limit.

5.2. FUTURE WORK

The future work in the configurable structures would be to simulate various other possible combinations to derive multiple functionalities. The current work is also based on static logic functions .It will be interesting to test dynamic logic circuits. Initial analysis of the circuit looks promising and choosing the right voltage levels will help realizing additional configurable circuits and it is currently underway for a future conference publication

On the analog side, the mixers can be extended to even more complicated circuit topologies and a balanced mixer is also in the offing. For instance, the circuit we propose in Fig.4.13 and Fig.4.12 can open new venues for further research and development. The 63 same circuit must be improved to introduce 180 º phase-shifts between the two arms of the mixer so that it can work like a balanced mixer, which can eliminate even-order terms and lead to better performance.

Apart from the above mentioned topological changes, in both the digital and analog applications the device simulator parameters can also be refined .With better precision and the 3D representation of the device structures, the details of mixer operation and precise control of back-gate based reconfiguration in logic circuits will be possible. Particularly in analog circuits, better physical and geometrical representations should allow identification of dominant AC device parameters for optimum mixing conditions. 64

6. REFERENCES

[1] G. Moore, “Progress in Digital Integrated Electronics," in IEDM Tech. Digest, pp. 11- 13, 1975.

[2] International Technology Roadmap for , 2001, http://www.itrs.net

[3] D. Frank et al., "25 nm CMOS Design Considerations,”. IEDM Technical Digest, pp.553, 1992.

[4] Nano CMOS, http://www.nanotech.re.kr/smalldoc/e_doc1_02.htm

[5] Voltage scaling, http://ece-www.colorado.edu/~bart/book/book/

[6] Nebel et al., "Low Power Design in Deep Submicron Electronics," Kluwer Academic Publishers, Boston/Dordrecht/, 1996.

[7] T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr, "Scaling Challenges and Device Design Requirements for High Performance Sub- 50nm Gate Length Planar CMOS Transistors," VLSI Tech. Digest, pp. 174, 2000.

[8] T. Douseki, et al., “Ultra-low power CMOS/SOI LSI Design for Future Mobile Systems,” Symposium on VLSI Circuits, Honolulu, Hawaii, June 2002.

[9] H.S. Wong, D. Frank, and P. Solomon, “Device Design Consideration for Double- Gate, Ground-Plane, and Single-Gated Ultra-Thin SOI MOSFETs at the 25nm Channel Length Generation,” Technical Digest of IEDM, pp. 407, 1998.

[10] H.-S. P. Wong, "Beyond Conventional Transistor," IBM Journal of Research and Development, pp. 133, 2002.

[11] ISE Systems, TCAD Suite, http://www.ise.com

[12] D. Hodges, H. Jackson and R. Saleh, “Analysis and Design of Digital Integrated Circuit,” Third Edition, McGraw-Hill, 2003 65

[13] P. Beckett, “VLSI in the Nanometer Era: Exploiting Multiple Functionality for Nano-Scale Reconfigurable Systems,” Proceedings of the 13th ACM Great Lakes Symposium on VLSI, April 2003.

[14] M. Ieong et al., “Experimental Evaluation of Carrier Transport and Device Design for Planar Symmetric/Asymmetric Double- Gate/Ground-Plane CMOSFETs,” In Electron Devices Meeting, IEDM Technical Digest. International, Washington, DC, pp. 6.1 – 6.4, 2001.

[15] G. Pei and E. C.C. Kan, “Independently Driven Double-Gate MOSFET for Mixed- Signal Circuits—Part I: Quasi-static and Nonquasistatic channel Coupling,” IEEE Trans. Electron Devices, pp.2086–2093, Dec. 2004.

[16] G. Pei and E. C.C. Kan, “Independently Driven Double-Gate MOSFET for Mixed- Signal Circuits—Part II: Applications on Cross-Coupled and Harmonic Generation,” IEEE Trans. Electron Devices, pp.2094–2101, Dec.2004.

[17] M. V. R. Reddy, D. K. Sharma, M.B. Patil and V.R. Rao, "Power-Area Evaluation of Various Double-Gate RF Mixer Topologies", IEEE Electron Device Letters, pp.664 – 666, June 2005.

[18] A Discussion of Mixers, http://www4.tpgi.com.au/users/ldbutler/MixerTheory.htm

[19] RF Mixer Design, http://www.plextek.com/papers/mixers2.pdf 66

7. APPENDICES

A. MATLAB CODE #------# To obtain the frequency spectrum of the mixer #------pi=3.14159265 ; N= 65 ; data = load('1.xmgr'); t= data(:,1); x=data(:,2); ti = 1.625e-10 : 1.53e-010 : 1e-08 ; xi = interp1(t,x,ti,'spline'); figure (1) plot (ti,xi) figure (2) plot (t,x); Fs=1/( 1.53e-010 ); % The time gap for each sample in the T domain %B = fs implies total Ny width = 2*fs Band = Fs/2; % The total no of samples in 407 thats spread across 2B nad hence f will be f = -Band: Band/32: Band; xcur = (1/N)*fft((xi-mean(xi))); figure(4) stem(f,abs(fftshift(xcur))) 67

B. DESSIS COMMAND FILE #------# # DGMOSFET # Simulating the ckt as given in nanoscale reconfigurable systems - Paul Beckett #------

# Defining dgmosfet n type Device dgmosn { Electrode{ { ="Source" Voltage=0.0 } { Name="Drain" Voltage=0.0 } { Name="GateTop" Voltage=0 Barrier=-0.35 } { Name="GateBot" Voltage=0 Barrier=-0.35 } } File{ Grid = "dg_body10_mdr.grd" Doping = "dg_body10_mdr.dat" Current = "dg_body10_sym_mdr.plt" Plot = "dg_body10_sym_des.dat" Param = "dessis.par" } Physics { Mobility( PhuMob HighFieldSaturation Enormal ) EffectiveIntrinsicDensity( OldSlotboom ) 68

Recombination( SRH(DopingDep) ) eQuantumPotential } } # Defining dgmosfet p type Device dgmosp { Electrode{ { Name="Source" Voltage=0.0 } { Name="Drain" Voltage=0.0 } { Name="GateTop" Voltage=0 Barrier=-0.65 } { Name="GateBot" Voltage=0 Barrier=-0.65 } } File{ Grid = "dg_body10_mdr1.grd" Doping = "dg_body10_mdr1.dat" Current = "dg_body10_mdr.plt" Plot = "dg_body10_des.dat" Param = "dessis.par" } Physics { Mobility( PhuMob HighFieldSaturation Enormal ) EffectiveIntrinsicDensity( OldSlotboom ) Recombination( 69

SRH(DopingDep) ) hQuantumPotential } } System { Vsource_pset v0 (n1 Vs) { pwl = (0.0e+00 0 1.5e-11 0 2.0e-11 0 4.0e-11 0 4.5e-11 1.5 6.5e-11 1.5 7.0e-11 1.5 9.0e-11 1.5 9.5e-11 0)}

Vsource_pset v1 (n2 Vs) { pwl = (0.0e+00 0 1.5e-11 0 2.0e-11 1.5 4.0e-11 1.5 4.5e-11 0 6.5e-11 0 7.0e-11 1.5 9.0e-11 1.5 9.5e-11 0)}

dgmosn dgnmos1 ("Source"=Vs "Drain"=n6 "GateTop"=n1 "GateBot" = n4 ) dgmosn dgnmos2 ("Source"=n6 "Drain"=n7 "GateTop"=n2 "GateBot" = n5 ) dgmosp dgpmos2 ("Source"=n3 "Drain"=n7 "GateTop"=n2 "GateBot" = n5) 70

dgmosp dgpmos1 ("Source"=n3 "Drain"=n7 "GateTop"=n1 "GateBot" = n4) Set (Vs = 0) Capacitor_pset c1 ( n7 Vs ){ capacitance = 1.5e-15 } Plot "nodes.plt" (time() n1 n2 n3 n4 n5 n6 n7 n8 Vs ) } File { Current= "dgmos" Output = "dgmos" } Plot{ *--Density and Currents, etc eDensity hDensity eCurrent hCurrent eMobility hMobility eVelocity hVelocity eQuasiFermi hQuasiFermi *--Fields and charges ElectricField Potential SpaceCharge eQuantumPotential *--Doping Profiles Doping DonorConcentration AcceptorConcentration *--Generation/Recombination SRH Auger AvalancheGeneration eAvalancheGeneration hAvalancheGeneration *--Driving forces eGradQuasiFermi/Vector hGradQuasiFermi/Vector eEparallel hEparalllel } Math{ 71

Extrapolate Digits = 5 Notdamped=50 Iterations=20 NewDiscretization Derivatives AvalDerivatives RelErrControl ErrRef(Electron) = 1.0E10 ErrRef() = 1.0E10 DirectCurrent } Solve{ Poisson Coupled{ Poisson } Coupled{ Poisson electron hole contact } Coupled{ Poisson electron hole contact circuit} #-ramp vdd to bias conditions: NewCurrent="drive_setup_" Quasistationary ( InitialStep=1e-4 MaxStep=0.1 Goal {Node=n7 Voltage= 1.5} Goal { Node=n3 Voltage= 1.5} Goal { Node=n4 Voltage= 1.5} Goal { Node=n5 Voltage= 1.5} ) { Coupled{ Poisson electron hole contact circuit} }

save(FilePrefix="Initialrun_") set (n3 = 1.5) 72

set (n4 = 1.5) set (n5 = 1.5) NewCurrent="finalrun_" Transient ( InitialTime=0 FinalTime=11e-11 InitialStep=1e-12 MaxStep=5e-12 Increment= 1.3 ) { Coupled{ Poisson electron hole contact circuit} Save( FilePrefix="finalrun_end" Time=(0.0;0.25;0.5;0.75;1.0) ) } }

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