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Digital and Analog Applications of Double Gate Mosfets

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Digital and Analog Applications of Double Gate Mosfets DIGITAL AND ANALOG APPLICATIONS OF DOUBLE GATE MOSFETS A thesis presented to the faculty of the Fritz J. and Dolores H. Russ College of Engineering and Technology of Ohio University In partial fulfillment of the requirements for the degree Master of Science Swetha Varadharajan November 2005 This thesis entitled DIGITAL AND ANALOG APPLICATIONS OF DOUBLE GATE MOSFETS by SWETHA VARADHARAJAN has been approved for the School of Electrical Engineering and Computer Science and The Russ College of Engineering and Technology by Savas Kaya Assistant Professor of Electrical Engineering and Computer Science Dennis Irwin, Dean, Russ College of Engineering and Technology VARADHARAJAN, SWETHA. M.S. November 2005. Electrical Engineering and Computer Science Digital and Analog Applications of Double gate MOSFETs(72pp.) Director of Thesis: Savas Kaya Moore’s law projects a continuous scaling down of devices with time. The technological trends to keep up with this empirical observation have ascertained Double gate MOSFETs as the imminent next generation transistor. This thesis investigates the digital and analog applications of the DG-MOSFETs. We illustrate the digital circuit applications of this novel device in the pass transistor logic (PTL).The ON resistance of the Double-gate MOSFET in the PTL logic shows attractive results over the conventional MOS PTL logic circuits. Also, we have implemented the PTL logic as an XOR gate and compared the device performance. The digital applications also include configurable structures based on a theoretical concept put forth by Paul Beckett. Furthermore, the analog applications include the mixer applications of DG-MOSFETs demonstrating an improved performance over the traditional MOSFET mixers. The effects of varying the physical parameters of the DG-MOSFET have been studied in a mixer. Approved: Savas Kaya Assistant Professor of Electrical Engineering and Computer Science ACKNOWLEDGEMENTS My thesis has been an extremely delightful and an enriching experience throughout. Thanks to Dr. Kaya for making my graduate research work a thoroughly enjoyable task. His genial disposition and enthusiasm has been a constant driving force and has helped me look beyond the text books. I would like to thank Dr.Janusz Starzyk for his valuable class discussions and course work in VLSI. I also want to express my appreciation to my committee members Dr.Henryk Lozykowski and Dr.Xiaoping Shen . 5 TABLE OF CONTENTS ABSTRACT ........................................................................................................................... 3 ACKNOWLEDGEMENTS ......................................................................................................... 4 LIST OF TABLES .................................................................................................................... 7 LIST OF FIGURES ................................................................................................................... 8 LIST OF ABBREVIATIONS..................................................................................................... 11 1. INTRODUCTION............................................................................................................... 12 1.1. OVERVIEW............................................................................................................... 12 1.2. CURRENT RESEARCH................................................................................................ 14 2. BACKGROUND ................................................................................................................ 16 2.1. OUTLINE .................................................................................................................. 16 2.2. DEVICE SCALING...................................................................................................... 17 2.3. SILICON ON INSULATOR ........................................................................................... 19 2.4. RF APPLICATIONS OF SOI.......................................................................................... 21 2.5. DOUBLE GATE MOSFET ............................................................................................ 22 2.6. DEVICE SIMULATOR................................................................................................. 25 2.6.1. ISE-TCAD .......................................................................................................... 25 2.6.2. MDRAW ............................................................................................................ 25 2.6.3. DESSIS .............................................................................................................. 27 2.6.4. INITIAL STEPS ................................................................................................... 27 2.6.5. PHYSICS SECTION.............................................................................................. 28 2.6.6. CIRCUIT SIMULATION........................................................................................ 29 2.6.7. INSPECT AND XMGRACE.................................................................................... 29 2.6.8. MATLAB ........................................................................................................... 29 3. DIGITAL APPLICATIONS................................................................................................... 31 6 3.1. BASIC DEVICE STRUCTURE AND SETUP..................................................................... 31 3.2. PASS GATE LOGIC .................................................................................................... 33 3.3. INITIAL RESULTS...................................................................................................... 35 3.4. XOR IMPLEMENTATION ............................................................................................ 36 3.5. RECONFIGURABLE STRUCTURES .............................................................................. 38 3.5.1. BIAS SUSCEPTIBILITY........................................................................................ 45 3.6. NEW RECONFIGURABLE XOR GATE........................................................................... 46 4. ANALOG APPLICATIONS .................................................................................................. 49 4.1. MIXER OVERVIEW.................................................................................................... 49 4.2. MIXING PRINCIPLE................................................................................................... 51 4.3. MIXER SETUP AND RESULTS..................................................................................... 53 4.4. MODIFIED MIXER CONFIGURATION .......................................................................... 58 5. SUMMARY AND CONCLUDING REMARKS......................................................................... 61 5.1. SUMMARY ............................................................................................................... 61 5.2. FUTURE WORK ......................................................................................................... 62 6. REFERENCES................................................................................................................... 64 7. APPENDICES.................................................................................................................... 66 A. MATLAB CODE ........................................................................................................... 66 B. DESSIS COMMAND FILE .............................................................................................. 67 7 LIST OF TABLES Table 2.1Comparison of the effect of scaling on MOSFET device parameters. .............. 17 Table 3.1 Device parameters used in the simulation setup............................................... 32 Table 3.2 Transitional delay comparison of transmission gate and DDG. ....................... 38 Table 3.3 Different operating conditions of gate voltages to derive various functionalities [13]............................................................................................................................ 41 Table 3.4 Biasing the back gate at different levels various functionalities can be realized. ................................................................................................................................... 47 8 LIST OF FIGURES Fig 1.1 Technology node vs. time..................................................................................... 13 Fig 1.2 MOSFET scaling trend for high performance [2] ................................................ 13 Fig 2.1 Time line of conventional MOS structure to the future transistor [4].................. 16 Fig 2.2 MOSFET device scaling [6]................................................................................. 18 Fig 2.3 A simple SOI FET ................................................................................................ 20 Fig 2.4 Structure of DGMOSFET with a thin body ( tsi = 10 nm) and a gate length (Lg) of 50 nm ........................................................................................................................ 23 Fig 2.5 Schematic band diagrams for symmetric and Asymmetric DG-MOSFET .......... 23 Fig 2.6 Variation of electron concentration with body thickness. .................................... 24 Fig 2.7 MDRAW GUI showing the structure of a DGMOSFET ....................................
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