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Indian Institute of Technology Jodhpur, Year 2015‐2016

Integrated Circuit Technology (Course Code: EE662) Lecture 1: Introduction

Course Instructor: Shree Prakash Tiwari, Ph.D. Email: [email protected] Office: 3106, Phone: 0291‐244‐9096

Webpage: http://home.iitj.ac.in/~sptiwari/ Course related documents will be uploaded on http://home.iitj.ac.in/~sptiwari/IC_Technology/

Note: Note: The information provided in the slides are taken mainly form text of Silicon VLSI Technology (Plummer, Deal, and Griffin) and Design(Jan M. Rabaey), and from other resources from internet; for teaching/academic use only 1

What is this course all about? Course Objectives: • Understanding of the fabrication methods and unit processes for device and circuit fabrication and issues in current ULSI – Unit Processes – Emerging CMOS technologies • Learning the scientific principles associated with the technologies used in VLSI fabrication. • Exposure to the processing for newer thtechno lilogies • Outcome: Understanding of fabrication processes and technology associated with it

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Books Text Books: • James D Plummer, Michael D Deal, Peter B. Griffin, Silicon VLSI Technology‐ Fundamentals, Practice And Modelling, Pearson (2009) • S.M.Sze, VLSI Technology, Tata McGraw‐Hill, 2003. • Stephen Campbell, The Science and Engineering of Microelectronics Fabrication, Oxford University Press, 1996

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Evaluation Theory • Midterm Exam 1 20%

• Midterm Exam 2 20%

• Final Exam 35%

• Lab/Assignment 25%

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ENIAC ‐ The first electronic computer (1946)

Dawn of the Transistor Age

1947: Bardeen and Brattain create point-contact transistor w/two PN junctions. Gain = 18

1951: Shockley develops junction transistor which can be manufactured in quantity.

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Introduction

Co‐recipient of Nobel prize in physics in 2000

First Point contact Transistor (1947, Bell First IC, Developed Labs) with Germanium Bardeen, Brattain, and Shockley (Seated) @ Bell independently by semiconductor, and J. Kilby (Texas Instruments) and two gold contacts Laboratories, 1948. The Nobel prize was given in 1956. R. Noyce, J. Hoerni (Fairchild separated by 50 Semiconductor), 1958. micron.

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Evolution of Electronic Devices

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1959: Planar Technology • Developed at Fairchild Semiconductor • Planar Technology (Jean Hoerni): base region is diffused into collector (substrate) and emitter region into the base • Integrated Wiring (Robert Noyce): By covering the planar transistor with an oxide, a layer of aluminum can be used on top to wire the device(s)

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1961: First Commercial Planar ICs • Based on the planar process by Hoerni and Noyce, Fairchild developed family of logic chips called resistors‐transistor logic(RTL) • Example shown is flip flop with 4 bipolar transistors and five resitistors

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Practice Makes Perfect

1961: TI and Fairchild introduced first logic IC (cost ~ $50 in quantity!). This is a dual flip‐flop with 4 transistors.

1963: Densities and yields improve. This circuit has four flip‐flops.

The First Integrated Circuits

Bipolar logic 1960’s

ECL 3-input Gate Motorola 1966

12 Digital Integrated Circuits, 2nd Ed., Rabaey.

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Practice Makes Perfect

1967: Fairchild markets the first semi‐ custom chip. Transistors (organized in columns) can be easily rewired to create different circuits. Circuit has ~150 logic gates.

1968: Noyce and Moore leave Fairchild to form Intel. By 1971 Intel had 500 employees; By 2004, 80,000 employees in 55 countries and $34.2B in sales.

The Big Bang

1970: Intel starts selling a 1k bit RAM, the 1103.

1971: Ted Hoff at Intel designed the first microprocessor. The 4004 had 4‐bit busses and a clock rate of 108 KHz. It had 2300 transistors and was built in a 10 um process.

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Exponential Growth

1972: 8080 introduced. Had 3,500 transistors supporting a byte‐wide data path.

1974: Introddiuction of the 8088. Had 6,000 transistors in a 6 um process. The clock rate was 2 MHz.

From 4 Transistors to 300‐mm Wafers Batch Fabrication

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Intel Core 2 Microprocessor

•In 2006 •143 mm2 •3 GHZ operation •65 nm CMOS technology •291 mln transistors

Integrated Circuits

22 nm CMOS

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Moore’s Law

In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.

He made a prediction that semiconductor techlhnology will dbldouble its effectiveness every 18 months

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Moore’s Law

K 1 Billion Transistors 1,000,000 !!!

100,000 Pentium® III 10,000 Pentium® II Pentium® Pro 1,000 Pentium® i486 100 i386 80286 10 8086 Source: Intel 1 1975 1980 1985 1990 1995 2000 2005 2010 Projected Transistors on Lead Microprocessors double every 2 years

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The Ever Shrinking Transistor

Using 45 nm technology, ≈ 400 transistors fit on a red blood cell!

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Design Hierarchy

SYSTEM

MODULE +

GATE

CIRCUIT

DEVICE G S D n+ n+

22 Digital Integrated Circuits, 2nd Ed., Rabaey.

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Complementary MOS Transistors (CMOS) • Fabricate PMOS and NMOS devices on the same substrate to build complementary MOS (CMOS)

• This is solved by using a p‐tub diffusion to create the background for the n‐channel devices

VDD

p A Y = A' n [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

GND

Advantages of CMOS

• Very low power consumption. • RilRail‐to‐rail voltage. Choice of the • Modular design. industry! • Reliable and robust.

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Not only Conventional CMOS

Tsai et al. 2013 (http://spie.org/) Yoo et al. High performance CMOS-compatible super- junction FINFETs for Sub-100V Applications (IEDM 2010)

25 nm thick organic Au source Au Drain semiconductor electrode electrode (30 nm) (30 nm)

Al Gate PEN substrate

3.6 nm thick AlO 1.7 nm thick Xie et al. Breakdown Voltage x (gate dielectric) HC14‐PA (SAM) Enhancement Technique for RF Process Compatible Power S. Bisoyi et al., Organic Electronics. 15, 3173 (2014) AlGaN/GaN HEMTs (ISPSD 2012)

Evolution of Electronics

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Summary • CMOS will be continuing for next many years • Proper understanding and Training for CMOS and VLSI is required • Research for new device designs and materials is necessary • Exploratory work should also be encouraged for new technologies

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For researchers…. • New Circuit Design Techniques • Novel Device Structures – Double gate MOSFETs – FinFETs • New materials for electronics – Graphene – Carbon nanotubes (CNTs) – Organic semiconductors • Cost reduction and large area circuits/systems – Organic/Flexible/printed Electronics Along with training and manpower building, exploratory research is necessary

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Lab assignment • http://www.siborg.ca/microtec.html

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